JPS61123153A - Gate-array lsi device - Google Patents

Abstract

PURPOSE:To clip an input terminal for an output circuit easily at fixed potential by fitting a polycrystalline silicon wiring, which passes through the upper section or lower section of the input terminal and is connected to a power supply, and mutually connecting the wiring and the input terminal by a contact hole. CONSTITUTION:The titled device connects input terminals, etc. as empty ones to a power supply through a contact hole and a polycrystalline silicon wiring and clips the input terminals at fixed potential. When an input terminal IN3 is brought to an empty terminal at the step of a slice in an output buffer circuit in a gate-array LSI device, the contact hole 21 connecting an aluminum wiring for the input terminal IN3 and the polycrysalline silicon wiring 20 for a clip is generated automatically through processing on a CAD, and the input terminal IN3 is clipped to the power supply VDD by the contact hole 21.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an r-) array LSI device, and in particular to a method for easily clipping the input terminals of an output circuit having a multi-input logic function to a predetermined potential using an extremely simple configuration. The present invention relates to an r-) array LSI device that enables the following.

(Conventional technology).

In a gate array LSI device, as shown in FIG.
A plurality of input/output cells 3 are arranged in a array around these internal goo cells 20. Then, an LSI device having a desired function is manufactured by connecting each of these cells with aluminum wiring or the like based on a logic circuit diagram presented by a customer or the like.

Recently, in such f-gate array LSI devices,
The human output 2777 circuit incorporated in the human output cell is provided with a logic function. FIG. 4 shows the structure of an input/output cell having such a logic function, and FIG. 5 shows the configuration of a human output 2777 circuit incorporated in this input/output cell. The input/output cells are for connection with external circuits, as shown in Figure 4. nding p4 ydo 4, human power protection circuit 5, input transistor 6, output transistor 7
, and a logic transistor 8. Among these circuit elements, the transistor is constituted by a drain or source region 9 formed by a diffusion layer or the like, and an r-to electrode 10 formed by a polycrystalline silicon layer or the like.

By connecting each of the circuit elements as described above using aluminum wiring or the like, an output buffer circuit shown, for example, in the area surrounded by a dashed line in FIG. 5 is formed. This output 8
177 circuit includes output driver 11 and 3-person NAN
Df-) circuit 12, and is a circuit having a logic function. Note that NAND r −) 12 is the sixth
Three P-channel MO8s connected in parallel as shown in the figure
) Lanzosta TPI.

TP2. It is constructed by appropriately connecting TP3 and three series-connected N-channel MOS transistors TNI, TN2, and TN3.

That is, as shown in FIG. 7, three P-channel MOS transistors TPI,
Tf"2.TP3 are connected in parallel, and the source electrodes of the transistors connected in parallel are connected to the stain source vDD by aluminum wiring.
and the commonly connected drain region to the output OU
It is connected to the output inverter as T. In addition, three N-channel MOS transistors TNI, TN2, T
N3 is connected in series. In addition, the transistor TPI,
ff-) of TNI are connected together and connected to input terminal INI, r-) of transistors TP2 and TN2 are connected together and connected to input terminal IN2, and r-) of transistors TP3 and TN3 are connected together. and is connected to input terminal IN3.

In FIG. 7, each aluminum wiring and the dirt electrode and each aluminum wiring and the drain and source regions are connected through contact holes 13, respectively.

By the way, in the output 8177 circuit as described above, 3
If one of the input terminals of the human-powered NAND r-to 12 becomes an empty terminal, especially in the CMO8 circuit, this terminal cannot be left open, and the voltage drops to a predetermined potential.
There is a need to. If a certain input terminal is in an open state, the potential of this terminal fluctuates due to noise voltage or the like, causing malfunction of the circuit and causing inconveniences such as unnecessary power consumption. For this reason, conventionally, as shown in FIG.
Stack f-4 that generates a predetermined potential by automatic wiring.
It was connected to 14.

For this reason, the conventional gate array 1. In a Sl device, when a certain terminal is to be clipped to a predetermined potential when designing wiring by automatic wiring using CAD, a cell or star that generates the predetermined potential is used.

It was necessary to define the root on the basic cell.

Since a predetermined potential is only taken out from the basic cell used as a stack dart and the transistor of the basic cell is not used, the basic cell is wasted, and the internal f-) circuit etc. is not used efficiently. There was an inconvenience that the value decreased.

(Problems to be Solved by the Invention) The present invention provides a dirt array LSI device equipped with an output circuit having a multi-input logic function. The purpose of the present invention is to enable the clipping to be performed in an appropriate manner, and to ensure that empty terminal processing is performed accurately.

(Means for Solving the Problems) According to the present invention, in an r-) array LSI device equipped with an output circuit having a multi-input logic function, the power supply A configuration is used in which a connected polycrystalline silicon wiring is provided, and the input terminal is clipped to a predetermined potential by connecting the input terminal and the polycrystalline silicon wiring to each other through a contact hole.

(Function) By using the above-mentioned means, the input terminal, etc., which is a vacant terminal, is connected to the power supply via the contact hole and the polycrystalline silicon wiring, and the input terminal is clipped to a predetermined potential. Therefore, empty terminals of an output circuit having a multi-input logic function can be easily handled by automatically generating a contact hole connecting between the polycrystalline silicon wiring and the aluminum wiring forming the input terminal.

(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIGS. 1(a) and 1(b) each show an example of an output buffer circuit in a y-dore array LSI device according to an embodiment of the present invention. The circuit shown in FIG. 1 (-) has an output connected to the output innocutor 11 connected to the dending gradation 4 and an output connected to the 3-man power N, similar to the circuit shown in FIG.
- In addition to the gate 12, a clip wiring 20 made of polycrystalline silicon or the like is provided in advance as a fixed wiring at the mask stage. The clip wiring 20 connects each input terminal INI and IN2 of the NAND r-) 12.
, IN3, and is connected to, for example, a high-level power supply vDD. The circuit pattern of the r-dore array LSI device is a fixed pattern such as transistors and f-) poles provided at the masking stage, and a /4 turn pattern such as wiring that changes according to the user's wishes at the slicing stage. However, the clip wiring 20 is composed of nine fixed turns of these circuit patterns.

In such an output cover 7A circuit, for example, if the input terminal IN3 becomes a vacant terminal at the slicing stage, a contact hole 21 connecting the aluminum wiring of the input terminal IN3 and the polycrystalline silicon wiring 20 for clipping is formed. This contact hole 21 is automatically generated by processing on CAD, and the input terminal IN3 is clipped to the power supply vDD.

Figure 1(b) shows the NAND r in Figure 1(,)
- ) 12, an output buffer circuit having No.
A polycrystalline silicon wiring a23 for a clip is provided so as to intersect with the aluminum wiring of each input terminal INI, IN2, IN3 of the board 22. However, the wiring 23 is connected to a low-level power source v88, such as a ground potential. [For example, when the input terminal IN3 becomes a vacant terminal, the input terminal INa is connected to the clip wiring 23 through the contact hole 24, thereby clipping it to a low level. It is also possible to provide two polycrystalline silicon wirings for clips, one of which is vDD and the other 'kVBB.

FIG. 2 shows the circuit structure of the output buffer circuit of FIG. 1(a) on a semiconductor chip. In the circuit structure shown in FIG. 2, the input terminals IN1. IN2
．． A polycrystalline silicon wiring 20 for clipping is provided, for example, in a direction perpendicular to IN3, and this wiring 20 is connected to the aluminum wiring of the power supply vDD through a contact hole 25. The other parts are the same as the structure shown in FIG. Then, click one of the input terminals INI, IN2, and IN3.

When connecting the contact holes 21 etc. 2>E to the connecting wiring 20 as described above at the intersection of each wiring. (Effects of the Invention) As described above, according to the present invention, Even when performing automatic wiring processing by It becomes possible to effectively utilize basic cells.

[Brief explanation of the drawing]

FIG. -) A professional circuit diagram showing the output cover and F circuit used in array LSI devices, Figure 2 is a plan view showing the specific structure of the circuit in Figure 1 (,), and Figure 3 is a general diagram. FIG. 4 is a plan view showing the structure of input/output cells in the r-) array LSI device shown in FIG. A block circuit diagram showing the output cover and F circuit used in LSI devices.
FIG. 7 is an electric circuit diagram showing a detailed configuration of an AND gate, and FIG. 7 is a plan view showing a circuit structure of an input/output cell including a conventional output buffer circuit. 1: Semiconductor chip, 2: Basic cell, 3: Input/output cell, 4
: Zenr-ing pad, 5: Input guarantee circuit, 6: Input transistor, 7: Output transistor, 8: Logic transistor, 9: Diffusion layer, 10: Boot electrode, 11:
Output inverter, 12: NAND dart, 13: contact hole, 14 stack y-t, 20, 23: wiring for clip, 21.24, 25: contact hole,
22:NORr-t. Figure 1 Figure 2 Figure 4 Stack Gate Figure 6 Figure 7

Claims (1)

[Claims] An output circuit having a multi-input logic function, and a clip wiring provided at an input terminal position of the output circuit and connected to a power source, and connecting the input terminal and the clip wiring through a clip contact hole. A gate array LSI device characterized in that input terminals are clipped by.