JPS59117132A - Master slice lsi substrate - Google Patents

Abstract

PURPOSE:To prevent local wiring contact by arranging the memory region in contact with the upper side of internal wiring region with the same width as the cell array. CONSTITUTION:An input/output buffer circuit 21, an input/output buffer circuit having an input pad 22, a cell array 9, an internal wiring region having wiring region 8, a memory region 7, a temporary external terminal 23, an RAM terminal 71, a buried layer 24 connecting the circuit 21 and terminal 23 and a leadout wire 232 connecting the circuit 21 and the temporary external terminal 231 are formed on an LSI substrate 1. Since the region 7 is arranged in contact with the upper side of the internal wiring region 3 in the same width as the cell array 9, it is no longer necessary to wire bridging over the region 7 and the detour of wiring is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a master slice type LSI board equipped with a random access memory, a read-only memory, and a programmable logic array.

Conventional technology As mask slicing LSIs become more popular, LS
The number of logic circuits that can be configured inside I is increasing. For example, there is a strong tendency to not only construct logic using general gates such as NAND and NOR gates, but also incorporate programmable logic arrays (PLA) and memory functions internally to realize complex logic. It has become to.

Therefore, conventional mask-sliced LSIs consisting of only cell arrays cannot meet these requirements; random access memory (RAM), read-only memory (ROM)
), PLA (hereinafter referred to as 6 storage areas), etc., within the board. However, in the case of such a board, the wiring within the storage area is generally Because wiring is not allowed, depending on its setting position, the shape of the storage area, and its terminal position, wiring for connections that cross storage areas may be
It is necessary to bypass the outer periphery of the storage area, resulting in local wiring congestion in the surrounding area.

Another problem is that when installed in contact with the outer edge of a cell array, a large amount of wiring area is required in the peripheral area for self-wires between the external terminals of the adjacent chip and the internal block, and the wiring method becomes difficult. bring about. As LSIs become larger in scale, it becomes important for wiring to be automatically generated by a program, which deteriorates wiring performance. This shortcoming has become a major problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a mask-sliced LSI substrate that eliminates the above-mentioned drawbacks, improves the wiring between blocks, and reduces the wiring area in the periphery.

Configuration of the Present Invention One of the substrates of the present invention includes: a rectangular wiring area in which a cell array is arranged; a storage area disposed within the wiring area so as to be in contact with one side of the rectangle of the wiring area; a buffer circuit placed outside the tangent side; a terminal placed on the side opposite the tangent side of the storage area; and an embedded line buried under the storage area to connect the buffer circuit and the terminal. He had a residence.

Examples of the invention Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, a conventional irregular region (here R
A master slice LSI board 1 having an AM area) is composed of a human output buffer circuit section 2 and an internal wiring area 3. The input/output buffer circuit section 2 includes a buffer circuit 21 . It is composed of an input/output bracket 22 and a temporary terminal 23. The internal wiring area 3 has cells 4 arranged in one row m.
A cell array is installed in a column, a wiring area 5° between cell rows 6, and a row 1 column (1≦k(n)) on the cell array.

It has a storage area 7 that is the size of an array of cells 4 (1<A<m). The storage area 7 has terminals 71 installed around it. In this structure, connections across storage area 7 are
Since passage through the memory (RAM) area is not allowed, it is necessary to take a detour to the vicinity of the memory area (R, AM) 7. As a result, local wiring congestion occurs near the iRAM, causing unwired connections. To prevent this, RAM
It becomes necessary to prepare a large amount of wiring area around the periphery, and the cells 4 must be removed accordingly, which lowers the degree of integration. Referring to FIG. 2, one embodiment of the present invention includes a mask L
An input/output buffer circuit section 2 having an input/output cover sofa circuit 21 and an input/output pad 22 on the SI board 1, a cell array 9 in which cell rows 6 each consisting of a plurality of cells 4 are arranged in a matrix, and wiring around this one-hill array 9. A rectangular internal wiring area 3 having a region 8, a memory (RAM) area 7 arranged so as to be in contact with one side of the square of this internal wiring area 3, and a memory (RAM) area 7 provided on a side opposite to the tangent side of this area 7. 1 temporary terminal 23, RAM juxtaposed to this terminal 23
The memory (RAM) area 7 for connecting the terminal 71, the buffer circuit 21 and the first temporary terminal 23
Embedded line 24 embedded under the memory (RAM)
Second temporary terminals 2 arranged on the right and left sides of the area
31, and a leader line 232 connecting between the buffer circuit 21 and the second temporary terminal. The memory (RAM) area 7 has the same width as the cell array and is installed in contact with the upper side of the internal wiring area 3.
The terminals 71 of the memory (RAM) area 7 are arranged side by side on the lower side of the memory (RAM) area 7.
It is connected to the embedded line 24 in the area 7, and is connected to the memory (RAM).
) are placed side by side on the lower side of area 7. RAM area 7
The temporary terminals 231 near the left and right sides of
32, the line extends to the bottom line of the RAM area 7.

In the embodiment B, there is no need for wiring across the RAM area 7 υ, and no wiring detours occur. That is,
Wiring performance can be improved without causing local wiring congestion. Furthermore, since the wiring between the temporary part terminal and the internal block is achieved by passing through the buried line 24, the setting of the wiring area 8 around the cell array is not necessary on the side where the RAM area 7 contacts. The wiring area can be reduced (1), and the disadvantage that the wiring length becomes longer than the core thickness by detouring around the surrounding area can also be solved at the same time.

The present invention has been described above with respect to one preferred embodiment thereof, but it is merely an illustrative example, and the present invention is not limited only to the embodiment described herein. It is a cycle layer.

For example, the setting position 1 of the RA Ivi area may be any of the four sides of the internal wiring area.

Effects of the Invention The present invention has a configuration that eliminates wiring that detours around irregular areas of RAM, 110M, and PLA%, thereby preventing extremely long wiring and local wiring congestion, and improving wiring efficiency. It has the effect of improving the

[Brief explanation of the drawing]

FIG. 1 shows a mask slice L with a conventional RAM area.
The SI board and FIG. 2 are diagrams showing an embodiment of the present invention. 1 and 2, 1...mask slice LSI board, 2... input/output buffer circuit section, 21... buffer allopath, 22...・
Input/output pad, 23...Temporary external terminal, 231.
...Temporary external terminals near the left and right sides of the RAN area,
232...Leader lines up to 231, 24...
...Push-in wire for drawing out temporary external terminals, 3...Internal wiring area, 4...Cell, 5...Wiring area, 6...Cell Row, 7...-RA, M
Area, 71...RAM terminal, 9...Wiring area around cell array, 9...Cell array. (b)1 Figure 2

Claims (1)

[Scope of Claims] A rectangular wiring area in which a cell array is arranged, a storage area arranged within the wiring area so as to be in contact with one side of the rectangle of the wiring area, and a storage area located outside the tangent side of the wiring area and the storage area. at least one buffer circuit disposed; - at least one terminal disposed on a side opposite to a tangent side of the storage area; embedded under the storage area so as to connect the buffer circuit and the terminal; 1. A mask sliced LSI substrate comprising at least one embedded line.