JPH0691157B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0691157B2 JPH0691157B2 JP62028510A JP2851087A JPH0691157B2 JP H0691157 B2 JPH0691157 B2 JP H0691157B2 JP 62028510 A JP62028510 A JP 62028510A JP 2851087 A JP2851087 A JP 2851087A JP H0691157 B2 JPH0691157 B2 JP H0691157B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- output buffer
- power supply
- area
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に関し、特に標準的回路機
能を予かじめハード・ブロックとしそれらの組合せによ
って任意の論理回路を構成する半導体装置に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor device in which a standard circuit function is preliminarily set as a hard block and an arbitrary logic circuit is formed by a combination thereof. .
近年、ディジタル半導体装置にはマスター・スライスの
設計思想で製造されるものが多い。特に準専用半導体集
積回路装置では低価格、小形化および信頼性の向上に大
きく寄与するのでマスター・スライス方式によるものが
一般的となっている。In recent years, many digital semiconductor devices are manufactured according to the master slice design concept. In particular, in the semi-dedicated semiconductor integrated circuit device, the master slice method is generally used because it contributes to a low price, downsizing, and reliability improvement.
一般に、自動設計ツールを用いた半導体装置では内部セ
ル配列は基板の内陸部に、また、入出力バッファ回路は
基板の周辺部にそれぞれ配置するようレイアウトされ入
出力バッファ回路に対する電源供給配線は基板周辺を一
周するように切れ目なく配線される。Generally, in a semiconductor device using an automatic design tool, the internal cell array is laid out in the inland part of the board, and the input / output buffer circuit is arranged in the peripheral part of the board. It is wired so that it goes around once.
通常、この電源供給配線は自動設計の取扱い対象外とす
るべく配設される入出力バッファ・ブロックの数とは関
係なく全てに渡ってほぼ同一パターンが採用され基板周
辺を切れ目なく一周するように配線される。Normally, this power supply wiring has almost the same pattern regardless of the number of input / output buffer blocks that are arranged to be excluded from the handling of automatic design, so that it makes a round circuit around the board without interruption. Wired.
しかしながら、LSI機能の種類如何によって周辺部に配
設すべき入出力バッファのブロック数に変化がおこる。
この際、多くの入出力信号が必要であるとか入出バッフ
ァに大きな能力が要求されるなどによりブロック数が増
えれば基板周辺部の配列領域を拡大せざるをえず、内部
セルの配列領域との間に必要以上の隙間を生ずる。逆に
所要数が少なくて済む場合は基板周辺部に所謂デット・
スペースが生じ基板面積の利用率を低下せしめるように
なる。However, the number of blocks of the input / output buffer to be arranged in the peripheral portion changes depending on the type of LSI function.
At this time, if the number of blocks increases due to the large number of input / output signals required or the large capacity of the input / output buffer, the array area in the peripheral area of the substrate must be expanded, and the array area of the internal cells must be expanded. There is a gap more than necessary between them. On the contrary, when the required number is small, the so-called dead
Space is generated and the utilization rate of the substrate area is reduced.
本発明の目的は、上記の情況に鑑み、入出力バッファ・
ブロックの配設されない基板周辺のデッド・スペースの
利用率を高めた半導体集積回路装置を提供することであ
る。In view of the above situation, an object of the present invention is to provide an input / output buffer,
It is an object of the present invention to provide a semiconductor integrated circuit device in which the utilization rate of the dead space around the substrate where no block is arranged is increased.
本発明によれば、半導体集積回路装置は、半導体基板と
前記半導体基板の内陸部および周辺部にそれぞれ配置さ
れる内部セル配列領域および入出力バッファ・ブロック
領域と前記入出力バッファへの電源供給配線とを含んで
成り、前記電源供給配線は入出力バッファ・ブロック領
域の縁端部においてそれぞれ折返す閉回路を形成し前記
縁端部の２つの間に挟まれる少なくとも一つの基板周辺
領域内に前記内部セル配列領域を拡大形成せしめること
を含む。According to the present invention, a semiconductor integrated circuit device includes a semiconductor substrate, an internal cell array region and an input / output buffer / block region, which are respectively arranged in an inland portion and a peripheral portion of the semiconductor substrate, and a power supply wiring for the input / output buffer. The power supply wiring forms closed loops at the edges of the input / output buffer block area, and the power supply wiring is provided in at least one substrate peripheral area sandwiched between the two edges. Enlarging and forming the internal cell array region.
すなわち、本発明によれば、入出力バッファ・ブロック
が配設されず基板周辺にデッド・スペースを生じている
場合の電源供給配線は従来の如く周辺部を切れ目なしに
一周することなく、入出力バッファ・ブロック領域の各
縁端部においてそれぞれ折返す閉回路を形成するように
配線される。That is, according to the present invention, when the input / output buffer block is not provided and a dead space is generated in the periphery of the substrate, the power supply wiring does not go around the peripheral portion seamlessly as in the prior art, Wiring is performed so as to form a closed circuit that is folded back at each edge of the buffer block region.
このように電源供給配線が入出力バッファ・ブロックの
形成領域毎に分離されて配線されると、互いに離間した
２つの入出力バッファ・ブロック間の基板周辺領域には
電源供給配線は全く配線されない。従ってこの基板周辺
領域内に内部セル配列領域を支障なく拡大形成せしめる
ことができ、従来デッド・スペースとして放置されてい
た領域を有効に活用せしめ得る。When the power supply wiring is separated and wired for each input / output buffer block formation region, no power supply wiring is provided in the substrate peripheral area between the two input / output buffer blocks separated from each other. Therefore, the internal cell array region can be enlarged and formed in the peripheral region of the substrate without any trouble, and the region left as a dead space in the past can be effectively used.
以下図面を参照して本発明をより詳細に説明する。Hereinafter, the present invention will be described in more detail with reference to the drawings.
第１図は本発明の一実施例を示す平面図である。本実施
例によれば、本発明半導体装置は、半導体基板１と、半
導体基板１の内陸部に形成される内部セル配置領域２
と、半導体基板１の周辺部に形成される入出力バッファ
・ブロック領域３と、入出力バッファ・ブロック領域３
の端縁部a,bにおいてそれぞれ布設が終了する電源供給
配線4,5と、電源供給配線4,5にそれぞれ接続される一対
の電源供給端子6,7と、入出力バッファ・ブロック領域
３の外側に配設される複数個のパッド電極８とを含む。FIG. 1 is a plan view showing an embodiment of the present invention. According to the present embodiment, the semiconductor device of the present invention includes a semiconductor substrate 1 and an internal cell arrangement region 2 formed in an inland portion of the semiconductor substrate 1.
And an input / output buffer / block area 3 formed in the peripheral portion of the semiconductor substrate 1, and an input / output buffer / block area 3
Of the input / output buffer / block area 3 and the power supply wirings 4,5 whose laying ends at the end edges a and b of the power supply wirings 4, the pair of power supply terminals 6 and 7 connected to the power supply wirings 4,5, respectively. It includes a plurality of pad electrodes 8 arranged outside.
本実施例は半導体基板１の右端周辺部に入出力バッファ
・ブロック領域３が形成されない場合を示す。この場合
は電源供給配線4,5は入力バッファ・ブロック領域の端
縁部ａおよびｂにおいてそれぞれ布設が終了し、折返し
閉回路が形成される。従って、２つの端縁部a,bの間に
挟まれる周辺部領域には内部セル配置領域２が拡大形成
される。尚第１図及び以下で説明する第２図、第３図に
於て電源供給配線は二重線で模式的に描かれており、一
般的な実際の配線パターンを表わすものではない。実際
には、入出力バッファ・ブロック領域のほとんど全面を
被う巾広の配線が布設される。In this embodiment, the input / output buffer block region 3 is not formed in the peripheral portion of the right end of the semiconductor substrate 1. In this case, the power supply wirings 4 and 5 have been laid at the edge portions a and b of the input buffer block area, respectively, and a folded closed circuit is formed. Therefore, the internal cell arrangement area 2 is enlarged and formed in the peripheral area sandwiched between the two edge portions a and b. In FIG. 1 and FIGS. 2 and 3 described below, the power supply wiring is schematically drawn by a double line and does not represent a general actual wiring pattern. In practice, a wide wiring is laid to cover almost the entire area of the input / output buffer / block area.
第２図は本発明の他の実施例を示す平面図である。本実
施例によれば半導体基板１の４隅に入出力バッファ・ブ
ロック領域3a、3b、3c、3dがそれぞれ離間して形成され
た場合が示されている。この場合には電源供給配線は4
a,5a〜4d5dの如く入出力バッファ・ブロック領域毎にそ
れぞれの端縁部a1,b1〜a4,b4において配線布設が終了
し、２つの互いに対向する縁端部（例えばa1〜b4）の間
に挟まれる周辺部領域には内部セル配置領域２がそれぞ
れ拡大形成される。FIG. 2 is a plan view showing another embodiment of the present invention. According to this embodiment, the case where the input / output buffer block regions 3a, 3b, 3c and 3d are formed at the four corners of the semiconductor substrate 1 so as to be separated from each other is shown. In this case, the power supply wiring is 4
a, 5a to 4d5d, the wiring laying is completed at the respective edge portions a 1 , b 1 to a 4 , b 4 for each input / output buffer / block area, and two edge portions (for example, a 1 The internal cell placement regions 2 are enlarged and formed in the peripheral region sandwiched between (b 4 ) to b 4 ).
以上２つの実施例から明らかなように本発明によれば従
来放置されていた基板周辺のデッド・スペースには内部
セル配置領域２を延延形成できるので基板面の無駄を省
き利用効率を向上させることができる。As is apparent from the above two embodiments, according to the present invention, the internal cell placement region 2 can be extendedly formed in the dead space around the substrate which has been conventionally left unattended, so that the waste of the substrate surface is eliminated and the utilization efficiency is improved. be able to.
第３図は従来技術によるチップレイアウトの平面図で本
発明の効果をより具体的に説明する目的で示したもので
ある。この第３図には２つの入出力バッファ・ブロック
領域3e,3fがそれぞれ分離されて設けられた場合が示さ
れているが電源供給配線4,5が周辺部を一周するように
切れ目なく配設されているので、機能回路を全く形成す
ることができない所謂デッド・スペース9a,9bが縁端部a
5,b6およびa6,b5間にそれぞれ一つづつ生じる。すなわ
ち、機能回路の形成には全く寄与しない放置領域を生じ
るので基板の利用効率を著しく低下せしめる。本発明に
よればこのデッド・スペース9a,9bには内部セル配列領
域２がそれぞれ拡大形成され内部セル配列領域２の回路
機能収容能力を増加せしめ得る。FIG. 3 is a plan view of a chip layout according to the prior art and is shown for the purpose of more specifically explaining the effects of the present invention. FIG. 3 shows the case where the two input / output buffer / block areas 3e and 3f are provided separately, but the power supply wirings 4 and 5 are arranged so as to make a round around the peripheral portion. Therefore, the so-called dead spaces 9a and 9b where no functional circuit can be formed are formed at the edge a.
One occurs between 5 , b 6 and a 6 , b 5 . That is, since a leaving region that does not contribute to the formation of the functional circuit is generated, the utilization efficiency of the substrate is significantly reduced. According to the present invention, the internal cell array region 2 is enlarged and formed in the dead spaces 9a and 9b, so that the circuit function accommodation capacity of the internal cell array region 2 can be increased.
以上詳細に説明したように、本発明によれば、入出力バ
ッファ・ブロック領域の形成されていない基板の周辺部
領域を内部セル配置領域として利用でき従来の如き所謂
デッド・スペースを生ぜしめることがないので、基板の
利用効率を高めると共に内部セル回路機能収容能力の大
きな半導体装置の実現に顕著なる効果を奏し得る。As described in detail above, according to the present invention, the peripheral area of the substrate in which the I / O buffer block area is not formed can be used as the internal cell arrangement area, and a so-called dead space as in the prior art can be produced. Therefore, it is possible to improve the utilization efficiency of the substrate and achieve a remarkable effect in realizing a semiconductor device having a large internal cell circuit function accommodating capacity.
第１図は本発明の一実施例を示すチップレイアウトの平
面図、第２図は本発明の他の実施例を示すチップレイア
ウトの平面図、第３図は従来技術によるチップレイアウ
トの平面図である。 １……半導体基板、２……内部セル配列領域、3,3a〜3f
……入出力バッファ・ブロック領域、4,5,4a〜4d,5a〜5
d……電源供給配線、a,b,a1〜a5，b1〜b6……入出力バ
ッファ・ブロック領域の縁端部、6,7……電源供給端
子、８……パッド電極、9a,9b……デッド・スペース。FIG. 1 is a plan view of a chip layout showing one embodiment of the present invention, FIG. 2 is a plan view of a chip layout showing another embodiment of the present invention, and FIG. 3 is a plan view of a chip layout according to the prior art. is there. 1 ... Semiconductor substrate, 2 ... Internal cell array region, 3, 3a to 3f
...... Input / output buffer / block area, 4,5,4a to 4d, 5a to 5
d ... Power supply wiring, a, b, a 1 to a 5 , b 1 to b 6 ... Edge portion of input / output buffer block area, 6, 7 ... Power supply terminal, 8 ... Pad electrode, 9a, 9b ... Dead space.
Claims (1)
び周辺部にそれぞれ配置される内部セル配列領域および
入出力バッファ・ブロック領域と前記入出力バッファへ
の電源供給配線とを含んで成り、前記電源供給配線は入
出力バッファ・ブロック領域の縁端部においてそれぞれ
折返す閉回路を形成し、前記縁端部の２つの間に挟まれ
る少なくとも１つの基板周辺領域内に前記内部セル配列
領域を拡大形成せしめたことを特徴とする半導体集積回
路装置。1. A semiconductor substrate, an internal cell array region and an input / output buffer block region, which are respectively arranged in an inland portion and a peripheral portion of the semiconductor substrate, and a power supply wiring to the input / output buffer, The power supply wiring forms a closed circuit that folds back at each edge of the input / output buffer block area, and expands the internal cell array area in at least one substrate peripheral area sandwiched between the two edges. A semiconductor integrated circuit device characterized by being formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62028510A JPH0691157B2 (en) | 1987-02-09 | 1987-02-09 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62028510A JPH0691157B2 (en) | 1987-02-09 | 1987-02-09 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63196060A JPS63196060A (en) | 1988-08-15 |
| JPH0691157B2 true JPH0691157B2 (en) | 1994-11-14 |
Family
ID=12250673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62028510A Expired - Lifetime JPH0691157B2 (en) | 1987-02-09 | 1987-02-09 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691157B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06326194A (en) * | 1993-05-17 | 1994-11-25 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
-
1987
- 1987-02-09 JP JP62028510A patent/JPH0691157B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
|---|
| 日経マイクロデバイス［１３（昭６１−７−１）Ｐ．１１１−１２６ |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63196060A (en) | 1988-08-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |