JPH01108742A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make it possible to reduce the wiring region by a factor about 2 without losing regularity, by converting simply the figure data of a composite function block. CONSTITUTION:Composite function block 1, 3 (F1, F3) and inverted composite function block 2, 4 (F2', F4') of line symmetry in the vertical direction are used. F2 and F3 are adjacent to each other. Between F1 and F2' and between F3 and F4', wiring regions 8, 9 are arranged. Terminals to be connected to external wirings are arranged on the outer periphery. These terminals are positioned at the lower side in F1 and F3, and on the higher side in F2' and F4' wiring is constituted of two layer. A first layer and a second layer are connected via contacts (X mark). Signals 5 are connected with terminals A1, A2, A3, A4 of F1, F2', F3, F4'. What is most distinctive, is that, for example, at the time of connecting A1 and A2, signal lines trace the same route as far as the wiring region 8 existing between F1 and F2, and are separated up and down on the wiring region 8 to be connected with A1 and A2. Therefore, the wiring region belonging to two composite function blocks can be commonly used. As a result, the area of wiring region can be reduced by a factor of about 2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated device having many repeated patterns on a chip.

[Conventional technology]

In order to make the systems around us more reliable, cheaper, and smaller, the wave of semiconductor integration is expanding day by day.In a system, there are multiple devices with the same mechanism, and it is necessary to control them. This type of system is surprisingly common. When a system is integrated with semiconductors, multiple complex function blocks with similar functions are lined up on a chip.

In this case, the arrangement of the multifunctional blocks has conventionally been done as shown in diagram tJ2. FIG. 2 is a diagram in which four composite function blocks 1, 2, 3.4 are arranged using two-layer wiring technology.

Arrangement II in the v1 function block! It is assumed that the area is used for intra-block wiring, and that no wiring from other areas passes over the multifunctional block. v1 function block 1, 2
, 3.4, the distribution range is 8.9, 10.11. Signal 5 is the terminal AI, A2 of each composite function block.
．． A3. A4, and signals 6.7 are also connected to the terminals of each composite function block.

(Problems to be Solved by the Invention) However, although the conventional arrangement method has regularity, it has the problem that the area of the arrangement region is large. In particular, as the number of multi-function blocks increases, the above problem becomes more serious, leading to an increase in chip size.

Therefore, an object of the present invention is to reduce the wiring area to about the same size without losing regularity by performing a simple geometrical transformation on the graphic data of a composite power block.

(Means for Solving the Problems) When arranging 2n complex function blocks on one chip, the semiconductor integrated device of the present invention has an inverted shape having vertically symmetrical (or horizontally symmetrical) graphic data with respect to the original complex function block. The composite functional blocks are arranged vertically (or horizontally) with the 2i-th (i=1.2...) being the inverted composite functional block and the 2i-1st (i=1.2...) being the composite functional block. ,
The 2i-th and 2i+1st (i=1.2...-1) multifunction blocks are placed adjacent to each other, and the wiring area is set between the 2i-1st and 2i-th (i=1.2...) multifunctional blocks. It is characterized by

〔Example〕

An embodiment of the present invention will be described with reference to FIG. There is a composite function block 1.3 (hereinafter referred to as F,,F,) and an inverted composite function block 2.4 (hereinafter referred to as F,',F,') which is vertically line-symmetrical, and F,' and F, are adjacent to each other. Ori%F1 and F! ' and F
, and between F and 7! There are I areas 8 and 9. It is assumed that the upper part of each composite function block is used for wiring between elements within the block, and is not used for wiring from outside the block. Terminals to be connected to external wiring are provided on the outer periphery of each complex function block, and in the example of Fig. 1, terminals are F, , F,
is on the bottom side, and F, J, F, and I are on the top side. Further, the wiring has a two-layer arrangement tS<for example, polysilicon-aluminum, aluminum-aluminum), and the first layer and the second layer are connected via contacts (marked with an x in the figure). Signal 5 is F 1 p
F*' + ps I Fa' terminals AI, A2.
A3. It is connected to the A4, but the most distinctive feature is the AI
, A2, the same route is followed up to the wiring area 8 between Fi and F,', and the wiring area 8 is divided vertically and connected to A1 and A2. A3. A4
When connecting to the wiring area 9, it follows the same route, but is divided into upper and lower parts above the wiring area 9 and connected to AS and A4. Similarly, the signal 6 terminals Bl, B2 . B3. The signal 7 is connected to terminals C1, C2, C3, and C4.

In other words, as shown in Fig. 2, according to the conventional arrangement method, each complex function block requires a wiring area with a capacity corresponding to the number of external IA lines, but according to the arrangement method of the present invention, two Since the 4I area attached to each composite function block can be shared, the area of the wiring area existing between each composite function block can be reduced to approximately half.

Next, the inversion of the composite function block will be explained using the third example.

The composite function block F, moved symmetrically to the straight line
*Move symmetrically to x. Terminals At and B on the lower side of F,
l, CI moves to the upper side of F% A2. B2. It becomes C2. In general, the graphics of semiconductor integrated circuits are often processed by computers, such as registering the graphics by digitizing or registering logic from a graphics terminal, and it is easy to create the line-symmetrical graphics data. Also, since the terminals move to the same X coordinate, regularity is not lost when wiring.

Finally, another embodiment of the arrangement method according to the present invention is shown in FIG. With the arrangement method shown in Figure 1, the number of composite function blocks is 4.
If the number increases, 8 pieces may be arranged vertically, or 4 pieces may be added in the same arrangement method horizontally. Whether to arrange everything vertically or add horizontally is determined by the size of the multifunctional block and the overall balance of the chip. In this case, 2゜4.12.14 is an inverted composite function block, the left half of the wiring area 8 is shared by the composite function block 1.2, the right half is shared by the composite function block 11.12, and the wiring area 8 is shared by the composite function block 11.12.
The left half of area 9 coexists with the composite function block 3.4, and the right half with the composite function block 13.14.

In this embodiment, the number of composite function blocks is an even number, but it is obvious that the present invention can be applied as is even in the case of an odd number of composite function blocks, with the exception of one at the end.

The present invention is also applicable to semiconductor integrated devices having a technology of 3Fs wiring or higher, such as polysilicon-aluminum-aluminum.

〔Effect of the invention〕

As described above, when arranging a plurality of multi-functional blocks, the present invention enables wiring areas existing between multi-functional blocks to be arranged without losing the advantage of "good regularity" that conventional arrangement methods have. This has the effect of reducing the chip area by approximately halving the area.

Furthermore, it is expected that the miniaturization of semiconductor devices will progress in the future.
In practice, the size of the wiring element is not very small due to limitations on allowable heat capacity due to current.

This dramatically increases the proportion of the wiring area in the entire chip, further increasing the effectiveness of the present invention.

[Brief explanation of the drawing]

Figure 1 is a layout W1 diagram of the inversion function block, Figure 2 is a layout diagram according to the conventional method, Figure 3 is a line-symmetrical movement diagram of the composite function block, and Figure 4 is a layout diagram of the two-dimensional inversion function block. be. 1.3... Composite function block 2.4... Inverted compound function block 8.9... Wiring area between compound function blocks 5.8.7
... External wiring or more 890 ----------------------X Figure 3 Figure 4

Claims (1)

[Claims] In a semiconductor integrated device using two-layer wiring technology, when arranging 2n identical complex function blocks including multiple element groups and their wiring on one chip, the structure is vertically symmetrical (or horizontally symmetrical) with respect to the base complex functional block. ), and the 2i (i=1, 2, . . . n)-th inverted compound function block, 2i-1 (i=1, 2, . . . )
)-th as the above-mentioned composite function block
and the 2i-th and 2i+1-th (i=1, 2
...n-1) multifunctional blocks adjacent to each other, and 2i
- A semiconductor integrated device characterized in that a wiring region is formed between a first and a 2i-th (i=1, 2, . . . ) multifunctional block.