JPS61198751A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To shorten a signal propagating time, by dividing a wiring group into wiring regions on both sides of a circuit block region, and providing wiring groups, which cross the circuit block region, in both wiring regions. CONSTITUTION:Circuit blocks 11a-11N are formed in an Si wafer. An output part is connected to signal output wirings 12. An input part is connected to signal input wirings 13. Switch elements 14 are provided at the intersections. The wirings 12 are divided into left and right wiring regions. Meanwhile, the wirings 13 are common. Namely, of the output lines from a circuit block region 10, 01, 03 and 05 are extended to the right wiring region; and 02, 04 and 06 are extended to the left wiring region. In this constitution, the number of the output lines extended to the right and left regions becomes about one half. Therefore, the length of the signal line from the output line leaving the logic circuit block to the input line 13 entering the logic circuit block again is reduced. Thus the signal propagating time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit whose chip functions are programmable.

[Technical background of the invention and its problems]

In recent years, with the demand for small-volume, high-mix products, L8Is have appeared.

(1) Circuit blocks with basic logic functions used in standard cell type LSIs are registered in advance with computer numbers, and automatic processing by the computer places and wires these circuit blocks as desired. to obtain the final product.

(2) Gate array method The basic circuits constituting the logic gates are arranged in an array in advance on top of the urchin, and the wiring pattern is determined by automatic wiring in the same way as the standard cell method, and the desired L
Obtain i9I.

Although the development period for these is shorter than LSIs that are completely hand-designed, they require mask manufacturing processes and wafer lithography using lithography technology from the end of the individual design that determines the functions of the LSI until the completion of the LSI. A processing step is required. Therefore, there is a problem in that it takes several weeks to several months from the end of individual design to the completion of the final LSI.

In response to this, the following method has been proposed by the present applicant (Japanese Patent Application No. 157718/1982).

That is, as shown in Figure @4, a plurality of circuit blocks 113゜11b, . . . are configured by one or more logical functional elements.
・1111 is pre-fabricated on the board using a dedicated IC method, and the input and output signals of each circuit block are guided onto a switch matrix that can electrically set ON and OFF states, and all of the circuit blocks are connected to each other. The output signals can be connected to all input signals via a switch element 14 such as an OM or a MOSFET with 1-bit memory. 12 is a T-shaped signal output wiring; 13 is a T-shaped signal output wiring;
is the signal input wiring.

According to this method, since it is field programmable, by writing the logic functions by hand, the user can obtain a desired LSI with high functionality extremely quickly. Furthermore, L8I can be designed by connecting the input and output signals of a logic block with a certain logic function, making it easy to understand even for designers accustomed to on-board logic design. The design is on each corner.

However, with this new method, the circuit blocks described above have become larger, and the input/output signals to the wiring area have increased.
Wiring area and switch collector are power inlet. As the wiring area increases, the output line from the circuit block force 1 turns on the switch element on the wiring area.

The wiring length is increased until the connection is controlled by the oFF state and becomes the input line of the circuit block again, which has the drawback of increasing the signal propagation delay time.

[Purpose of the invention]

The present invention is based on the LS disclosed in the above-mentioned Japanese Patent Application No. 58-157718.
L that can shorten the propagation delay time of the signal from the circuit block having the logic function of the I configuration method via the above wiring area.
The purpose is to provide SI.

[Summary of the invention]

The present invention provides wiring areas on both sides of a circuit block area,
Among the signal input wiring group and the signal output wiring group, one of the wiring groups forming a T-shape is distributed to both wiring areas, and a wiring group in a direction across the circuit block area is provided for each wiring area. Accordingly, the length of the T-shaped wiring, for example, the output line, is shortened.

〔Effect of the invention〕

When the present invention is used, the number of output lines extending to the left and right regions is approximately half that of the conventional method. Therefore, the area of the switch matrix is divided into left and right parts, and each area is about half that of the conventional case. Therefore, the wiring length of the signal line from the output line coming out of the logic circuit block to the input line entering the logic circuit block again is reduced, and the signal propagation time is shortened.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

First, the layout will be explained with reference to Figure @1.

That is, circuit blocks lla, llb, etc. are placed on the SN wafer.
.r...lln are built in, and each circuit block is composed of one or more logic functional elements, such as a 4-input NAND gate. This logic functional element has a CMOS configuration, and is a dedicated IC, that is, a standard cell system.
This can be a hand-built standard cell or a pre-wired gate array. Complex logic functional elements may be formed by combining standard cells with interconnections using a standard cell method.

The configuration of the circuit block is as follows.

■ Block with 82 4-input NAND gates
...15 songs ■ 2
Block with 4 input NAND gates

・-Tune 141 8 input NA
Block with one ND gate
・
...... 1. Block with 4 inverters...100 blocks. Block with 8-bit registers...19 blocks. Block with 2 D-type flip-flops.
・19 songs ■ Block with two 4-input AND gates ・・
...17 ■ Blocks with four 2-to-1 data selectors ...13 ■ Blocks with two 4-bit binary counters

・・・・・・ 11 pieces [F] 2
-Block with two 4-line decoders...
7 blocks■ Block with 3-8 line decoders...
3 pieces @ 4-1 Block with two selectors... 5 pieces [
Phase] Block with 8-1 selector...
4 blocks with G 8-bit serial parallel output shift registers... 3 blocks [
Phase] Block with 8-bit parallel input and serial output shift registers...3 pieces @1
Block with 8-bit serial input/serial output shift register 2 blocks ■ Block with 2 monostable multivibrators

・・・・・・ 4 [phase] Block with 4 2-input OR gates ・・・・・・ 4 [phase] Block with 84 2-input NOR gates
・・・・・・ 3 I solid ■ AN
Block with two D-OFt inverters...
31 fixed■ 64-bit RAM block ・River... 3 pieces 0
2 input EXCLUSIV[-OR'7'-t%
Block with 4... 2 [phase] 4-bit comparator block...
3 pieces [phase] Block with 2 flip-flops on J-... 4 pieces■ 9-bit even/odd parity generator/checker block...... 3 pieces■
4-bit binary full adder block...2 pieces ■ 2
Block with 4 input multiplexers
・・・・・・ 5 pieces @ S-R
Block with 84 latches...2 pieces■ AI,
U block Song: 1 piece @ 8-bit addressable latch block: 1 piece ■ Look-ahead carriage generator block

・・・・・・ 1 piece, that is, 274 M
It is equipped with a circuit block consisting of SI, so that an L8I with all functions can be created from one type of chip. The average number of inputs and outputs of each circuit block is 8 and 4, respectively. The input section and output section of the logic functional element serve as the input section and output section of the circuit block.

The output sections are each provided with an output buffer (not shown). And the output part is a T-shaped signal output wiring 1
2. The input sections are respectively connected to a signal input wiring @13 that intersects with this. And, at the intersection, a switch element 14
is provided.

Then, by controlling ON/OFF of the switch, a chip having a desired function can be produced.

Signal output wiring 1 forming a T-shape as shown in Figure 1
2 are divided into left and right wiring areas, and the - force signal input wiring 13 is both A. That is, circuit block area 1
Of the output lines from 0, lines 01°03.05 extend to the wiring area on the right, and lines 02, 04.06 extend to the wiring area on the left.

Figure 2 (a) shows the case where the output of 05 is transmitted as the input of IIO, and Figure 2 (b) shows the corresponding case of 05'→IIO' in Figure 4. be. (1) has a shorter wiring length by (L-7),
Therefore, wiring capacitance is reduced and signal propagation delay time can be shortened.

In the above example, the signal output wiring is T-shaped, but the signal input wiring may be T-shaped.

In addition, the signal lines that cross the circuit block area are wires that run in a straight line from one end of the chip to the other, as shown in the figure.
It may be connected to one output (or input) of the circuit block, or the same output (or input) terminal may be provided at both ends of the circuit block and extend from there to the wiring areas on both sides.

FIG. 3 is an example in which a method called the divided block method is applied. That is, the aforementioned 274 circuit blocks ① to ② are grouped into several islands and are divided into divided circuit blocks 31a,
31b, 31C...... are configured. The inside of the divided circuit block can be programmed using the method shown in FIG. Among the aforementioned phases ① to [phase], circuit blocks of the same type are distributed to each divided circuit block.

According to this method, the number of switching elements can be significantly reduced. That is, taking the divided circuit block 31a as an example, this is because the total number of input/output lines from the divided circuit block 31m is small compared to the total number of input/output lines that the circuit blocks lla to lid have, so they are not purchased. Even if there are 2 in this example,
@Similar to Figure 1, divided circuit blocks 31a, 31b, 31
Wiring areas are provided on both sides of the circuit block area formed by c..., producing the same effect as in Figure @1.

[Brief explanation of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention, and FIG. 2 is a plan view showing the effects of the present invention. If! FIG. 3 is a plan view showing another embodiment, and FIG. 4 is a plan view showing a comparative example. In the figure, 11 m, 1 l b -11n---circuit block oy
12... Wiring for signal output, 13... Wiring for signal input, 14... Switch element. Representative Patent Attorney Noriyuki Chika (and 1 other person) Figure 1 Figure 3 Figure 4

Claims (1)

[Claims] A circuit block area provided on a substrate and having a plurality of signal input sections and signal output sections, a wiring area provided on both sides of this circuit block area, and a signal input of the circuit block area provided in this wiring area. A signal input wiring group and a signal output wiring group that intersect with each other are connected to the signal input wiring group and the signal output wiring group, respectively, and switch elements are provided at the intersections of the signal input wiring group and the signal output wiring group, respectively. , T
One of the wiring groups forming a letter shape is distributed and provided in both wiring areas, and the other wiring group arranged in a direction crossing the circuit block area is provided respectively for both wiring areas. Semiconductor integrated circuit.