JPS62217632A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the skew of a clock to a large extent, by extending and forming interconnecting lines having the equal lengths from a plurality of clock buffers at the peripheral part of a substrate as clock bus lines on the substrate. CONSTITUTION:Clock buffers 6 and 7 having high driving power are provided at the central part of one side of a substrate 1. Clock buffers 8 and 9 having high driving power are provided on the central part of the other side of the substrate 1. Interconnecting lines 10, 11, 12 and 13 are formed in parallel as clock bus lines in the up and down directions along the central part, where blocks 2-5 are not present on the substrate 1. The ends of the lines 10, 11, 12 and 13 are connected to the buffers 6, 7, 8 and 9. Since the lines 10, 11, 12 and 13 have the equal length, the line interconnecting capacities are also equal, and the skew of the clock as the entire substrate becomes very small.

Description

[Detailed Description of the Invention] [Summary] In a gate array semiconductor integrated circuit, L (by forming wiring lines of equal length from each of the clock buffers provided on the side of the board layer on the substrate as a clock bus line) , which minimizes the skew of each clock across the entire board.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit, and in particular to a gate array large-scale integrated circuit (LSI) in which a plurality of blocks each having a large number of basic logic gates arranged regularly are formed on the same 1'' board.
) regarding.

When producing 6'i of various breeds of LSI cattle in a short period of time in response to the various requests of LSI users, a fully custom LSI would require a huge amount of production time and cost, so gate array LS
It is well known that I is used. In this gate array LSI, a large number of basic logic gates made of transistors, resistors, etc. are arranged regularly on the same substrate in advance, and only the wiring between them is arranged by the LSI manufacturer according to the LSI user's logic circuit information. By doing, L
It realizes the logic circuit functions required by SI users.
Also called master slice type LSI.

According to this gate array LSI, since only wiring is required, the mask design is simple and the opening period can be shortened.

Behind the gate array LSI, especially in the CMOS gate array, for example, VL exceeding 1oooo gate
In the case of SI, the clock skew (phase shift) across the entire semiconductor substrate (chip) is a factor that determines the performance of the system, so it is required to reduce this clock skew as much as possible.

[Conventional technology]

Particularly in a CMOS gate array, the signal propagation delay time that causes clock skew is dominated by wiring capacitance, and this wiring capacitance is determined by the wiring length. Therefore, by arranging circuits close to logically related circuits, we can prevent increases in wiring length and wiring capacity, improve LSI performance, and increase wiring density. In terms of layout, it was divided into, for example, four blocks.

[Problem that the invention seeks to solve]

However, for multiple 10 pieces on the same board, the LS
When a wiring pattern is created to realize the logic circuit functionality required by a user, the length of the clock bus line for each block usually differs from each other. The reduction was insufficient.

An object of the present invention is to provide a semiconductor integrated circuit with further reduced clock skew.

[Another way to solve the problem]

In order to achieve the above object, the semiconductor integrated circuit according to the present invention has the following features:
A plurality of clock buffers are provided around the periphery of the substrate, and wiring lines of equal length are formed extending from each of the plurality of clock buffers onto the substrate as clock bus lines.

[Effect]

According to the above means, since the clock buses connected to each of the plurality of clock buffers have the same length, the wiring capacitance of each clock bus becomes equal. Here, when the wiring pattern is applied to the LSI afterwards, the individual clock wiring lengths to each block will differ, but the clock delay time will depend on the overall wiring length of each clock bus rather than the individual wiring length to each block. Since it is governed by the determined wiring capacitance of each clock bus line, the skew of the clock bus can be minimized over the entire board.

〔Example〕

FIG. 1 shows a configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

In the same figure, there are four blocks 2°3.4 on the board 1.
and 5 are formed by dividing each block, and each block 2 to 5 has a large number of basic logic gates such as CMO8T transistors arranged regularly.

A large drive power (
Clock buffers 6 and 7 are provided, respectively, and clock buffers 6 and 7, which have a large drive power, are also provided at approximately the center of the other side of the board 1 opposite to the above-mentioned side. of)
Clock buffers 78 and 9 are installed, respectively.

Also, on the board 1, wiring lines 10, 11, 12 and 13 are arranged parallel to each other and along the central part of the board 1 where blocks 2 to 5 are not present, in the vertical direction as shown in FIG. It is formed. Wiring line 10, 11.12
and 13 are clock buffers 6, 7, 8 and 9.
It is connected to the. Furthermore, the wiring line io, 11.12
and 13 are selected to be equal to each other.

The gate array LSI with the above structure has blocks 2 to 5 in order to realize the logic circuit function required by the LSI user.
Each of the basic logic gates in the blocks 10 to 13 is appropriately selected and connected, and the wiring lines 10 to 13 are connected to lock buffers of the blocks 2 to 5 as necessary.

In this way, four-phase clocks are input from the outside to the clock buffers 76 to 9 of the gate array Sl obtained, and are input to all or part of blocks 2 to 5 via wiring lines 10 to 13, etc. be done.

Strictly speaking, the clock delay time is clock buffer 6
It is determined by the wiring length from ~9 to the input end of the clock buffers of blocks 2 to 5, but in reality the wiring capacity is determined by the total length of each of the wiring lines 10 to 13, which are clock bus lines -1
It can be assumed that it is determined by As described above, since the wiring lines 10 to 13 have the same length, their wiring capacitances are also the same, so that the clock skew is extremely small on the entire board.

Next, a second embodiment of the present invention will be described. FIG. 2 shows a block diagram of a half-body assembly R1 circuit according to a second embodiment of the present invention. In the figure, the same components as in Figure 1 are designated by the same reference numerals.
The explanation will be omitted.

In FIG. 2, the wiring line 15 is connected to the clock buffer 76.
A clock bus line is formed extending from the clock buffers y19, 20, 21 and 22 of blocks 2.3.4 and 5 to just before the input terminals of the clock buffers y19, 20.21 and 22 of Kokichi h1, respectively. Similarly, each of wiring lines 16.17 and 18 connects clock buffers 7.8 and 9 respectively to clock buffers 19, 20, 21 and 22 of Kokichi h1 of blocks 2.3.4 and 5.
The clock ffl lines are formed to extend to the same length immediately before all the input terminals of the clock ffl line. For clock distribution,
Is there a necessary wiring line among wiring lines 15 to 18 and a necessary lock buffer among clock buffers 119 to 22? Perform wiring processing between the input terminal and the input terminal.

According to this embodiment, the wiring line 1 as a red bus
Since the clock buffers 19 to 18 are formed to extend immediately before the input terminals of the clock buffers 19 to 22 of the blocks 2 to 5, the skew of the clocks when the board is idle can be reduced as shown in the first embodiment shown in FIG. can be reduced more than that of

Next, a third embodiment of the present invention will be described. FIG. 3 shows a configuration diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.

In the figure, the same components as in FIG. 1 are denoted by the same reference numerals, and their explanations will be omitted.

In FIG. 3, a line 24a whose one end is connected to the clock buffer 76 is formed extending downward from the center of the board 1 in the figure. In the figure, the line 24 is formed to extend in the left-right direction, and
It is connected to the line 24a at the position where it intersects the line 24a. That is, clock buffers 6 to 24 a and 2
A cross-shaped wiring line consisting of blocks 2.3.
4 and 5 as a clock bus.

Similarly, a cross-shaped wiring line consisting of 25a and 25b is formed extending from the clock buffer 7 as a clock bus line between each of the four blocks 2 to 5, and a cross-shaped wiring line consisting of 26a and 26b is formed from the clock buffer 78. , and a cross-shaped wiring line consisting of 27a and 27b from the clock buffer 9 is connected to the four blocks 2.
.about.5 are formed to extend as clock busbars.

In the m3 diagram, the wiring line 24a is formed to extend in the vertical direction.
, 25a, 26a and 27a are of equal length, and the wiring lines 24b, 25b are formed to extend in the left-right direction.
26b and 27bl; iM are of equal length.

Therefore, the four cross-shaped clocks fnl whose ends are connected to the clock buffers 6 to 9 have the same length, and the delay times of the clocks propagating through them are equal. As a result, this embodiment can also suppress clock skew for the people in blocks 2 to 5.

Next, a fourth embodiment of the present invention will be described. FIG. 4 shows a configuration diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

In the figure, the same components as in FIG. 1 are denoted by the same reference numerals, and their explanations will be omitted.

In FIG. 4, there are clock buffers on each of the four sides of the board 1. 30, 31, 32 and 33 are provided, and four clock buffers 34, 35.
6 and 37 are provided. These are clock buffers 34, 35, 36 and 3 provided on the periphery of the board 1.
7, wiring lines of equal length to each other 38.39.40
and 41 are individually preformed. Furthermore, output wiring is formed in advance to extend from each of the clock buffers 38 to 41 in all directions.

In this embodiment, wiring lines 38 to 41 serve as clock bus lines.
Since the wiring patterns are the same length, the clock skew can be further reduced compared to the above embodiments.

Therefore, this embodiment is particularly useful when applied to, for example, a CMOS gate array having four divided blocks of ioooo gates or more.

In addition, in FIG. 3, it is also possible to provide a clock buffer at each connection point of the cross-shaped wiring line.

〔Effect of the invention〕

As described above, according to the present invention, since the wiring capacitance 1i of each clock bus line is made equal, the skew of each clock on the entire board of the gate array LSI can be significantly reduced. be.

[Brief explanation of drawings]

1 to 4 are configuration diagrams showing respective embodiments of the present invention. In the figure, 1 is a board, 2 to 5 are blocks, 6 to 9, 19 to 22, 30 to 37 are L1 block buffers, 10 to 13, 15 to 18. 24a, 24b. 25 Fl, 25 b, 26 a, 26
b, 27 a. 27b, 38-41 are wiring lines. 7・'-Shoji・、Actually・″ Agent Patent attorney Igata Sada Otsu, -゛-go... A shocking surprise! Figure 2

Claims (5)

[Claims] (1) In a gate array semiconductor integrated circuit, a clock buffer (
A plurality of wiring lines (10-13, 15-1) of equal length are provided from each of the plurality of clock buffers (6-9, 30-33).
8, 24a, 24b, 25a, 25b, 26a, 26b
, 27a, 27b, 38-41) are formed extending on the substrate as clock busbars. (2) The semiconductor integrated circuit according to claim 1, wherein the wiring lines (10 to 13) of equal length are formed to extend along the center of the substrate (1). . (3) The wiring lines (15 to 18) of equal length to each other are formed to extend to just before the input ends of the clock buffers (19 to 22) of each of the plurality of blocks (2 to 5) on the substrate (1). A semiconductor integrated circuit according to claim 1, characterized in that the semiconductor integrated circuit is made of: (4) The wiring lines (24a, 24b,
25a, 25b, 26a, 26b, 27a, 27b) are formed on the substrate (1).
2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is formed to extend in a cross shape between each of the semiconductor integrated circuits. (5) The wiring lines (39 to 41) having substantially equal lengths to each other are connected to four clock buffers (34 to 37) formed in the center part of the substrate where the four blocks (2 to 5) are not located.
2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is connected to the circuit board (1) and extends in all directions from each of the four clock buffers in the center of the substrate.