JPS59161839A - Wiring array chip - Google Patents

Wiring array chip

Info

Publication number
JPS59161839A
JPS59161839A JP3716783A JP3716783A JPS59161839A JP S59161839 A JPS59161839 A JP S59161839A JP 3716783 A JP3716783 A JP 3716783A JP 3716783 A JP3716783 A JP 3716783A JP S59161839 A JPS59161839 A JP S59161839A
Authority
JP
Japan
Prior art keywords
wiring
terminals
chip
input
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3716783A
Other languages
Japanese (ja)
Inventor
Mikio Kyomasu
京増　幹夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP3716783A priority Critical patent/JPS59161839A/en
Publication of JPS59161839A publication Critical patent/JPS59161839A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

PURPOSE:To enable to effect connection between chips, such as a logic circuit element, a programmable logic array, etc., in a short time by a method wherein a plural pieces of terminal to be positioned along the peripheral part of a chip, wiring patterns to be connected to the terminals, programmable switching elements to be connected to the patterns or in between the patterns, etc., are provided on one piece of chip and the constitution is utilized as a wiring array. CONSTITUTION:One line each of wiring patterns 10-1-10-n is respectively provided in between two terminals corresponding to each other among input-output terminals a1- an and b1-bn for connection in the transversal direction and one line each of wiring patterns 11-1-11-i is respectively formed in between two terminals corresponding to each other among input-output terminals c1-ci and d1-di for connection in the longitudinal direction. Also, one line each of wiring patterns 12-1-12-m and 13-1-13-m is respectively connected to one each of any of input-output terminals e1-em and f1-fm for loop connection. Here, each of the input-output terminals is made to position along the peripheral part of a chip and programmable switching elements 14 are arranged at one each of any of the intersecting points of these patterns. Through these procedures, input-output terminals in the transversal direction or the longitudinal direction are selected and the terminals are utilized for the use of connection between chips, such as a logic circuit element, etc.

Description

【発明の詳細な説明】 技術分野 本発明は任意の回路素子間に所望の結線をなす配線アレ
イチップに関する。。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a wiring array chip that makes desired connections between arbitrary circuit elements. .

従来技術 論理回路素子やＰＬＡ（プログラマブルロジックアレイ
）が形成されたチップを複数個使用する装置類において
はチップ相互間に結線を施さねばならない。一般にチッ
プ間の結線工程には多くの工数を必要とするため、装置
等の組立てに長時間を要したり、装置コストが高くなる
などの問題がある。2. Description of the Related Art In devices using a plurality of chips each having a logic circuit element or a PLA (programmable logic array) formed thereon, wiring must be provided between the chips. Generally, the process of connecting chips between chips requires a large number of man-hours, so there are problems such as a long time required for assembling the device, etc., and an increase in device cost.

目的 本発明は、論理回路素子やＰＬＡなどのチップ間の所望
の結線を短期間でしかも安価に達成できる結線用の汎用
で標準的な配線アレイチップを提供することを目的とす
るものである。OBJECTS OF THE INVENTION It is an object of the present invention to provide a general-purpose, standard wiring array chip for wiring, which can achieve desired connections between chips such as logic circuit elements and PLAs in a short period of time and at low cost.

構成 本発明を実施例に従って説明する。第１図は一実施例で
ある１個の配線アレイチップの路線図であり、１個のチ
ップ上に形成されている。Structure The present invention will be explained according to examples. FIG. 1 is a route diagram of one wiring array chip, which is one embodiment, and is formed on one chip.

３〜ａ　及びｂ１〜ｂｎは横方向結線用の入　　　　ｎ 出力端子で対応する端子間には配線パターン１０−１〜
１０−ｎが設けられている。Ｃ１〜Ｃｉ及びｄ□〜ｄ、
は縦方向結線用の入出力端子で、この場合も対応する端
子間に配線パターン１１−１〜１１−１が設けられてい
る。８１〜０ｍ及び１０〜１ｍ４ｉループ結線川の入出
力端子であり、これらループ結線用端子は各１本の配線
パターン１２−１〜１２−ｍ及び１３−１〜１３−ｍに
接続されている。各入出力端子はチップの周縁部に設置
されている。3~a and b1~bn are input/n output terminals for horizontal connection, and wiring patterns 10-1~ are connected between the corresponding terminals.
10-n is provided. C1~Ci and d□~d,
are input/output terminals for vertical connection, and in this case also, wiring patterns 11-1 to 11-1 are provided between corresponding terminals. 81 to 0 m and 10 to 1 m are input/output terminals for loop connection rivers, and these loop connection terminals are connected to one wiring pattern 12-1 to 12-m and 13-1 to 13-m, respectively. Each input/output terminal is installed on the periphery of the chip.

横方向の配線パターンｌ０−１〜１０−ｎ及び縦方向の
配線パターン１１−１〜１１−　ｉ、並びに各配線パタ
ーン１０−１〜１０−ｎ、１１−１〜１１−ｉ、１２−
１〜１２−ｍ及び１３−１〜１３−ｍ間の交点にはプロ
グラム可能なスイッチング素子１４が配置されている。Horizontal wiring patterns l0-1 to 10-n, vertical wiring patterns 11-1 to 11-i, and each wiring pattern 10-1 to 10-n, 11-1 to 11-i, 12-
Programmable switching elements 14 are arranged at the intersections between 1 to 12-m and 13-1 to 13-m.

このスイッチング素子１４としては、ＰＬＡで使用され
ているバイポーラトランジスタ、ＦＡＭＯ８又はダイオ
ードなどのように、電気的あるいは熱的に導通状態又は
非導通状態にプログラムできる素子であれば、どのよう
なものも使用することができる。As the switching element 14, any element can be used as long as it can be electrically or thermally programmed into a conductive state or a non-conductive state, such as a bipolar transistor used in PLA, FAMO8, or a diode. can do.

本実施例の配線アレイチップにおいて、例えば端子３□
、ｂ０間で横方向に結線を施すには、スイッチング素子
１４−１が導通状態になるようにプログラムを施せばよ
い。また例えば端子Ｃ１。In the wiring array chip of this embodiment, for example, terminal 3□
, b0 in the lateral direction, it is sufficient to program the switching element 14-1 to be in a conductive state. Also, for example, the terminal C1.

ｄ□間で縦方向の結線を施すには、スイッチング素子１
４−２が導通状態になるようにプログラムを施せばよい
。また、例えばスイッチング素子１４−３を導通状態と
すれば、縦方向の端子Ｃ□と横方向の端子ｂ　間で結線
が施されるし、例えばスイッチング素子１４−４を導通
状態とすれば、ループ用端子ｅ□とｆ□間で結線が施さ
れる。このように、適当なスイッチング素子を導通状態
とすることにより、任意の端子間の結線を施すことがで
きる。To make a vertical connection between d□, switch element 1
Programming may be performed so that 4-2 becomes conductive. Further, for example, if the switching element 14-3 is in a conductive state, a connection is made between the vertical terminal C□ and the horizontal terminal b; for example, if the switching element 14-4 is in a conductive state, a loop is established. A connection is made between terminals e□ and f□. In this way, by bringing appropriate switching elements into conduction, connections between arbitrary terminals can be established.

このように本発明の配線アレイチップは、端子と、端子
に接続される配線パターンと、配線パターンあるいは配
線パターン間に接続されたスイッチング素子とを１チツ
プ上に配置して構成されており、使用にあたりスイッチ
ング素子にプログラミングを施すことにより、端子間に
任意の所望の結線を構成するものである。In this way, the wiring array chip of the present invention is configured by arranging the terminals, the wiring patterns connected to the terminals, and the wiring patterns or switching elements connected between the wiring patterns on one chip, and can be used. By programming the switching elements, any desired connection can be made between the terminals.

この配線アレイチップを複数個の論理回路素子等のチッ
プ間の結線に使用するには、論理回路素子等の・チップ
をこの配線アレイチップと共に配置し、両チップ間の端
子を接続する。配線アレイチップ内のスイッチング素子
のプログラミングは、論。理回路素子等のチップとの端
子間接続の前又は後のいずれで行なってもよい。In order to use this wiring array chip for connection between a plurality of chips such as logic circuit elements, chips such as logic circuit elements are placed together with this wiring array chip, and terminals between both chips are connected. Programming the switching elements in a wiring array chip is a matter of theory. This may be performed either before or after the connection between terminals with a chip such as a logic circuit element.

次に、この実施例の配線アレイチップを用いてＰＬＡボ
ードを構成した例を第２図に示す。Next, FIG. 2 shows an example in which a PLA board is constructed using the wiring array chip of this embodiment.

２１は基板で、その基板２１上には９個のＰＬＡアレイ
チップ２２（２２−１〜２２−９）と９個の配線アレイ
チップ２３　（２３−１〜２３−９）とが、図の如く交
互に配列されている。横方向に隣接するＰＬＡアレイチ
ップと配線アレイチップの間は横方向の配線パターン２
４により接続され、縦方向に隣接する配線アレイチップ
間は縦方向の配線パターン２５により接続されている。21 is a board, and on the board 21 are nine PLA array chips 22 (22-1 to 22-9) and nine wiring array chips 23 (23-1 to 23-9), as shown in the figure. arranged alternately. There is a horizontal wiring pattern 2 between the horizontally adjacent PLA array chip and the wiring array chip.
4, and vertically adjacent wiring array chips are connected by vertical wiring patterns 25.

また配線アレイチップ２３−３と２３−６の間、及び２
３−６と２３−９の間には、ループを構成するための配
線パターン２６が設けられている。配線アレイチップ２
３−１にはこのボートの入出力端子２８が配線パターン
２７により接続されている。Also, between the wiring array chips 23-3 and 23-6, and between the wiring array chips 23-3 and 23-6,
A wiring pattern 26 for forming a loop is provided between 3-6 and 23-9. Wiring array chip 2
The input/output terminal 28 of this boat is connected to 3-1 by a wiring pattern 27.

この例のＰＬＡボードは、複数個の標準的なＰＬ　Ａア
レイチップ２２と、複数個の標準的な配線アレイチップ
２３を一枚の基板上に配置し、それらの間を予め配線パ
ターン２４．２５．２６＋こより結線したＰＬＡの標準
的なホードであり、用途に応じてＰＬＡアレイチップ２
２及び配線アレイチップ２３にプログラムを施すように
したものである。In the PLA board of this example, a plurality of standard PLA array chips 22 and a plurality of standard wiring array chips 23 are arranged on a single board, and a wiring pattern 24, 25 is placed between them in advance. It is a standard board of PLA wired with .26+ wires, and PLA array chip 2 can be attached depending on the application.
2 and the wiring array chip 23 are programmed.

ＰＬＡは通常、プログラム可能なＡＮＤアレイとＯｋア
レイ、又はＮＯＲアレイを備え、各アレイにプログラム
を施すことにより任意の論理回路を構成することができ
るものとして知られている。A PLA is generally known to include a programmable AND array, an Ok array, or a NOR array, and can configure any logic circuit by programming each array.

しかしながら、１個のＰＬＡについては容量に限界があ
り入出力端子数にも制約がある。However, one PLA has a limited capacity and a limited number of input/output terminals.

この例のＰＬＡボードによれば、このボード基板２１の
入出力端子２８に対し、３個の配線アレイチップ２３−
１〜２３−３を介して３個のＰ　ＬＡアレイチップ２２
−１〜２２−３が並置されているので、その入出力端子
２８の数は１個のｊＬＡアレイチップ２２の入出力端子
数の３倍まで増加させることができる。According to the PLA board of this example, three wiring array chips 23-
Three PLA array chips 22 via 1 to 23-3
-1 to 22-3 are arranged in parallel, so the number of input/output terminals 28 can be increased to three times the number of input/output terminals of one jLA array chip 22.

なお、ＰＬＡアレイチップ２２と配線アレイチップ２３
の配列方法は第２図のものに限られず、例えば、両アレ
イチップを組構両方向に交互になるように配列するなど
、他の配列方法も可能である。Note that the PLA array chip 22 and the wiring array chip 23
The arrangement method is not limited to that shown in FIG. 2, and other arrangement methods are also possible, such as arranging both array chips alternately in both directions of the structure.

また、本発明の配線アレイチップを用いて結線を施すこ
とのできるチップは、第２図のＰＬＡ以外の論理回路素
子チップであってもよく、全く同様にしてチップ間の端
子接続と配線アレイチップ内のスイッチング素子のプロ
グラミングを施せばよい。Further, the chip to which connections can be made using the wiring array chip of the present invention may be a logic circuit element chip other than the PLA shown in FIG. All you have to do is program the switching elements inside.

効果 以上のように本発明の配線アレイチップはスイッチング
素子のプログラミングにより、論理回路素子等のチップ
間に所望の任意の結線を施すことができるように構成さ
れているので、この配線アレイチップを標準品として予
め用意しておき、ユーザーの要請に応じて必要な論理回
路素子等と共に配置し、チップ間の端子接続とスイッチ
ング素子のプログラミングを施すことにより、所望の論
理回路が短期間で製作でき、かつその論理回路、延いて
はそれを用いる装置等のコストが低下するなど著しい効
果を達成することができる。Effects As described above, the wiring array chip of the present invention is configured so that any desired connections can be made between chips such as logic circuit elements by programming the switching elements. The desired logic circuit can be manufactured in a short period of time by preparing it as a product in advance, arranging it with the necessary logic circuit elements according to the user's request, and connecting the terminals between the chips and programming the switching elements. Moreover, it is possible to achieve remarkable effects such as a reduction in the cost of the logic circuit and, by extension, the cost of devices using the logic circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す路線図、第２図は一実
施例の配線アレイチップをＰＬＡアレイチップと共に用
いてＰＬＡボードを構成した例を示す平面り１である。 ａ１〜ａｎ、　ｂ１〜ｂｎ、　ｃ１〜（ｉ、　ｄｔ　〜
ｄ；。 ８１〜０ｍ　、ｆ１〜ｆｍ・・・端子、１ｏ−１〜ｌ。 −ｎ、１１−１〜１１−４．１２−１−ｍ１２−ｍ。 １３−１〜１３−ｍ・・・配線パターン、１４．１４−
１〜１４−４・・・スｉ（ング素子、２１・・・基板、
２２−１〜２２−９・・・ＰＬＡアレイチップ、２３−
１〜２３−９・・・配線アレイチップ。 特許出願人　　株式会社　リコーFIG. 1 is a route diagram showing an embodiment of the present invention, and FIG. 2 is a plan view 1 showing an example in which a PLA board is constructed using the wiring array chip of the embodiment together with a PLA array chip. a1~an, b1~bn, c1~(i, dt~
d;. 81~0m, f1~fm... terminal, 1o-1~l. -n, 11-1 to 11-4.12-1-m12-m. 13-1 to 13-m... Wiring pattern, 14.14-
1 to 14-4... switching element, 21... substrate,
22-1 to 22-9...PLA array chip, 23-
1 to 23-9... Wiring array chip. Patent applicant Ricoh Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] は）周縁部の複数個の端子と、前記端子に接続された配
線パターンと、前記配線パターンあるいは配線パターン
間に接続されたプログラム可能なスイッチング素子、と
を１個のチップ上に備えたことを特徴とする配線アレイ
チップ。(b) A single chip comprising a plurality of terminals on the peripheral portion, a wiring pattern connected to the terminal, and a programmable switching element connected to the wiring pattern or between the wiring patterns. Characteristic wiring array chip.
JP3716783A 1983-03-07 1983-03-07 Wiring array chip Pending JPS59161839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3716783A JPS59161839A (en) 1983-03-07 1983-03-07 Wiring array chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3716783A JPS59161839A (en) 1983-03-07 1983-03-07 Wiring array chip

Publications (1)

Publication Number Publication Date
JPS59161839A true JPS59161839A (en) 1984-09-12

Family

ID=12490037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3716783A Pending JPS59161839A (en) 1983-03-07 1983-03-07 Wiring array chip

Country Status (1)

Country Link
JP (1) JPS59161839A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61198751A (en) * 1985-02-28 1986-09-03 Toshiba Corp Semiconductor integrated circuit
JPS61198919A (en) * 1984-09-26 1986-09-03 エキシリンク，インコ−ポレイテツド Special mutual connection for form adaptable logical array
JPS61280120A (en) * 1985-06-04 1986-12-10 ジリンクス・インコ−ポレイテツド Configurable logic array
JPH01175413A (en) * 1987-12-29 1989-07-11 Matsushita Electric Ind Co Ltd Digital device
US5371390A (en) * 1990-10-15 1994-12-06 Aptix Corporation Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits
US5377124A (en) * 1989-09-20 1994-12-27 Aptix Corporation Field programmable printed circuit board
US5400262A (en) * 1989-09-20 1995-03-21 Aptix Corporation Universal interconnect matrix array
US5448496A (en) * 1988-10-05 1995-09-05 Quickturn Design Systems, Inc. Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system
US5477475A (en) * 1988-12-02 1995-12-19 Quickturn Design Systems, Inc. Method for emulating a circuit design using an electrically reconfigurable hardware emulation apparatus
US5640308A (en) * 1991-06-14 1997-06-17 Aptix Corporation Field programmable circuit module
US6377911B1 (en) 1988-12-02 2002-04-23 Quickturn Design Systems, Inc. Apparatus for emulation of electronic hardware system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5754430A (en) * 1980-09-17 1982-03-31 Nec Corp Integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5754430A (en) * 1980-09-17 1982-03-31 Nec Corp Integrated circuit

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09261040A (en) * 1984-09-26 1997-10-03 Xilinx Inc Programmable logic device
JPS61198919A (en) * 1984-09-26 1986-09-03 エキシリンク，インコ−ポレイテツド Special mutual connection for form adaptable logical array
JPH06283996A (en) * 1984-09-26 1994-10-07 Xilinx Inc Special interconnection for logical array having adaptability to shape
JPH09261039A (en) * 1984-09-26 1997-10-03 Xilinx Inc Programmable logical device
JPS61198751A (en) * 1985-02-28 1986-09-03 Toshiba Corp Semiconductor integrated circuit
JPS61280120A (en) * 1985-06-04 1986-12-10 ジリンクス・インコ−ポレイテツド Configurable logic array
JPH01175413A (en) * 1987-12-29 1989-07-11 Matsushita Electric Ind Co Ltd Digital device
US5448496A (en) * 1988-10-05 1995-09-05 Quickturn Design Systems, Inc. Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
US5812414A (en) * 1988-10-05 1998-09-22 Quickturn Design Systems, Inc. Method for performing simulation using a hardware logic emulation system
US5796623A (en) * 1988-10-05 1998-08-18 Quickturn Design Systems, Inc. Apparatus and method for performing computations with electrically reconfigurable logic devices
US5612891A (en) * 1988-10-05 1997-03-18 Quickturn Design Systems, Inc. Hardware logic emulation system with memory capability
US5734581A (en) * 1988-10-05 1998-03-31 Quickturn Design Systems, Inc. Method for implementing tri-state nets in a logic emulation system
US5657241A (en) * 1988-10-05 1997-08-12 Quickturn Design Systems, Inc. Routing methods for use in a logic emulation system
US6377911B1 (en) 1988-12-02 2002-04-23 Quickturn Design Systems, Inc. Apparatus for emulation of electronic hardware system
US5477475A (en) * 1988-12-02 1995-12-19 Quickturn Design Systems, Inc. Method for emulating a circuit design using an electrically reconfigurable hardware emulation apparatus
US6842729B2 (en) 1988-12-02 2005-01-11 Quickturn Design Systems, Inc. Apparatus for emulation of electronic systems
US5377124A (en) * 1989-09-20 1994-12-27 Aptix Corporation Field programmable printed circuit board
US5544069A (en) * 1989-09-20 1996-08-06 Aptix Corporation Structure having different levels of programmable integrated circuits interconnected through bus lines for interconnecting electronic components
US5400262A (en) * 1989-09-20 1995-03-21 Aptix Corporation Universal interconnect matrix array
US5654564A (en) * 1990-10-15 1997-08-05 Aptix Corporation Interconnect structure with programmable IC for interconnecting electronic components, including circuitry for controlling programmable IC
US5504354A (en) * 1990-10-15 1996-04-02 Aptix Corporation Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits
US5973340A (en) * 1990-10-15 1999-10-26 Aptix Corporation Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits
US6160276A (en) * 1990-10-15 2000-12-12 Aptix Corporation Double-sided programmable interconnect structure
US5371390A (en) * 1990-10-15 1994-12-06 Aptix Corporation Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits
US5640308A (en) * 1991-06-14 1997-06-17 Aptix Corporation Field programmable circuit module

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