JPS6065625A - Master slice type semiconductor circuit device - Google Patents

Abstract

PURPOSE:To utilize effectively a conventional operating area being easily an idle area by constituting four corners of a rectangular chip as the conventional operating area and integrating the logical circuit of a Schmitt trigger circuit in this area. CONSTITUTION:The master slice type semiconductor circuit device 1 consists of plural logical cell arrays 2, plural input/output cells 3-6, a power terminal 7 and wiring areas 8, 9, and the conventional operating area 10 exists at the four corners of the device 1. The logical circuit is integrated in the conventional operating area 10. The logical circuit is the Schmitt trigger circuit. That is, an inverter 14, two-input NAND circuits 15, 16 are integrated. Moreover, an input terminal IN in the area and an output terminal OUT in the area are connected electrically to a pattern in the wiring area 8 and/or 9. Thus, the constitution of the desired logical circuit is attained in the conventional operating area 10 in this way and the cell in the logical cell array 2 is utilized efficiently.

Description

[Detailed description of the invention] (8) Technical field of the invention The present invention relates to a master slice type semiconductor circuit device.

In particular, on a quadrilateral semiconductor chip, such as an aluminum gate mask-sliced semiconductor circuit device, in which metal wiring and diffused resistors are provided perpendicularly to the wiring area, The present invention relates to a master slice type semiconductor circuit device in which a logic circuit which is generally difficult to construct but is not constructed using cells on a logic cell column is integrated on at least one of four corners.

Background and Problems of the fBl Technology The present inventors previously developed an aluminum gate mask-sliced semiconductor circuit device by arranging a metal wiring and a diffused resistor on a wiring area so as to be orthogonal to each other. We proposed that the desired wiring be achieved by making appropriate connections.

FIG. 1 shows the overall concept of such a master slice type semiconductor circuit device. In the figure, reference numeral 1 denotes a mask slice type semiconductor circuit device, 2 denotes logic cell columns constituting a basic cell column and/or a flip-flop column, 3, 3. ...3 is an input/output cell placed on the left side of the figure (the whole constitutes a cell column...
・・・・The same applies hereafter), 4.4. . . . 4 is an input/output cell arranged at the lower side in the figure; 5, 5 . . . ...5 is an input/output cell placed on the right side in the figure, 6,6...-6
are input/output cells arranged on the upper side of the figure, 7.7 are power supply terminals, 8, 8. ... is the wiring area of O-1, 9,9
゜・・・・・・ is the second wiring area, 10.10・ge...
represents the general use area according to the present invention.

Note that the wiring area 9 of the above-mentioned wiring area 2 is connected to the above-mentioned logic cell column 2゜2.
... upper end and the above input/output cell row (6, 6...)
This area corresponds to the long space between the groove shown in the figure. In addition, although the above general use area 10.10... 9 is shown with a circle mark in the binding, the circle mark does not actually exist, but the one proposed by the inventors above. In a mask slice type semiconductor circuit device, a so-called empty area exists, and this empty area can be considered to be called a general use area.

The first wiring area 8 shown in Fig. 1 and the wiring area 9 of Spear 2 include 9. Since the example is an aluminum gate master slice type semiconductor circuit device as described above, the wiring area 9 shown in Fig. 2 is The area is filled with a pattern as shown in FIG. 1 is formed and the electrical connection between the two is achieved by forming a contact window 13.
In the wiring area 9 of No. 2, there is a metal wiring 11 extending in the horizontal direction.
are provided, and a diffused resistor 12 extending vertically on the lower surface thereof is provided, and electrical coupling between the two is achieved through a contact window 13. Of course.

Needless to say, connections between patterns in the wiring area and cells in the logic cell column and input/output cells are also made as necessary.

In the case of the master slice type semiconductor circuit device proposed by the inventors as described above, the general-purpose use area lO shown in FIG. It's easy to become. On the other hand, using the cells in the logic cell column 2 described above.

For example, when trying to configure a Schmitt trigger circuit, power-on reset circuit, delay circuit, mono multivibrator, analog switch circuit, etc., a large number of cells are occupied.

In some cases, it may be extremely difficult or impossible to configure.

+Q Purpose and Structure of the Invention The present invention aims to solve the above-mentioned problems, and as described above, the general-purpose use area 10, which tends to become an empty area, so to speak.
The purpose is to make effective use of the Therefore, in the master slice type semiconductor circuit device of the present invention, logic cell rows each consisting of a basic cell row and/or one off-flip flop row are arranged with a plurality of rows apart, and the plurality of logic cell rows are Input/output cell rows are arranged on four sides in a wrap-around manner, and wiring areas are provided in gaps between the logic cell rows and gaps between the input/output cell rows and the logic cell rows. In a master slice type semiconductor circuit device having a rectangular chip.

At least one of the four corners of the rectangular chip is configured as a general use area.

The present invention is characterized in that a logic circuit that is not or is not preferably formed by a combination of logic cells forming the logic cell array is integrated on the general-purpose area. This will be explained below with reference to the drawings.

tD) Embodiment A-3 of the Invention FIG. 4 shows an embodiment of a logic circuit constructed within the general-purpose area shown in FIG. 1, and FIG. 4 is an explanatory diagram illustrating its operation.

One embodiment of the master slice type semiconductor circuit device of the present invention may also be configured as shown in FIG. That is, a plurality of logic cell columns 2. Multiple input/output cells 3, 4,
5,6. Power terminal 7. It may be considered that the device 1 has a wiring area 9 of 8 degrees A72, and general use areas 10 exist at the four corners of the device 1. Of course.

It can be considered that each wiring area 8 and 9 has a pattern as shown in FIG.

In the case of the present invention, within the general use area 10 as described above, one
For example, logic circuits as shown in Figure i3 are integrated. In the case shown in FIG. 3, the logic circuit is shown to be a Schmitt trigger circuit.

That is, the reference numeral 10 in Fig. 1 indicates the general use area shown in Fig. 1;
4 represents an inverter, and 15.16 represents a two-man NAND circuit. Further, IN is an intra-area input terminal and is electrically connected to the turn in the wiring area 8 and/or 9, and OUT is an intra-area output terminal and is electrically connected to the turn in the wiring area 8 and/or 9.
Or electrically connected to the turn in 9.

For example, when constructing a Schmitt trigger circuit as described above, the circuit has input/output characteristics regarding Vin and VolLt as shown in FIG. 4, but the inverter 14 shown in FIG.・Depending on the points,
The two-man NAND circuits 15 depend on the lower points shown in FIG. cannot be configured. Of course, this does not mean that it cannot be configured by using a large number of basic cells, but it becomes virtually impossible to configure it when considering the usage efficiency of the basic cells.

The logic circuit configured in the general-purpose area 10 is as follows.

Although not limited to the above-mentioned Schmitt trigger circuit, power-on reset circuit, delay circuit, mono-multi-by-break circuit, and analog switch, in any case, these logic circuits are connected to the power supply terminal 7 shown in FIG. 7(
It is desirable that consideration be given to making wiring possible for all terminals (terminals of basic cells and input/output cells) other than those shown in the figure (Vcc and VB2).

(E) As described in detail, according to the present invention, it is possible to configure a desired logic circuit within the general use area 10 shown in Figure 1''A71, and the cells in the logic cell row can be further expanded. It becomes possible to use it efficiently.

[Brief explanation of the drawing]

Fig. 11 of the bottle and Fig. 2 of the fan 2 represent a master slice type semiconductor circuit device which is the premise of the present invention, and an embodiment of the present invention (-14 configuration); FIG. 4 shows an explanatory diagram illustrating its operation. In the figure, 1 is a master slice type semiconductor circuit device. 2 is a logic cell column, and 3 to 6 are input/output cells. , 7 is a power supply terminal, 8 is a first wiring area, 9 is a second wiring area, 10 is a general use area, 11 is a metal wiring. 12 is a diffused resistor, 13 is a contact window, 14 is an inverter, 15.16 represents a two-person Nando circuit. Patent applicant: Fujitsu Limited, representative patent attorney Mori 1) Hiroshi (one other person) Figure 4 → V-

Claims (1)

[Claims] Logic cell columns consisting of basic cell columns and/or flip-flop columns are arranged at a plurality of column intervals, and
Input/output cell rows are arranged on four sides to surround the plurality of logic cell rows, and gaps between the logic cell rows and gaps between the input/output cell rows and the logic cell rows are provided. In a master slice type semiconductor circuit device having a rectangular chip having a wiring area, at least one corner of the four corners of the rectangular chip is configured as a general use area, and a wiring area is provided on the general use area. To. A master slice type semiconductor circuit device characterized in that a logic circuit that is not configured or is not preferably configured by a combination of logic cells constituting the logic cell array is integrated.