JPS62187356U - - Google Patents
Info
- Publication number
- JPS62187356U JPS62187356U JP7568386U JP7568386U JPS62187356U JP S62187356 U JPS62187356 U JP S62187356U JP 7568386 U JP7568386 U JP 7568386U JP 7568386 U JP7568386 U JP 7568386U JP S62187356 U JPS62187356 U JP S62187356U
- Authority
- JP
- Japan
- Prior art keywords
- central processing
- integrated circuit
- new command
- bus line
- processing units
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000011159 matrix material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Multi Processors (AREA)
Description
第１図は本考案に係る半導体集積回路素子の実
旋例を模式的に示す図、第２図は第１図に示す半
導体集積回路素子における中央演算処理装置の構
成を概略的に示す図、第３図は従来の半導体集積
回路素子を模式的に示す図である。
１……集積回路基板、２……制御部、３……演
算部、４……内部記憶部、５……バスライン制御
部、Ｃｉｊ……ＣＰＵ（中央演算処理装置）。
FIG. 1 is a diagram schematically showing an actual example of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a diagram schematically showing the configuration of a central processing unit in the semiconductor integrated circuit device shown in FIG. FIG. 3 is a diagram schematically showing a conventional semiconductor integrated circuit element. DESCRIPTION OF SYMBOLS 1... Integrated circuit board, 2... Control unit, 3... Arithmetic unit, 4... Internal storage unit, 5... Bus line control unit, Cij... CPU (Central Processing Unit).
Claims (1)
上に実装される半導体集積回路素子であつて、 上記各中央演算処理装置を縦横揃えてマトリク
ス状に配置するとともに、 互いに縦横にて隣り合う上記各中央演算処理装
置をメツシユネツトワーク状に各々接続し、 各中央演算処理装置にバスライン制御部を設け
、このバスライン制御部にてバスラインのスイツ
チング制御を行なうことにより命令実行中に新た
な命令を受けた場合にはこの新たな命令を取込ま
ず、命令実行中以外に新たな命令を受けた場合に
のみこの新たな命令を取り込むようにしたことを
特徴とする半導体集積回路素子。[Claims for Utility Model Registration] A semiconductor integrated circuit device in which a plurality of central processing units are mounted on a single integrated circuit board, and each of the central processing units is arranged vertically and horizontally in a matrix. , the above-mentioned central processing units that are adjacent to each other vertically and horizontally are connected to each other in the form of a mesh network, each central processing unit is provided with a bus line control unit, and this bus line control unit performs bus line switching control. By doing this, if a new command is received during command execution, this new command will not be imported, but this new command will be imported only if a new command is received other than during command execution. Characteristic semiconductor integrated circuit elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7568386U JPS62187356U (en) | 1986-05-20 | 1986-05-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7568386U JPS62187356U (en) | 1986-05-20 | 1986-05-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62187356U true JPS62187356U (en) | 1987-11-28 |
Family
ID=30922057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7568386U Pending JPS62187356U (en) | 1986-05-20 | 1986-05-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62187356U (en) |
-
1986
- 1986-05-20 JP JP7568386U patent/JPS62187356U/ja active Pending
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