JPS63183642U

JPS63183642U -

Info

Publication number: JPS63183642U
Application number: JP7230587U
Authority: JP
Priority date: 1987-05-14
Filing date: 1987-05-14
Publication date: 1988-11-25

Description

[Brief explanation of the drawing]

第１図は本考案の基本的構成を示すためのコン
ピユータ制御システムの概略システム構成図、第
２図は実施例に係るオフイスコンピユータのシス
テム回路図、第３図は実施例回路の作動プロセス
を示すフローチヤート、第４図は従来技術におけ
るＤＭＡ方式を採用した場合のシステム構成図、
第５図は従来技術におけるＤＭＡ実行中のバス共
有状態を示すフローチヤートである。１……ＣＰＵ、２……メモリ、３……Ｉ／Ｏ装
置Ｂ、４……ＣＰＵバス、５……Ｉ／Ｏ装置Ａ、
５ａ……Ｉ／Ｏインターフエース、６……転送用
メモリ、７……Ｉ／Ｏインターフエースのバス、
８……スイツチング回路、９……制御線、１０…
…インタラプト制御線。 Fig. 1 is a schematic system configuration diagram of a computer control system to show the basic configuration of the present invention, Fig. 2 is a system circuit diagram of an office computer according to an embodiment, and Fig. 3 shows an operating process of the embodiment circuit. Flowchart, Figure 4 is a system configuration diagram when adopting the DMA method in the conventional technology,
FIG. 5 is a flowchart showing a bus sharing state during DMA execution in the prior art. 1...CPU, 2...Memory, 3...I/O device B, 4...CPU bus, 5...I/O device A,
5a... I/O interface, 6... Transfer memory, 7... I/O interface bus,
8...Switching circuit, 9...Control line, 10...
...Interrupt control line.

Claims

[Claims for Utility Model Registration] In the DMA method of a computer control system, a CP that accesses memory and I/O devices
The U bus and the bus of the I/O interface of an I/O device that executes DMA other than the above-mentioned I/O device are separated, and a transfer memory in a memory area different from the above-mentioned memory and a transfer memory under the control of the CPU are separated. A switching circuit that switches and connects the transfer memory to the CPU bus or I/O interface bus, and a DMA
1. A DMA circuit characterized in that an interrupt control line is provided for connecting between an I/O interface of an I/O device that executes a CPU and a CPU.