JPS62162756U - - Google Patents

Info

Publication number
JPS62162756U
JPS62162756U JP4724786U JP4724786U JPS62162756U JP S62162756 U JPS62162756 U JP S62162756U JP 4724786 U JP4724786 U JP 4724786U JP 4724786 U JP4724786 U JP 4724786U JP S62162756 U JPS62162756 U JP S62162756U
Authority
JP
Japan
Prior art keywords
microprocessor
memory
control device
access control
memory access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4724786U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4724786U priority Critical patent/JPS62162756U/ja
Publication of JPS62162756U publication Critical patent/JPS62162756U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案を実施したメモリ・アクセス制
御装置の構成ブロツク図、第2図は本考案を実施
した他の例のメモリ・アクセス制御装置のブロツ
ク図、第3図は第2図に示したメモリ・アクセス
制御装置の動作を表わすタイム・チヤート、第4
図は従来のメモリ・アクセス制御装置の構成ブロ
ツク図、第5図はデータ・ホールド・タイムを説
明するための図である。 1,1,1…マイクロプロセツサ、2…メ
モリ、3…制御回路、4,4,4…スリー・
ステート・バツフア、Bd,Bd,Bd…デ
ータ・バス。
FIG. 1 is a block diagram of the configuration of a memory access control device embodying the present invention, FIG. 2 is a block diagram of another example of a memory access control device embodying the present invention, and FIG. 3 is shown in FIG. Time chart representing the operation of the memory access control device, No. 4
This figure is a block diagram of a conventional memory access control device, and FIG. 5 is a diagram for explaining data hold time. 1, 1 1 , 1 2 ...Microprocessor, 2...Memory, 3...Control circuit, 4, 4 1 , 4 2 ...Three.
State buffer, Bd, Bd1 , Bd2 ...data bus.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データ処理を行なうマイクロプロセツサと、こ
のマイクロプロセツサにデータ・バスを介して接
続されてこのマイクロプロセツサとデータの授受
が行なわれるメモリとを有するメモリ・アクセス
制御装置において、前記データ・バス上の前記マ
イクロプロセツサと前記メモリとの間に、ハイ・
インピーダンス状態を保持するバツフア回路を設
けたことを特徴とするメモリ・アクセス制御装置
In a memory access control device having a microprocessor that processes data, and a memory that is connected to the microprocessor via a data bus and that exchanges data with the microprocessor, between the microprocessor and the memory.
A memory access control device comprising a buffer circuit that maintains an impedance state.
JP4724786U 1986-03-31 1986-03-31 Pending JPS62162756U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4724786U JPS62162756U (en) 1986-03-31 1986-03-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4724786U JPS62162756U (en) 1986-03-31 1986-03-31

Publications (1)

Publication Number Publication Date
JPS62162756U true JPS62162756U (en) 1987-10-16

Family

ID=30867672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4724786U Pending JPS62162756U (en) 1986-03-31 1986-03-31

Country Status (1)

Country Link
JP (1) JPS62162756U (en)

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