JPH04214668A - Master slice method semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the wiring load by reducing a wiring area remarkably in a wiring region. CONSTITUTION:Inverters 11a-11c, each provided with a contact for input, a contact for output and a contact for injector, are so set side by side that the contacts for injector 5a-5c may be located on the same side to constitute a single basic cell 10. On this basic cell, wires are run between the contacts for input and the contacts for output to build up a basic logic circuit.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a master slice type semiconductor integrated circuit device using IIL logic circuit elements.
In particular, the present invention relates to a master slice type semiconductor integrated circuit device in which basic cells for integrated circuit design are improved.

0002

[Prior Art] Generally, using IIL logic circuit elements,
When constructing a master slice type semiconductor integrated circuit device, a three-output type inverter is often used as a basic cell for integrated circuit design.

FIG. 5 shows an example of a conventionally used basic cell, and a master slice type semiconductor integrated circuit device is constructed by arranging such basic cells side by side. That is, the basic cell 1 consists of only one IIL inverter 2, and a circuit is configured with this and a wired AND. That is, a desired wiring pattern is formed on a plurality of contacts 3 formed on the IIL inverter 2 using wiring aluminum 4, and the ends thereof are drawn out into the wiring area. In addition, at the end of the IIL inverter 2,
An injector contact 5 is formed, and an INJ line 6, which is a power supply wiring, is formed.

0004

However, the conventional master slice type semiconductor integrated circuit device using the basic cell as described above has the following problems to be solved. That is, the basic cell 1 consists of only an inverter,
Since the circuit is configured with this and wired,
Even in order to configure a basic logic circuit, it is necessary to connect elements in a wiring area, and complicated wiring is required within the wiring area. Since this wiring is loaded with the normal wiring, the wiring area increases and the area efficiency in the wiring area decreases. Furthermore, since the wiring between each element becomes long, there is also a drawback that the operating speed decreases. Furthermore, since the portion within the basic cell 1 used for drawing out the wiring to the outside (wiring area) becomes large, the area efficiency within the cell becomes extremely poor. Furthermore, automated algorithms for placement and wiring commonly used in MOS logic circuits and the like are difficult to use, and even if they are available, the wiring efficiency is not good. Furthermore, since the circuit is configured with an inverter and a wired circuit, it is necessary to rewrite the circuit for IIL, and there is also the drawback that it takes a long time to design a circuit that meets the needs of the customer.

The present invention was proposed in order to solve the above-mentioned drawbacks of the prior art, and its purpose is to use a basic cell with good area efficiency and easy automation of placement and wiring. An object of the present invention is to provide a master slice type semiconductor integrated circuit device in which the wiring load applied to the wiring area is reduced.

[0006]

[Means for Solving the Problems] A master slice type semiconductor integrated circuit device of the present invention includes a plurality of inverters each having an input contact, an output contact, and an injector contact such that the injector contacts are on the same side. The device is characterized in that they are arranged in parallel to form a single basic cell, and on this basic cell, the input/output contacts are connected to form a basic logic circuit.

[0007]

[Operation] The operation of the present invention having the above-mentioned structure is as follows.

That is, since the basic logic circuit can be constructed within the basic cell, the only wiring in the wiring area is the wiring that connects the logic circuits. Furthermore, since the basic logic circuit is connected with the shortest wiring distance, the operating speed of the circuit is improved and the area efficiency within the basic cell is also improved. Furthermore, since the basic elements are composed of standard logic circuit elements, automated placement and wiring algorithms used in MOS and the like can be used.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be specifically described below with reference to FIGS. 1 to 4. Note that the same members as those of the conventional type shown in FIG. 5 are designated by the same reference numerals, and the description thereof will be omitted.

In this embodiment, as shown in FIG.
The basic cell 10 is configured by arranging three first to third IIL inverters 11a, 11b, 11c in parallel, and
Injector contacts 5a, 5b of each inverter,
5c are arranged on the same side, and by connecting these with wiring aluminum, an INJ line 12, which is a power supply wiring, is formed.

Note that each inverter 11a to 11c includes:
Three output contacts 13 and one input contact 14 are formed respectively.

In the master slice type semiconductor integrated circuit device of this embodiment having such a configuration, a basic logic circuit can be configured within the cell as described below. That is, in the case of the basic cell 10 configured with three inverters as shown in FIG. 1, the basic logic circuits that can be realized within the cell include two-input AND, NAND, OR,
There are NOR, buffer, etc. As an example of such a basic logic circuit, FIG. 3 shows the wiring state of each inverter in a cell when a NOR is configured. That is, the input contacts 14a, 1 of the second and third inverters 11b, 11c
4c, separate wiring patterns (input 1, input 2) are formed using wiring aluminum 15, and the ends thereof are drawn out to the wiring area. On the other hand, the output contacts 13 of the second and third inverters 11b and 11c
A wiring pattern (output) is formed in b and 13c to connect them so that one of the inverters can be selected, and the ends thereof are drawn out to the wiring area. Further, FIG. 3 shows the basic cells forming the NOR shown in FIG. 2 in the form of logical symbols. When actually designing an integrated circuit, use the data at the level shown in Figure 3.
The basic logic circuit within the cell is formed.

Further, other basic logic circuits can be developed in the same way, and when a circuit is constructed using these basic cells, the wiring in the wiring area is as shown in FIG. The only wiring required is to connect logic circuits formed in the same way. That is, in FIG. 4, two input wirings (I) and one output wiring (O) are connected to the NAND in the left column, and this output wiring (O) is input to an adjacent BUF. In addition, the wiring connecting these logic circuits is formed of wiring aluminum that forms the same layer when not buffering each other, but for example, the wiring connecting BUF and NOR is not buffered with other wiring In this case, both parties shall have 1
Connection is made between the wiring aluminum layer in the first layer, a through conductor (VIA) that penetrates the insulating layer formed above the wiring layer, and the second layer aluminum wiring layer. In Figure 4, adjacent N
The same applies to ORs.

As described above, according to this embodiment, the wiring for configuring the logic circuit, which was conventionally done within the wiring area, is configured within each cell, so that the wiring in the wiring area is performed between logic circuits. The wiring area is greatly reduced. Further, since the basic logic circuit is connected within the basic cell, the wiring distance is the shortest, and the operating speed of the circuit is also improved. Furthermore, the number of input/output terminals in each cell is reduced, and the number of wires used for wiring is reduced.
Area efficiency within the cell improves. In addition, since the basic elements are made up of standard logic circuit elements, automated placement and wiring algorithms used in MOS and the like can be used, and results similar to those achieved when using MOS and the like can be obtained in terms of wiring efficiency. Furthermore, the configuration of the basic logic element is uniquely determined for each cell. Furthermore, there is no need to rewrite the circuit for IIL, making it possible to shorten the time required for circuit development.

Although the above-described embodiment shows an example in which three three-output inverters are combined in one basic cell, the number of combinations and the output of the incorporated inverters can be changed as appropriate. Further, the arrangement order of input contacts and output contacts in each inverter can be mutually converted.

[0016]

As described above, according to the present invention, a single basic cell is constructed by arranging a plurality of inverters in parallel so that the injector contacts are on the same side, and input/output is performed on this basic cell. By configuring the basic logic circuit by connecting the contacts, it is possible to provide a master slice type semiconductor integrated circuit device in which the wiring load on the wiring area is reduced.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing one embodiment of a basic cell used in a master slice type semiconductor integrated circuit device according to the present invention.

FIG. 2 is a plan view showing an example of the wiring state of each inverter in the basic cell shown in FIG. 1;

FIG. 3 is a diagram representing FIG. 2 as a logical symbol;

FIG. 4 is a diagram showing a wiring state in a wiring area when a circuit is configured using the basic cells shown in FIG. 2;

FIG. 5 is a plan view showing an example of a conventionally used basic cell.

[Explanation of symbols]

1 Basic cell 2 IIL inverter 3 Contact 4 Aluminum for wiring 5 Injector contact 6 INJ line 10 Basic cell 11a-11c IIL inverter 12 INJ line 13a-13c Output contact 14a-14c Input contacts 15 Aluminum for wiring

Claims (1)

[Claims] [Claim 1] An inverter equipped with an input contact, an output contact, and an injector contact,
A single basic cell is constructed by arranging a plurality of the injector contacts on the same side, and a basic logic circuit is constructed by connecting the input/output contacts on the basic cell. Master slice type semiconductor integrated circuit device.