JPS624343A - Master-slice-type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To optimize the construction of a call for decreasing the parasitic capacity, by providing specific logic circuit regions such as a flip-flop, or exclusive OR or NOR gate in specific areas in an inner cell region. CONSTITUTION:A master-slice-type semiconductor integrated circuit device is constituted by bonding pads 111-11n, 121-12n, 131-13n and 141-14n, power supply circuits 21-24 and inner cell region 4. The inner cell region 4 consists of flip-flop regions 51-5m, gate regions 61-6m+1 and cell connecting regions 71-7m. Since the flip-flop regions 51-5m are isolated from the gate regions 61-6m+1, a pattern can be laid out in an optimum manner for constituting a flip-flop. Accordingly, the parasitic capacity produced by ineffective wiring regions can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice type semiconductor integrated circuit that is formed in common up to the process excluding the wiring process, and various logic circuits are configured by changing only the wiring process. .

[Conventional technology]

Conventionally, this type of master slice type semiconductor integrated circuit device has a bonding pad 1 as shown in FIG.
0ss, 10□,..., 101%, 10□, 1~.
....

101Me 1081e to,, ”'e 10St
l* 1041* 1041* ”・-, 104%, various power supply circuits 11□, 11., 11., 11., input/output passive circuit 12..12., 12., 12., and internal cell area 13, an input/output buffer circuit 12
Various logic circuits were constructed by changing only the wiring steps of 1 to 124 and the internal cell region 13.

In the example shown in FIG. 3, the internal cell region 13 is composed of three NOR gates. Further, the configuration of the internal cell region 13 is TTL, I''L, and STp in the Heibora system.

There are ECL logics, etc., and ECL logics are often used especially in high-speed master slice integrated circuit devices.

Figure 4 shows an example of a three-person Kanoa gate constructed using ECL logic, with transistors 14, 15, and 16 constituting a differential pair.
,17. It is composed of a constant current source transistor 18 and an emitter follower transistor 19. It is well known that parasitic capacitance of wiring and resistors is one of the factors that impede the high speed performance of high-speed logic circuits, and that the parasitic capacitance at portions 20 and 21 in FIG. 4 is particularly problematic. 20 is the parasitic capacitance of wiring and resistance within the cell, 2
1 is considered to be the capacitance mainly due to the wiring between cells. Therefore, when attempting to construct an exclusive-OR-NOR gate, a flip-flop, etc. using a plurality of gates shown in FIG. C: Impairing high speed.

If it is expected that a large number of vertical product exclusive-or-nor gates and flip-flops will be used for this purpose,
As shown in FIG. 5, when one logic circuit is constructed by combining a large number of transistors and resistors into one cell, the capacitance caused by the wiring is reduced so as not to impair high speed performance. FIG. 6 shows a latch constructed with cells having this cell structure. In this case as well, there are parasitic capacitances due to internal wirings 22 to 23 and 24 to 25, resistances, and intercell wirings.

By configuring the cell as shown in FIG. 5, parasitic capacitance can be reduced to some extent and high speed performance can be maintained. but,
In order to configure multiple logic circuits with a certain cell configuration, a certain degree of redundancy must be provided in the cell structure, which means that when a certain logic circuit is configured, there will be some wasted parts. However, this wasted portion becomes a parasitic element, which is a factor that hinders high speed performance. Furthermore, if the circuit configuration has many parts in which left registers and cascaded flip-flops are connected in cascade, connections through wiring areas will also be a wasteful part from the point of view of cascade connection of flip-flops.

[Problem that the invention seeks to solve]

The conventional master slice semiconductor integrated circuit device described above has redundancy in its cell structure and has wiring between cells that is unique to the master slice. The drawback is that it sacrifices the device's inherent high speed.

[Means for solving problems]

The master slice semiconductor integrated circuit device of the present invention has a specific logic circuit in a specific area of the internal cell area that constitutes the logic circuit.

In this way, by providing specific logic circuits such as flip-flops and exclusive-OR-NOR gates in specific areas of the internal cell area, the cell configuration can be optimized. This makes it possible to reduce the parasitic capacitance that previously existed, and to manufacture a high-speed master slice type semiconductor integrated circuit device.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a master slice type semiconductor integrated circuit device of the present invention.

The master slice type semiconductor integrated circuit device of this example is as follows:
Ponding pad 1゜, 1□,...v 1tss
1altle ”'a 11%p l1ls 1n
e ”'p 11%s 141s 141y ””a
i4s, various power supply circuits 2H2@-2B-24, and
Output buffer 1 circuit 3. ．． 3. , 3. , 3. and an internal cell area 4, and the internal cell area 4 is comprised of flip-flop areas 5, , 5 . ,-...,5. and the conventional gate region S,
, S,...

6 y, and wiring area 71#'y,...,7 between cells
．． It consists of .

In this way, the flip-flop areas 51-5. and gate area 6. ~6°, the tree tube flop regions 51 to 5. This enables an optimal pattern layout for configuring a flip-flop, and in the gate region 61 to aw, there is too much redundancy in the conventional structure in which a flip-flop can be constructed from 1 to 2 cells. The portion that would otherwise have been wasted is reduced because it does not form a tree flop, which reduces parasitic capacitance and maintains high speed to some extent. Also, flip-flop area 5. ~5. By providing cascade connections such as shift registers and kakuntas, connections between flip-flops can be made in the wiring area 7. ~7. The input terminal 8 and output terminal 9 of the adjacent cell are connected to the second
By placing the flip-flops on the left and right sides of the cell as shown in the figure, flip-flops can be connected over the shortest distance. Further, in this embodiment, the logic circuit in the specific area is a flip-flop, but depending on the circuit type, it may be an exclusive-or-nor gate.

Note that, although the present invention does not particularly specify the cell structure constituting the flip-flop and gate region,
Needless to say, the cell configuration should be designed to provide an optimal layout for configuring the solid flop and gate.

〔Effect of the invention〕

As explained above, the present invention enables (1) to optimize the cell configuration by providing a specific logic circuit area such as a flip-flop or an exclusive-OR-NOR gate in a specific area of the internal cell area; Therefore, C: It is possible to reduce the parasitic capacitance that conventionally existed in wasted wiring areas, and it is possible to manufacture high-speed master slices. (2) Connections between cells in specific areas can be made by appropriately positioning the input and output terminals. By placing
Connections can be made at the shortest possible distance without going through the wiring area, and therefore the wiring length can be shortened, resulting in a reduction in parasitic capacitance attached to the output terminal of the cell, and power consumption inside the cell. This has the effect of reducing the number of devices and increasing the degree of integration.

[Brief explanation of the drawing]

A configuration diagram of a conventional example of a product circuit device. ・Figure 4 is a diagram showing an example of the circuit of the internal cell in Figure 3. Figure 5 is a cell configuration that takes into account vertical product exclusive-or-one circuit and flip-flop. FIG. 6 is a diagram showing an example of a latch configured with the cell structure of FIG. 5. l1ls l1m5 ””y i,%* 111# Ko,..., 18%# lIn14,...e 11f&
*141# to..., 14%: Ponding pal area, 5m, 5□...tss" flip flop area, 61ps,..., 6%, Pagate area, 71
#7! t..., 73: Wiring area.

Claims (1)

[Scope of Claims] 1. In a master slice type semiconductor integrated circuit device in which processes are commonly formed up to the process excluding the wiring process, and various logic circuits are formed by changing only the wiring process, internal cells forming the various logic circuits; A master slice type semiconductor integrated circuit device characterized in that a specific logic circuit is provided in a specific region of the regions. 2. The master slice type semiconductor integrated circuit device according to claim 1, wherein the specific logic circuit in the specific area is a flip-flop. 3. A specific logic circuit in the specific area is an exclusive OR/
The master slice type semiconductor integrated circuit device according to claim 1, which is a NOR gate.