JPS63310136A - Complementary mis master slice logic integrated circuit - Google Patents

Complementary mis master slice logic integrated circuit

Info

Publication number
JPS63310136A
JPS63310136A JP62146652A JP14665287A JPS63310136A JP S63310136 A JPS63310136 A JP S63310136A JP 62146652 A JP62146652 A JP 62146652A JP 14665287 A JP14665287 A JP 14665287A JP S63310136 A JPS63310136 A JP S63310136A
Authority
JP
Japan
Prior art keywords
functional
region
wiring
active transistor
wiring part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62146652A
Other versions
JP2742052B2 (en
Inventor
Hideki Fukuda
Masami Urano
Original Assignee
Nippon Telegr & Teleph Corp <Ntt>
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegr & Teleph Corp <Ntt> filed Critical Nippon Telegr & Teleph Corp <Ntt>
Priority to JP62146652A priority Critical patent/JP2742052B2/en
Publication of JPS63310136A publication Critical patent/JPS63310136A/en
Application granted granted Critical
Publication of JP2742052B2 publication Critical patent/JP2742052B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118Masterslice integrated circuits
    • H01L27/11803Masterslice integrated circuits using field effect technology
    • H01L27/11807CMOS gate arrays

Abstract

PURPOSE:To realize a high-speed operation by securing the flexibility during a designing operation without lowering an integration density and by securing the drive capacity of a transistor by a method wherein a wiring operation inside a functional cell or a functional macrocell and between these cells is executed by using a region of the active transistor. CONSTITUTION:A region C of an active transistor coexists without separating wiring regions A inside a functional cell or a functional macrocell constituting logic from a wiring region B between functional cells or functional macrocells. Thereby, a wiring part inside the functional cell or the functional macrocell and the wiring part between the functional cells or the functional macrocells can be installed in such a way that they coexists in the region of the active transistor by making a wiring part of a VDD power supply wiring part 10 or a ground wiring part 11 as a boundary line. If the active transistor constituting the region C is added and connected in parallel whenever necessary, the region C can be expanded. By this setup, an integration density can be enhanced; the drive capacity of the active transistor can be increased; a high-speed operation of a function of an LSI is achieved.
JP62146652A 1987-06-12 1987-06-12 Complementary mis master slice logic integrated circuits Expired - Fee Related JP2742052B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62146652A JP2742052B2 (en) 1987-06-12 1987-06-12 Complementary mis master slice logic integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62146652A JP2742052B2 (en) 1987-06-12 1987-06-12 Complementary mis master slice logic integrated circuits

Publications (2)

Publication Number Publication Date
JPS63310136A true JPS63310136A (en) 1988-12-19
JP2742052B2 JP2742052B2 (en) 1998-04-22

Family

ID=15412570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62146652A Expired - Fee Related JP2742052B2 (en) 1987-06-12 1987-06-12 Complementary mis master slice logic integrated circuits

Country Status (1)

Country Link
JP (1) JP2742052B2 (en)

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04287369A (en) * 1991-03-15 1992-10-12 Sharp Corp Manufacture of gate array and semiconductor integrated circuit device
JPH07153927A (en) * 1993-12-01 1995-06-16 Nec Corp Semiconductor integrated circuit
JPH0897387A (en) * 1994-09-29 1996-04-12 Nec Corp Semiconductor device
JP2001237317A (en) * 2000-02-22 2001-08-31 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device, its designing method, and computer-readable recording medium recording i/o cell library
JP2010219256A (en) * 2009-03-16 2010-09-30 Elpida Memory Inc Semiconductor device and arrangement method for compensation capacitor of semiconductor device
JP2011515841A (en) * 2008-03-13 2011-05-19 テラ イノヴェイションズ インコーポレイテッド Crossings in restricted gate level layout architecture coupled transistor layout
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8680626B2 (en) 2007-10-26 2014-03-25 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US8701071B2 (en) 2008-01-31 2014-04-15 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8756551B2 (en) 2007-08-02 2014-06-17 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US8759985B2 (en) 2008-03-27 2014-06-24 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US8823062B2 (en) 2006-03-09 2014-09-02 Tela Innovations, Inc. Integrated circuit with offset line end spacings in linear gate electrode level
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8863063B2 (en) 2009-05-06 2014-10-14 Tela Innovations, Inc. Finfet transistor circuit
US8951916B2 (en) 2007-12-13 2015-02-10 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8966424B2 (en) 2007-03-07 2015-02-24 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US9754878B2 (en) 2006-03-09 2017-09-05 Tela Innovations, Inc. Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074549A (en) * 1983-09-30 1985-04-26 Fujitsu Ltd Semiconductor device
JPS62169445A (en) * 1986-01-22 1987-07-25 Nec Corp Semiconductor device
JPS62169445U (en) * 1986-04-18 1987-10-27

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074549A (en) * 1983-09-30 1985-04-26 Fujitsu Ltd Semiconductor device
JPS62169445A (en) * 1986-01-22 1987-07-25 Nec Corp Semiconductor device
JPS62169445U (en) * 1986-04-18 1987-10-27

Cited By (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04287369A (en) * 1991-03-15 1992-10-12 Sharp Corp Manufacture of gate array and semiconductor integrated circuit device
JPH07153927A (en) * 1993-12-01 1995-06-16 Nec Corp Semiconductor integrated circuit
JPH0897387A (en) * 1994-09-29 1996-04-12 Nec Corp Semiconductor device
JP4629826B2 (en) * 2000-02-22 2011-02-09 パナソニック株式会社 The semiconductor integrated circuit device
JP2001237317A (en) * 2000-02-22 2001-08-31 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device, its designing method, and computer-readable recording medium recording i/o cell library
US8921896B2 (en) 2006-03-09 2014-12-30 Tela Innovations, Inc. Integrated circuit including linear gate electrode structures having different extension distances beyond contact
US10186523B2 (en) 2006-03-09 2019-01-22 Tela Innovations, Inc. Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US10141334B2 (en) 2006-03-09 2018-11-27 Tela Innovations, Inc. Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures
US10217763B2 (en) 2006-03-09 2019-02-26 Tela Innovations, Inc. Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid
US10141335B2 (en) 2006-03-09 2018-11-27 Tela Innovations, Inc. Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures
US8946781B2 (en) 2006-03-09 2015-02-03 Tela Innovations, Inc. Integrated circuit including gate electrode conductive structures with different extension distances beyond contact
US9917056B2 (en) 2006-03-09 2018-03-13 Tela Innovations, Inc. Coarse grid design methods and structures
US8952425B2 (en) 2006-03-09 2015-02-10 Tela Innovations, Inc. Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length
US9905576B2 (en) 2006-03-09 2018-02-27 Tela Innovations, Inc. Semiconductor chip including region having rectangular-shaped gate structures and first metal structures
US10230377B2 (en) 2006-03-09 2019-03-12 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9859277B2 (en) 2006-03-09 2018-01-02 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9754878B2 (en) 2006-03-09 2017-09-05 Tela Innovations, Inc. Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires
US9240413B2 (en) 2006-03-09 2016-01-19 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9711495B2 (en) 2006-03-09 2017-07-18 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9673825B2 (en) 2006-03-09 2017-06-06 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9589091B2 (en) 2006-03-09 2017-03-07 Tela Innovations, Inc. Scalable meta-data objects
US9425273B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same
US9425272B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same
US9425145B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8823062B2 (en) 2006-03-09 2014-09-02 Tela Innovations, Inc. Integrated circuit with offset line end spacings in linear gate electrode level
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9741719B2 (en) 2006-03-09 2017-08-22 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US8921897B2 (en) 2006-03-09 2014-12-30 Tela Innovations, Inc. Integrated circuit with gate electrode conductive structures having offset ends
US9633987B2 (en) 2007-03-05 2017-04-25 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US10074640B2 (en) 2007-03-05 2018-09-11 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US9910950B2 (en) 2007-03-07 2018-03-06 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9424387B2 (en) 2007-03-07 2016-08-23 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8966424B2 (en) 2007-03-07 2015-02-24 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9595515B2 (en) 2007-03-07 2017-03-14 Tela Innovations, Inc. Semiconductor chip including integrated circuit defined within dynamic array section
US8756551B2 (en) 2007-08-02 2014-06-17 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US8759882B2 (en) 2007-08-02 2014-06-24 Tela Innovations, Inc. Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
US8680626B2 (en) 2007-10-26 2014-03-25 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US8951916B2 (en) 2007-12-13 2015-02-10 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9281371B2 (en) 2007-12-13 2016-03-08 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9818747B2 (en) 2007-12-13 2017-11-14 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9202779B2 (en) 2008-01-31 2015-12-01 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8701071B2 (en) 2008-01-31 2014-04-15 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US9530734B2 (en) 2008-01-31 2016-12-27 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US9081931B2 (en) 2008-03-13 2015-07-14 Tela Innovations, Inc. Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer
US8847331B2 (en) 2008-03-13 2014-09-30 Tela Innovations, Inc. Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures
US9208279B2 (en) 2008-03-13 2015-12-08 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods
US9213792B2 (en) 2008-03-13 2015-12-15 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
US8853793B2 (en) 2008-03-13 2014-10-07 Tela Innovations, Inc. Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends
US8836045B2 (en) 2008-03-13 2014-09-16 Tela Innovations, Inc. Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track
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JP2014158036A (en) * 2008-03-13 2014-08-28 Tela Innovations Inc Cross-coupled transistor layouts in restricted gate level layout architecture
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US8785979B2 (en) 2008-03-13 2014-07-22 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer
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US9871056B2 (en) 2008-03-13 2018-01-16 Tela Innovations, Inc. Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
US8772839B2 (en) 2008-03-13 2014-07-08 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
US8853794B2 (en) 2008-03-13 2014-10-07 Tela Innovations, Inc. Integrated circuit within semiconductor chip including cross-coupled transistor configuration
US8669594B2 (en) 2008-03-13 2014-03-11 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within at least twelve gate level feature layout channels
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US8669605B2 (en) 2009-03-16 2014-03-11 Yoshiaki Shimizu Semiconductor device and arrangement method of compensation capacitor of semiconductor device
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