JPS601844A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the integration and to enhance the performance of a semiconductor integrated circuit device by realizing the logic circuit operation of a cell via the first and second metal layers, and connecting between the signal terminals of the cell at least the third and fourth metal layers on the cell. CONSTITUTION:The logic circuit operation of a cell is realized via the first metal layer (b), the second metal layer (c), a contacting hole (e), and the connecting hole of the first layer and the second layer. The connecting hole of the first and second layers is used as a signal leading terminal of the cell, the terminal can be disposed at the arbitrary position on the second layer like l1-l4 as shown, thereby improving the provision of automatic wirings. In order to perform automatic wirings, the third metal layer is used in the longitudinal channel, and the fourth metal layer is used in the lateral channel. Accordingly, in the abovementioned construction, the position of the signal leading terminal can be altered to the position capable of readily connecting, and the all third and fourth layers can be used as the wiring regions. Consequently, the degree of freedom of wirings can be improved, thereby improving the integration of a chip.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having a multilayer metal wiring structure.

[Prior art and its problems]

FIG. 1 shows an example of a pattern layout for cells and inter-cell wiring in a conventional semiconductor integrated circuit device.

Figure 1 is an example of a CMOS integrated circuit device using the master slice method.

Generally, in order to realize a semiconductor integrated circuit device using the master slicing method, it must be done with an automatic design system that includes a combi-coater and C4.
Determine the direction and connect the wires.

In the figure, (e) shows the contact hole, and (f) shows the first contact hole.
The connection hole between the metal layer and the second metal layer is shown, and s F! To achieve the desired logic circuit operation, JT requires the first metal MM.
(b) Connections between cells are made using a second metal M # (C), and the signal extraction terminals of each cell are connected to each other in a wiring area (d) that has multiple rows of wiring channels provided between cell rows. Wiring is selectively performed in the first metal layer and the second metal layer. In this case, the wiring for realizing the logic circuit operation has already been laid out on the cell, and there is only a small area that is not divided by dividing lines, and the area on the cell cannot be used efficiently as a wiring area. Therefore, with this method, it is necessary to increase the required wiring area as the circuit becomes larger.
This had the disadvantage of reducing chip usage efficiency.

[Purpose of the invention]

The present invention improves the drawbacks of the conventional device described above, and aims to provide a semiconductor integrated circuit device with an improved degree of integration.

[Summary of the invention]

That is, according to the present invention, the logic circuit operation of the cell is realized by the first metal layer and the second metal layer, and the signal ends of the cell are connected by at least the third metal layer and the fourth metal layer on the cell. .

〔Effect of the invention〕

According to this invention, since the wiring between the signal terminals of the cell is performed at least in the third metal layer and the fourth metal layer on the cell, it is possible to reduce the increase in the wiring area due to an increase in the circuit scale, and to increase the integration of the chip. can be improved. In addition, since a wiring layer with a large distance from the board and low capacitance is used for wiring between signal terminals, the wiring becomes less responsive, and the delay between signal terminals due to the wiring length (DC time constant) ) can be reduced and high performance can be achieved.

[Embodiments of the invention]

Second. Third. FIG. 4 is an explanatory diagram of an embodiment for explaining the present invention in detail.

In the figure, (i) is the first cell (g) and (h) is the first cell, respectively.
Gold end layer Niyoru VB8. vDD and the first metal layer (b)
, the second metal layer (C), the contact hole (e), and the connection hole (f) between the first metal layer and the second metal layer, the logic circuit operation of the cell is realized. Since the wiring channels (j) and (2) in the figure are not used to realize the logic circuit operation of the cells, they can also be used as connections between cells that cross the cells.

FIG. 3 shows the second camphor layer (c) of the cell shown in FIG. Although the second metal layer is shown only above the cell in the figure, it may extend outside the cell area.

The connection holes of the second metal layer and the third metal layer are used as signal extraction terminals of the cell, and the terminals are 1A, I12,
It is possible to set it at any position on the second metal layer, such as 13 and 14.

By making the signal output end position variable in this way, the ease of wiring by automatic wiring is improved.

Although 11.12, 13.14 are shown on the lattice points in the first metal layer and the second metal layer, they do not necessarily have to be on the lattice points in the first metal layer and the second metal layer.

FIG. 4 shows an example of connection of signal extraction terminals of cells. In the figure, fil, i2. i3 indicates a cell, and cell 11 is the same as the cell shown in FIG. 3 and indicates the second metal layer (C). 1 is the signal extraction terminal of the cell, 2 is the third metal layer,
3 is the fourth metal layer, 4 is a connection hole between the third metal layer and the fourth gold striped layer, and in order to perform automatic wiring, the third metal layer is a vertical channel, and the fourth metal layer is a horizontal channel. used for.

Therefore, with the above configuration, the position of the signal extraction terminal can be changed to a position where it is easy to connect, and the entire area of the third metal layer and fourth metal layer can be used as a wiring area, so the degree of freedom in wiring is improved. Therefore, it is possible to improve the degree of integration of the chip.

In the figure, the third metal bridge layer (2) is a vertical channel, and the fourth metal layer (4) is a horizontal channel, but it is not necessarily limited to this.

[Brief explanation of the drawing]

FIG. 1 is a plan view illustrating conventional cells and inter-cell wiring;
(2) FIGS. 2 and 3 are plan views for explaining the present invention in detail, and FIG. 4 is a plan view for explaining connections of signal extraction terminals of cells. In the figure, b...first metal layer, C...second metal layer, 1...cell signal terminal, 2...third metal layer, 3...fourth metal layer, Ai( i=1 to 8)...Logic circuit wiring, Bi (i=
1 to 8)...Wiring for signal terminals. Agent Patent attorney Noriyuki Chika (and 1 other person) Figure l Figure d Figure 2 Figure 4

Claims (2)

[Claims] (1) In a semiconductor integrated circuit device formed by arranging and integrating a plurality of cells each consisting of a plurality of active elements on a semiconductor board, the logic circuit operation of the cell is realized by the first metal layer and the second metal layer, and the cell connection between the signal terminals of at least the third
A semiconductor integrated circuit device comprising a metal layer and @4 metal layer. (2) The semiconductor integrated circuit device according to item 1 of the patent scope, characterized in that a desired logic circuit operation is realized by a master slice method.