JPS62128152A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the mutual effect of signals between wirings by a method wherein the lattice wiring, consisting of one or more wirings provided in extended form in the longitudinal direction of a wiring channel region and the wiring with which the prescribed potential is supplied by cross-connecting to the wiring on the wiring channel region, is provided and a wiring with which each macro-cell is connected is provided in extended form in the track separated by the lattice wiring. CONSTITUTION:Four paralleled wirings 11 are provided in extended form on a wiring channel region 4 in its longitudinal direction, namely, along X-direction as a first layer wiring, and a wiring 12 orthogonally intersecting with said wirings 11 is provided leaving the interval in the amount of two macro-cells 1 as a second layer wiring. Then, said wirings 11 and 12 are connected to each other by a through hole 13, a lattice wiring 14 is constituted as a whole, and a Y-direction wiring 12 is connected to a GND through the macro-cell 1. As a result, all X-direction wirings 11 can be maintained at the GND potential. Also, as the input-output terminal 3 of each macro- cell 1 is mutually connected, the X-direction wiring 5 consisting of the first layer wiring and the Y-direction wiring 6 consisting of the second layer wiring are provided, and these wirings are mutually connected by a through hole 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device using a macrocell array method.

[Conventional technology]

-C, a semiconductor integrated circuit device of the macrocell array type has a macrocell array 2 configured by arranging a plurality of macrocells 1 in one direction, for example, the X direction, as shown in FIG. The direction perpendicular to this, that is, Y
The configuration is such that they are arranged in parallel at a required interval in the direction.

Each of the macrocells 1 is arranged such that respective input/output terminals 3 are arranged on both sides of the macrocell array 2, and a wiring channel region 4 between each macrocell array 2 is used for mutual wiring between the macrocells 1 and 2. It is configured so that it can be applied.

In the conventional wiring in the wiring channel region 4,
The wiring 5 in the X direction is composed of first layer wiring, and the wiring 6 in the Y direction
is composed of second layer wiring formed on the first layer wiring, and these first layer wirings are formed on the first layer wiring. The circuit layout is designed so that the second layer wirings 5 and 6 are interconnected through through holes 7 and the overall wiring area is minimized.

[Problem that the invention seeks to solve]

In the conventional semiconductor integrated circuit device described above, the first . Since the pattern design of each wiring 5.6 in the second layer is carried out with consideration only in terms of wiring area, in some cases two or more different wirings may be placed close to each other and parallel to each other over a long distance. It may be extended. Therefore, the signals applied to these adjacent wirings may influence each other, which may adversely affect the electrical characteristics of the semiconductor integrated circuit device.

This phenomenon is particularly likely to occur between wirings extending in the longitudinal direction of the wiring channel region 4, that is, in the X direction in the above example,
In a semiconductor integrated circuit device that handles high frequencies, mutual interference between adjacent wiring lines becomes significant, which seriously affects the characteristics of the semiconductor integrated circuit device.

[Means for Solving the Problems] The semiconductor integrated circuit device of the present invention stabilizes characteristics and improves reliability by preventing mutual interference between signals in parallel wiring lines. It is.

The semiconductor integrated circuit device of the present invention has a lattice wiring including one or more wirings extending in the longitudinal direction of the wiring channel region and wirings cross-connected to the wirings to supply a predetermined potential. The configuration is such that wires connecting macro cells extend within tracks separated by the wires.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the invention. As shown in the figure, a macrocell array 2 is created by arranging a plurality of macrocells 1 in the X direction.
The macrocell arrays 2 are arranged in parallel in the Y direction at required intervals, and a wiring channel region 4 is formed between each macrocell array 2. Further, each macrocell 1 constitutes an array such that input/output terminals 3 are arranged on both sides of the macrocell array 2.

In the wiring channel region 4, four parallel wirings 11 are extended as first-layer wirings along the longitudinal direction of the wiring channel region 4, that is, in the It is arranged as a two-layer wiring at an interval of two macro cells 1.

Then, by connecting these wirings 11 and 12 with each other through through holes 13 to form a lattice wiring 14 as a whole, and connecting the Y-direction wiring 12 to GND via the macro cell 1, all the X-direction wiring 11 is kept at GND potential. Note that only this grid wiring 14 is shown in FIG.
It can be seen that five directional regions (referred to as tracks) 8 are formed.

Further, in the wiring channel region 4, in order to mutually connect the input/output terminals 3 of each macro cell 1, there are wirings 5 in the X direction consisting of first layer wirings, and wirings 6 in the Y direction consisting of second layer wirings.
are arranged, and each is connected to each other by a through hole 7. Among these wirings 5 and 6, wiring channel region 4
The wiring along the longitudinal direction, that is, the wiring 5 in the X direction in this embodiment, is connected to each track between the wirings 11 in the X direction of the grid wiring 14.
Each wiring 5 is configured to be isolated in the Y direction by the wiring 11 of the grid wiring 14.

According to this configuration, all the interconnects fa5 extending in the X direction in the interconnect channel region 4 are isolated by the interconnects 11 held at the GND potential, so the interconnects 5 are mutually shielded, Electrical interference between adjacent wires 5 extending in the longitudinal direction is prevented, and mutual influence of signals of each wire 5 can be prevented. In addition, the lattice wiring 1 held at the GND potential also in the wiring 6 adjacent to the Y direction.
They can be isolated from each other by the wiring 12 in the Y direction of No. 4, and the wiring 6
It is also possible to prevent influence between signals.

In this embodiment, since four grid wiring lines 11 are provided, five tracks are formed in the wiring channel region 4, and five X-direction wiring lines 5 can be arranged in parallel, as described above.

Therefore, in the wiring channel region 4, the influence of signals between the long adjacent wirings 5 can be eliminated, and the characteristics of the semiconductor integrated circuit device can be stabilized and the reliability can be improved.

FIG. 3 shows another embodiment of the present invention, in which the same or equivalent parts as in FIG. 1 are given the same reference numerals.

In this embodiment, as only the grid wiring 14A is shown in FIG.
While the wiring 11 in the direction is composed of three wires, the wiring 111 on both sides
There are two Xs between a and lla and macrocell array 2.
It is constructed so that the direction wiring 5 can be extended, and six tracks 8A are formed as a whole, so that the X-direction wiring 5 can be extended respectively. This distribution billa and macro cell
For the wiring 5 provided between the array 2 and the array 2, a wiring that does not cause mutual influence of signals even when adjacent to each other is selected and extended. It goes without saying that the wiring 5 whose signals mutually influence each other is separated by the grid wiring 14A as in the previous example.

In this example, the same effect as the previous example can be obtained, and
Although there are three wires 11 in the X direction of the lattice wire 14A in the wire channel region 4, the number of tracks 8A that can be practically used is six, and the wires in the X direction interconnect the input/output terminals 3 of the macro cells 1. 5 can be arranged in parallel in the Y direction, and the degree of integration can be improved.

Here, each X-direction wiring 5 is not necessarily the wiring 11 of the grid wiring.
It should be noted that it is not necessary to install only one line in each trunk separated by a line, but two or more lines may be placed in the same track if the wiring is shifted in the length direction of the wiring channel 4. Needless to say.

〔Effect of the invention〕

As explained above, the present invention provides a grid wiring consisting of one or more wirings extending in the longitudinal direction of the wiring channel region and wirings cross-connected to the wirings to supply a predetermined potential. Since the wires connecting macro cells are extended in tracks separated by the wires, adjacent wires are shielded from each other by the grid wires, and mutual influence of signals between these wires can be prevented. 4
It is possible to stabilize the characteristics and improve the reliability of the integrated circuit device.

[Brief explanation of drawings]

Fig. 1 is a layout diagram of one embodiment of the present invention, Fig. 2 is a layout diagram showing only the grid wiring, Fig. 3 is a layout diagram of another embodiment of the invention, and Fig. 4 is a layout diagram showing only the grid wiring. The layout diagram shown in FIG. 5 is a conventional layout diagram. ■... Macro cell, 2... Macro cell array, 3
...Input/output terminal, 4...Wiring channel area, 5...
・X direction wiring, 6...Y direction wiring, 7...Through hole, 8° 8A...Track, 11. lla...(
Wiring (in the X direction), 12... Wiring (in the Y direction), 13.
...Through hole, 14.14A...grid wiring. Figure 2 1 Mu-Y-11 Figure 3 Figure 4

Claims (1)

[Claims] 1. A semiconductor integrated circuit device in which macrocell arrays each consisting of a plurality of macrocells are arranged in a plurality of rows, and each of the macrocells is interconnected in a wiring channel region defined between the macrocell arrays. , a lattice wiring is provided that is maintained at a predetermined potential by one or more wirings extending in the longitudinal direction of the wiring channel region and wirings cross-connected to the wiring, and the wirings connecting between the macro cells are connected to the lattice wiring. 1. A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is installed in a plurality of tracks separated by a plurality of tracks. 2. A semiconductor integrated circuit according to claim 1, in which a plurality of wires extending in the longitudinal direction of the wiring channel region are arranged in tracks separated in a direction perpendicular to the longitudinal direction. Device.