JPS62122145A - Lsi of master slice system - Google Patents

Abstract

PURPOSE:To utilize a vacant area in a block for interblock wiring and thereby to reduce an interblock wiring region by a method wherein positions of external terminals comprising input and output terminals used for connections of cells of (k) lines and lcolumns arranged on a cell array and for those between each of a plurality of blocks are provided in wiring portions in each block. CONSTITUTION:In blocks 7 and 8, external terminals 71, 72, 81 and 83 are positioned inside the blocks respectively, and they are the same with mutual connection wirings 73, 76, 86 and 84 between cells respectively, which are inner-block wiring portions of these external terminals. These blocks are arranged in LSI and wired mutually. An interblock wiring 9 is provided with a lead from the external terminal which is formed in accordance with the arranged place of the block. In other words, cells formed of transistors, resistors or the like isolated electrically from one another are set in an array of (n) lines and (m) columns, and a wiring region is prepared between cell lines. In relation to input and output terminals used for connections between the blocks constituted by cells of (k) lines and l columns (1<=k<=n, 1<=l<=m) arranged on the cell array and mutual wirings between them, the positions of the external terminals thereof are equivalent to the entire inner-block wiring portions to which the respective external terminals are connected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice type LSI, and particularly to external terminal positions used for inter-block wiring.

[Conventional technology]

Conventionally, the external terminal positions of this type of block have been set at one to several points on the periphery of the block. This arises from the necessity to treat the inside of a block as prohibited when wiring between blocks. This configuration has the advantage of simplifying the wiring program. As a conventional technology with this configuration, an LS called master image is used.
There is the following example in which the external terminal positions are set on the upper and lower sides of the block used on the I board. [19th Design Automation Conference (19th DesignA
automation Conference) J (J
1982), pages 163-169 of R. Donze et al.
LSI design system A (PHILO-A VL
See SI Design System) J.

Another configuration is based on the method of designing a large-scale master slice LSI by dividing it into four blocks.

An example of this is when the external terminals of the block are placed on four sides. “IEICE Technical Research Report” (1984, 1)
The paper by Ofuji et al. published on pages 37-42 of ``January 30th''
3-layer wiring large-scale gate array”.

[Problem that the invention seeks to solve]

In the conventional block external terminal position setting described above, it is necessary to set the external terminal position on the peripheral side of the t block at the block design stage, and the external terminal position determination is optimized for the following reasons 1) and 2). 1) At the block design stage, it is unknown where the block will be placed on the cell array of the master slice.

2) When multiple of the same block is used in an LSI, the mutual positional relationship between those blocks and the other blocks connected to them will be different, so optimize the wiring between blocks at all locations. The inability to set external terminal positions results in a large amount of wiring area being required during inter-block wiring, or in making the wiring length longer than necessary.

The above drawbacks can be explained in Figure 2 w, (13, p) as follows.

Block 7 in Part 2 and block 8 in Figure 2 0 are circuits that realize different functions, and each has 4 cells in 2 rows and 4 columns.
and cell 4 interconnection wiring 73°74.75.76.
84, 85, 86, 87 and external terminal 71° 72.81.
It consists of 82.83. here.

Each block 7.8, external terminal 71.72.81.82
83 is installed on the peripheral side of block 7.8, and internal wiring is drawn out to that position. Figure 2 0 is the second
2 is a wiring diagram showing the result of inter-block wiring for the block shown in FIG. 2 and the G block 8 of FIG. 2. FIG. In the figure, the wiring 9 between the blocks is connected according to the connection request between the external terminals 71, 72, 81, 82° 83 of the block 7.8.
Since this is realized using the area between the blocks, an increased portion 10 of the wiring area is generated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a next-master slice type LSI which solves the above-mentioned problems and prevents the wiring area from increasing.

[Means for solving problems]

The configuration of the present invention is a master slice type LSI in which cells are electrically isolated from each other and are arranged in a play shape with in rows and m columns of cells, and a wiring area is arranged between the columns of the cells. Rows to columns (1≦≦n, l≦l
≦m) of cells and wiring between these cells, and external terminals consisting of input and output terminals used for connection between the blocks are provided at the marked line portion of the love lock. .

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

Figure 1 (0) is a configuration diagram showing each block of a master slice type LSI according to an embodiment of the present invention; The first specific block 7 and the block 8 in FIG. 7
5.76 and 84°85, 86.87, and external terminals 71, 72. and 81°82.83. In each block 7.8, external terminals 71, 72, 81.83 are located within the block, and interconnection wiring 73.76.86.
They are the same as 84. Although the external terminal 82 is located within the block, there is only one external terminal 82 because there is no interconnection wiring between the cells.

An LSI consists of a circuit that realizes a certain function as a whole by arranging these blocks and wiring them. It can be seen that the inter-block wiring 9 in FIG. 10 is led out from friend external terminals depending on where the blocks are placed.

Furthermore, since it uses the empty space within both blocks.

The increase 10 in the hybridization line area seen in Figure 2, ◎, described above does not occur. Therefore, it can be seen that it greatly contributes to improving the wiring density.

That is, according to the present invention, in a master slice type LSI in which cells (Hn rows and m columns) consisting of transistors, resistors, etc. that are electrically isolated from each other are arranged in a play shape, and a wiring area is prepared between the cell columns, the above-mentioned Arranged on the cell array in one row and one column (1≦≦n).

1≦l≦m) cells and interconnections between them, an input used for connection between blocks;
For output terminals (referred to as external terminals), the external terminal position should not be limited to just a few points on the peripheral side of the block, but should be all of the wiring within the block to which each external terminal connects. A characteristic mask slicing LSI can be obtained.

An embodiment of the present invention has been described above.

Various modifications other than this embodiment are possible. For example, the block is not limited to a rectangular shape, but may have any shape.

〔Effect of the invention〕

As explained above, according to the present invention, by setting the external terminal position of the block to the block self-registered line part of the external terminal, the terminal can be drawn out onto the peripheral side of the block at the block design stage. This eliminates the need for wiring between blocks, and enables optimal extraction from external terminals depending on the placement location of blocks when wiring between blocks.Furthermore, since the empty space within the block is used for wiring between blocks, the wiring area between blocks can be optimized. Effects such as being able to reduce

[Brief explanation of drawings]

The first characteristic is a mask slicing method LS according to an embodiment of the present invention.
FIG. 1 (I3) is a configuration diagram showing the other block of the master slice type LSI according to an embodiment of the present invention, ◎ in FIG. Wiring diagrams showing the wiring state between the blocks in Figures 2 to 8 are the configurations of one and the other blocks of a conventional master slice type LSI, Figure 2 0 is the wiring between the blocks in Figure 2 and @ It is a wiring diagram showing a state.

Claims (1)

[Claims] In a master slice type LSI in which cells that are electrically isolated from each other are arranged in an array of n rows and m columns, and a wiring area is arranged between the columns of the cells, there are k rows and l columns (1 ≦k≦n, 1≦l≦m) and the wiring between these cells. A master slice type LSI characterized in that: