JPS63187647A - Master slice system semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To control wiring length by performing connection within internal blocks and external blocks, and between the internal blocks and the external blocks, by using blocks for wirings consisting of basic cells for the wirings. CONSTITUTION:Basic cells 3 for wirings are arranged among basic cell rows 2 for a master slice type semiconductor integrated circuit and among cell rows 1 for input-output circuits and the basic cell rows 2. A block 10 for the wiring is disposed onto a cell array for the wirings just under an internal block 4 and an internal block 7. An output terminal 5 for the internal block 4 and a connecting terminal 11 for the block 10 for the wiring, an input terminal 8 for the internal block 7 and a connecting terminal 13 for the block for the wiring, an input terminal 9 for the internal block 7 and a connecting terminal 14 for the block 10 for the wiring, and an output terminal 6 for the internal block 4 and a connecting terminal 12 for the block 10 for the wiring are connected respectively. Accordingly, wiring length can be controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate array LSI, and particularly to the structure of a wiring region provided between unit cell columns thereof.

[Conventional technology]

Conventionally, this type of gate array LSI consists of basic cell rows in which a large number of basic cells 2 such as several basic transistors are arranged in one direction as shown in FIG. A plurality of basic cell rows are arranged in parallel, and the periphery of the basic cell row group is surrounded by a cell row consisting of basic cells 1 for input/output circuits. Further, the connection between the functional blocks 4 and 7, which are the plurality of basic cells 2, is made within the wiring area 20.
This was automatically designed and carried out using the AD system.

[Problem that the invention seeks to solve]

In the conventional master slice type semiconductor integrated circuit described above, there are 4.7 functional blocks (hereinafter referred to as internal blocks) composed of several basic cells 2 and input/output circuits arranged around the basic cell row group. The connection with the functional blocks (hereinafter referred to as external blocks) made up of the basic cells 1 is made using the wiring area 20 provided between the columns of the basic cells 2, using CAD on the wiring grid set on the chip in advance.
This was done automatically using a system. However, if there is a signal bus whose delay time is expected to be a problem at the circuit design stage, it is necessary to control the minimum value of the delay time. It is necessary to control the maximum value. Alternatively, in cases where it is necessary to control relative variations between buses, the results of automatic wiring may not be sufficient. In such cases, in conventional master slice type semiconductor integrated circuits, the operator must modify the wiring individually after the automatic wiring is completed, or the necessary wiring data must be specially input during automatic wiring. This method requires the following operations, which has the drawback of increasing the number of design steps. Furthermore, this becomes even more remarkable in a circuit configuration having a data bus line.

[Means for solving problems]

According to the present invention, the basic cell array for wiring is installed in at least one of the wiring area provided between the basic cell rows and the area between the basic cell array area and the basic cell area for input/output circuits, and is connected to the wiring area. By arranging the intended basic cells between the blocks, a master slice type semiconductor integrated circuit is obtained in which the wiring length between the input and output terminals of the blocks can be easily controlled.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a master slice type semiconductor integrated circuit according to an embodiment of the present invention. Basic cell for input/output circuit 1
is placed on the periphery of the chip, and the external block made up of this cell 1 outputs signals from the internal block made up of basic cell 2 to the outside of the integrated circuit, and sends signals from the outside to the internal block. It has the function of sipping. A plurality of basic cells 2 are arranged horizontally to form a basic cell row. By combining these basic cells 2, various functional blocks (internal blocks) 4.7 can be constructed. The basic cells 3 for wiring are installed in the wiring area between the basic cells 2. By combining several of these basic wiring cells 3, a wiring block 10 having 24 wiring lengths and 24 wiring layers can be constructed. 3 basic cells 2
The internal block 4 made up of the following has output terminals 5, 6, and the internal block 7fi made up of the four basic cells 2 has input terminals 8.9. 10 basic wiring cells 3 to 1
Two wiring blocks 1o are formed. In this example, two wiring data and four connection terminals 11°12.13.
It has 14.

In this embodiment, the output terminals 5, 6 of the internal block 4
When attempting to connect the input terminals 8 and 9 of the internal blocks 6 and 6 at short distances and with the same wiring length, the wiring block 1o is placed on the wiring cell array immediately below the internal blocks 4 and 7. Then, during automatic wiring, the output terminal 5 of the internal block 4 and the connection terminal 11 of the wiring block 1o, the input terminal 8 of the internal block 7 and the wiring block 1
゜ connection terminal 13, input terminal 9 of internal block 7 and connection terminal 14 of wiring block 10, and internal block 4
This connection is completed by simply connecting the output terminal 6 of the wiring block 1o and the connection terminal 12 of the wiring block 1o.

FIG. 2 is a block diagram of a master slice type semiconductor integrated circuit according to another embodiment of the present invention. An external block 15 is constituted by the input/output circuit basic cell 1 and has an input terminal 16. The output terminal 5 of the internal block 4 and the input terminal 16 of the external block 15 are connected via connection terminals 18 and 19 of the wiring block 17. As described above, in this embodiment, the basic wiring cells 3 constituting the wiring block 17 are installed not only between the columns of basic cells 2 but also between the 10th column of input/output circuit cells and the 20th column of basic cells. This makes it possible to use the wiring block 17 not only for connecting the internal blocks 4 to each other but also for connecting the external block 15 and the internal block 4 or connecting the external blocks 15 to each other.

〔Effect of the invention〕

As explained above, the present invention arranges basic cells for wiring between the basic cell rows and between the input/output circuit cell row and the basic cell row of a master slice type semiconductor integrated circuit, and consists of the basic cells for wiring. By using wiring blocks to connect internal blocks, external blocks, and internal and external blocks, wiring length can be easily controlled, resulting in a reduction in man-hours in gate array design.

It has the effect of shortening 'f'AT.

[Brief explanation of the drawing]

FIG. 1 is a plan configuration diagram of a master slice type semiconductor integrated circuit according to one embodiment of the present invention, and FIG. 2 is a plan configuration diagram of a master slice W half integrated circuit according to another embodiment of the present invention. FIG. 3 is a plan configuration diagram of a master slice type semiconductor integrated circuit in the United States. 1...Basic cell for input/output circuit, 2...
Basic cell, 3...Basic cell for wiring, 4.7...
...Internal block, 5.6...Output terminal of internal block, 8,9...Input terminal of internal block, 10.17...Wiring block, 11,
12, 13, 14.18.19... Connection terminal of wiring block, 20... Wiring area. y-¥,'-J,”,, Agent Patent Attorney Susumu Uchihara/,,,”-. Ku・-1′ Ga 1 time Rod 2 Shiman 3 times

Claims (1)

[Claims] A plurality of columns in which a plurality of first unit cells are arranged in one direction are arranged in parallel with a wiring area at a predetermined interval between the columns, and a second unit cell is arranged in parallel with the first unit cell. In a master slice type semiconductor arranged around a group of columns, a unit cell for wiring for connection between functional blocks constituted by the first unit cell or the second unit cell in the wiring region; A master slice type semiconductor integrated circuit characterized by being installed in a.