JP3251028B2 - Master slice type semiconductor integrated circuit and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for a master slice type semiconductor integrated circuit, and is particularly referred to as a large-scale function block (hereinafter, referred to as a large-scale macro) such as a ROM (Read Only Memory) and a RAM (Random Access Memory). )
The present invention relates to a macro structure of a master slice type semiconductor integrated circuit having a built-in structure and a method of manufacturing the same .

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional master slice type semiconductor integrated circuit incorporating a large-scale macro has a large number of internal basic cells 1 composed of several transistors and elements such as resistors arranged in one direction. Arrange multiple cell columns,
Large-scale macros 3, 4, and 5 such as ROM, RAM, and ALU are arranged in parallel with the internal cell array, and I / O (input / output circuit) basic cells around the large-scale macros 3, 4, and 5 and the internal cell array. In this configuration, the cell is surrounded by a cell row composed of two cells. Conventionally, in this type of master slice type semiconductor integrated circuit, the large-scale macros 3, 4, and 5 are positioned adjacent to the I / O basic cell column in consideration of the signal flow and the wiring property in automatic wiring by CAD. Was placed in

In such a master slice type semiconductor integrated circuit, a signal taken into the integrated circuit from outside via the I / O basic cell 2 is generally processed once by an internal macro composed of the internal basic cell 1. The result is input to large-scale macros 3, 4, and 5, such as RAM, and the data stored in RAM, ROM, etc. are processed therein, and finally integrated circuit via I / O basic cell 2. In most cases, it is taken out of the device.

Accordingly, as shown in FIG. 3, an I / O basic cell 2
Input / output terminals 6, 7, 8 and 9 are large-scale macro 3,
4 and 5 are not connected, but are connected to the input / output terminals 10, 11, 12 and 13 of the internal macro constituted by the internal basic cell 1. In general, the large-scale macros 3, 4, and 5 such as ROM and RAM have a complicated structure, so that it is almost impossible for other wires to freely pass through the macro. , The wiring connecting the I / O basic cell 2 and the internal basic cell 1 is provided only up to the gap between the large-scale macros 3, 4, and 5, as shown in FIG.

[0005]

In this conventional master-slice type semiconductor integrated circuit, it is impossible for other wirings to pass over a built-in large-scale macro.
All wiring connecting the O basic cell and the internal basic cell must be performed in such a manner as to avoid this large-scale macro. As a result, the wiring length between large-scale macros increases, and the signal propagation delay time increases. There were drawbacks.

In a master-slice type semiconductor integrated circuit, wiring processing between such large-scale macros is usually automated using CAD. , That is, a large number of unwirings occur.

An object of the present invention is to eliminate the above-mentioned drawbacks, thereby shortening the wiring length between internal basic cells and / or between external basic cells sandwiching a large-scale macro and improving the wiring property. To provide a master slice type semiconductor integrated circuit and a method of manufacturing the same.

[0008]

SUMMARY OF THE INVENTION The present invention provides a master slice type semiconductor device comprising a basic cell group in which a plurality of basic cells are arranged in an array, and a large-scale functional block having a structure different from the basic cells. In the integrated circuit, the rule
The functional blocks are provided on different wiring layers, respectively.
And a plurality of lateral directions and
And a signal line from an output terminal of the clock driver is connected to the horizontal and vertical wiring patterns.
Use a pattern to short circuit in a large-scale functional block.
Thus, it is characterized by being wired in a tree structure .

[0009]

The large-scale macro is electrically insulated from a wiring pattern for forming the macro, has one or more through wiring patterns penetrating the upper and lower sides or the left and right sides thereof , and has a terminal of this wiring. Is provided .

Therefore, for example, when connecting the internal basic cells arranged on the upper side and the lower side of the large-scale macro, the wiring terminal at the end of the large-scale macro and the internal basic cell are connected.
By connecting, the upper and lower sides of the large-scale macro can you to interconnect with the through wiring pattern through the, it is possible to achieve the improvement of the wiring length shortening the wiring resistance.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic layout diagram showing a main part of a first embodiment of the present invention. In the first embodiment, a plurality of internal basic cells 1 composed of elements such as transistors and resistors arranged in an array inside the integrated circuit and the periphery of the integrated circuit for interfacing signals inside and outside the integrated circuit. A plurality of I / O (input / output) basic cells 2 arranged so as to enclose a large scale macro 3, such as a ROM and a RAM, disposed between the internal basic cell 1 and the I / O basic cell 2.
In the master slice type semiconductor integrated circuit provided with the macros 4 and 5, the large scale macros 3, 4, and 5, which are the feature of the present invention, are completely provided with wirings for forming the macros inside. It includes through wiring patterns 16a to 16d and 19a to 19d arranged so as to penetrate between the upper and lower sides and between the left and right sides of the independent macro. Note that 14a to 14d, 15a to 15d, 17a to 17d, and 18a
Reference numerals 18d to 18d are connection terminals for connecting each wiring pattern to the input / output terminals of another macro. Also, 6, 7
Reference numerals 8 denote input / output terminals of an I / O macro composed of the I / O basic cell 2, and 10-13 denote input / output terminals of an internal macro composed of the internal basic cell 1. In the first embodiment, the terminal 6
Is connected to 10, 7 to 11, 8 to 12, and 9 to 13, respectively.

Here, the connection between the input / output terminal 6 of the I / O macro and the input / output terminal 10 of the internal macro is performed by using a through wiring pattern 16b provided in the large-scale macro 3. That is, the connection between the input / output terminals 6 and 10 is completed by connecting the input / output terminal 6 to the terminal 14b and the input / output terminal 10 to the terminal 15b. Similarly, input / output terminals 7 and 11, input / output terminal 8
And 12 are also performed using the through wiring patterns 16c and 16d, respectively. In addition, I / O terminals 9 and 13 are large-scale macro 3
Are connected by using a through wiring pattern 19b of a wiring layer different from the through wiring patterns 16a to 16d provided in the wiring.

In the first embodiment, the large-scale macro 3
Is 2 mm long and 1 mm wide, wiring is performed from the I / O basic cell 2 corresponding to the substantially central position of the large-scale macro 3 to the internal basic cell 1 substantially symmetrical with respect to the large-scale macro 3. In the case where it is necessary to perform wiring around the large-scale macro 3 as in the conventional example, the wiring length is 4 mm + α.
(Α is the wiring length from the I / O basic cell 2 to the vicinity of the large-scale macro 3 and the wiring length from the internal basic cell 1 to the large-scale macro 3), but according to the first embodiment, Since the wiring passes through the macro 3, the wiring length is only 2mm + α,
The wiring length can be significantly reduced.

FIG. 2 is a schematic layout diagram showing a main part of a second embodiment of the present invention, in which large-scale macros 3, 4, and 5 are arranged at positions sandwiched between internal basic cells 1. Things. In FIG. 2, reference numeral 20 denotes a clock driver composed of the I / O basic cell 2,
Signals are supplied to some of the internal macros composed of the internal basic cells 1 arranged above and below and. The output terminal 21 of the clock driver 20 is used for large-scale macros 3, 4, and 5.
Are connected to the input terminals 24 and 25 of the internal macro via the through wiring patterns 19b and 16a provided in the internal macro. Here, the internal wiring patterns 16 of the large-scale macros 3, 4, and 5 are set.
Unlike the first embodiment, a and 19b are short-circuited inside the macro, which is advantageous for a signal line configuration in which skew such as a clock signal becomes a problem. That is, in the second embodiment, the signal from the output terminal 21 of the clock driver 20 does not bypass the large-scale macros 3, 4, and 5, and the wiring is formed by using the wiring pattern provided in the macro.
It is possible to a tree structure.

[0016]

As described above, according to the present invention, a large-scale macro built in a master slice type semiconductor integrated circuit is provided with a wiring pattern completely independent of an intra-macro wiring penetrating its upper and lower sides and left and right sides. Since the wiring is provided, the wiring connecting the I / O basic cell sandwiching the large-scale macro and the internal basic cell, and the wiring between the internal basic cells sandwiching the large-scale macro are arranged in the large-scale macro without bypassing the large-scale macro. Since it can be performed using the provided wiring pattern,
In the automatic wiring using the CAD system, there is an effect that the wiring length between macros can be reduced and the wiring property can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a schematic layout diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a schematic layout diagram showing a main part of a second embodiment of the present invention.

FIG. 3 is a schematic layout diagram showing a main part of a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Internal basic cell 2 I / O basic cell 3-5 Large-scale macro 6-13 Input / output terminals 14a-14d, 15a-15d, 17a-17d, 18a-18d, 2
2, 23 terminals 16a to 16d, 19a to 19d Through wiring pattern 20 Clock driver 21 Output terminal 24, 25 Input terminal

Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 27/088

Claims (2)

(57) [Claims] A basic cell group 1. A plurality of basic cells are arranged in an array, the master slice type semiconductor integrated circuit having a large functional blocks having different structures from that of the basic cell, the large-scale features Blocks are placed on different wiring layers.
And a plurality of laterals penetrating the large block
It has a direction and a longitudinal direction of the wiring pattern, the signal line, the lateral side of the output terminal of the clock driver
Large-scale function block using vertical and vertical wiring patterns
A master-slice type semiconductor integrated circuit, which is wired in a tree structure by being short-circuited in a rack. 2. A plurality of basic cells are arranged in an array.
A basic cell group and a large cell having a different structure from the basic cell.
Master-slice semiconductor with large-scale functional blocks
In the method of manufacturing an integrated circuit, the large-scale function block
Wiring pattern to realize the function of
Bordered and upper and lower sides or left and right of large-scale function block
SideVertically and horizontally with different wiring layersPenetrateSo
Each of multipleWiring the wiring pattern in advance
WithThe vertical and horizontal wiring patterns can be
Having a process of short-circuiting in the  Prepare connection terminals at the end of the large-scale function block.
Automatically wiring the connection terminals and the basic cell group,
 For signal wiring where skew is a problemThe large-scale machine
Penetrated the upper and lower sides or left and right sides of the Noh blockTree
ofMaster slice type characterized by automatic wiring
A method for manufacturing a semiconductor integrated circuit.