JPH0143398B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor integrated circuit having a plurality of random access memories (hereinafter referred to as RAM).

Using multiple, for example, two random access memories, each with its own address, one
Display information is stored in RAM and display modification information, such as display blinking information, is stored in other RAM.
Two RAMs with one-to-one correspondence between RAM addresses.
A technique for obtaining display signals by inputting data from the same address to the same gate circuit was disclosed in Japanese Patent Laid-Open No. 56-30182.
It has been proposed in the Publication No. FIG. 1 shows configuration examples of two RAMs used in such technology.

In FIG. 1, in the RAMs 12 and 13, word lines 2 to 5 are commonly arranged in the row direction, bit lines are arranged in the column direction, and read outputs are taken out. RAM
The address decoding circuit 1 allows two
When a word line, for example word line 2, is selected that selects the same location in both RAMs, for example, the first RAM 12 and the second RAM 13, RAM cells 18 to 19 at addresses 4 to 16 of the first RAM 12, The addresses of RAM cells 20 to 21 at addresses 4 to 16 of the RAM 13 are selected, and for example, the output of address 4 of the first RAM 12 is sent to bit line 7, and the output of address 4 of the second RAM 13 is sent to bit line 7. 6, and a first gate 8 is configured using these output lines 6 and 7 as inputs. In this case, as shown in FIG.
In the conventional case, the RAM 13 is divided into separate parts to draw the photomask original drawing (hereinafter referred to as the original drawing).
Metal wiring 17 must be routed from bit line 6 of RAM 12 and bit line 7 of RAM 13 to logic gate 8, which receives data at addresses 4 of RAM 12 and 4 of RAM 13 and modifies these data. When another conductive material is passed over the metal wiring 17, tunnel wiring must be formed using a conductor 16 such as a diffusion layer or polysilicon, and contacts 14 and 15 are required for this purpose. The same applies to the second to fourth gate circuits 9 to 11. Furthermore, wiring 17 from the bit line
The bit line 6 is significantly longer than the bit line 6, and its stray capacitance and resistance increase, causing delay and a drop in level. Furthermore, since they intersect with other wiring lines 16, signal interference occurs with each other, resulting in large noise in read signals.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which redundant wiring from the RAM bit line to the logic gate, contact tunnel wiring, etc., as described above, are reduced.

The present invention provides a semiconductor device having a plurality of random access memories in which the same address is selected by the same word line, in which the random access memory cells at the same address are arranged adjacent to each other on a semiconductor substrate. It is characterized by

An embodiment of the invention is shown in FIG. In this embodiment, a plurality of RAM groups for different purposes are not arranged separately, but are arranged so that RAM cells at the same location are adjacent to each other. In FIG. 2, for example, the first RAM 12 and the second RAM 13 selected by the word line 2
RAM cells at the same address, for example, RAM cells at addresses 4, 8, etc., are arranged adjacent to each other. For this reason,
Wiring contacts and tunnel wiring for connection from the bit lines 6 and 7 at address 4 of the first RAM 12 and address 4 of the second RAM 13 to the logic gate 8 are unnecessary. That is, according to the present invention, not only the wires are shortened, but also there are no wires that cross each other. This greatly simplifies the manufacturing process and improves the reliability of the device. The same can be said of other addresses. Therefore, the bit output lines can be arranged in a small area, and a device with less noise can be realized. In addition, in the present invention,
Since the data from the two RAMs 12 and 13 only need to be supplied when the gate circuits 8 to 11 operate, the two RAMs 12 and 13 can be operated completely in parallel by a common control system, or even if they are operated separately. The operation timing may be slightly different depending on the control system. If the control systems are provided separately, the control circuits for RAMs 12 and 13 are placed close to each other due to connection to external terminals, so the control lines to the two RAMs are The intersection actually exists and does not increase the wiring area in FIG. Further, the control signal line is not required to have a low resistance like the bit line, and crosstalk does not become a problem like the data signal on the bit line.

As described above, if the present invention is used, it is possible to draw the original drawing in a smaller size, thereby reducing the chip size, which is effective in reducing the cost of semiconductor integrated circuits. Also, as shown in the embodiment, when a logic gate is configured by one RAM output and the other RAM output,
For example, data from one RAM can be transferred from one RAM to another RAM.
The present invention is especially effective when it is necessary to modify the data using the following data.

[Brief explanation of drawings]

Figure 1 is a simplified block diagram of the conventional RAM layout. In the figure, 1...RAM address decoder circuit, 2, 3, 4, 5... word line, 6, 7... bit line, , 9, 10, 11...first to fourth logic gates, 12, 13...first and second RAMs, 1
4, 15...Contact, 16...Diffusion layer or tunnel wiring such as polysilicon, 17...Metal wiring from the bit line to the logic gate, 18, 19...First
RAM cells of RAM, 20, 21... of second RAM
RAM cell. FIG. 2 is a simplified block diagram of the RAM arrangement of the embodiment of the present invention. In the figure, 1...RAM address decoder circuit, 2, 3, 4, 5... word line, 6, 7... bit Lines 8, 9, 10, 11...first to fourth logic gates, 12, 13...first and second RAMs.

Claims (1)

[Scope of Claims] 1. In a semiconductor device having a plurality of random access memories in which the same address is selected by the same word line, the random access memory cells at the same address are arranged adjacent to each other on a semiconductor substrate. A semiconductor device characterized by: 2. It has a plurality of random access memories each having a plurality of addresses divided into rows and columns, and the plurality of random access memories each have a plurality of addresses in a specified row by specifying one row. Data in memory cells is read column by column, and data read from the same address in the plurality of random access memories is input to the same gate circuit.
A semiconductor device characterized in that memory cells at the same location of access memory are arranged in adjacent columns.