KR20010002116A - Semiconductor integrated circuit using SRAM between DRAM and logic circuit as buffer - Google Patents

Abstract

PURPOSE: A semiconductor integrated circuit using a static random access memory as a buffer between a dynamic random access memory and a logic circuit is provided to improve function and reduce electric power consumption. CONSTITUTION: A semiconductor integrated circuit includes first and second pad portions, an upper memory bank portion, a lower memory bank portion, a data path for a dynamic random access memory, a static random access memory portion, and a logic circuit. The first pad portion includes power supply pads for a dynamic random access memory. The upper memory bank portion at least includes one or more dynamic random access memory banks. The lower memory bank portion at least includes one or more dynamic random access memory banks. The data path for a dynamic random access memory gives and takes a data to the upper memory bank portion and the lower memory bank portion. The static random access memory portion gives and takes a data to the data path. The logic circuit is arranged in close to the static random access memory portion, and gives and takes a data to the static random access memory portion. The second pad portion is arranged in close to the logic circuit and includes power supply pads and input and output pads for the logic circuit.

Description

Semiconductor integrated circuit using SRAM between DRAM and logic circuit as buffer}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, in particular using static random access memory (hereinafter referred to as SRAM) as a buffer between a dynamic random access memory (DRAM) and a logic circuit. It relates to a semiconductor integrated circuit.

High-end products in recent graphics systems require larger memory capacity to perform high resolution and 3D graphics functions, and also require larger bandwidths between the logic circuitry that performs the memory and graphics engine functions. Doing.

To achieve this, there is a method such as Rambus DRAM, which maximizes the bandwidth per pin and reduces the number of pins per package to be adopted in graphic systems. However, in this case, the band-per-pin also has some limitations, and by placing several components on the printed circuit board, the area of the printed circuit board is increased and the power consumed by the capacitance per pin cannot be ignored. There is a problem that the consumption is large.

As another method for realizing a high speed band between the graphics memory and the graphics engine, a recent Merged Memory with Logic (MML) structure has been proposed as another solution. In this case, a large-capacity DRAM having a plurality of inputs and outputs and a logic circuit for processing data exist on one chip. At this time, the DRAM has a plurality of inputs and outputs (512 or less). And if the graphic logic circuit uses internal data processing in fewer units than the number of I / O that DRAM has, it is more effective if SRAM is used as a buffer between DRAM and logic circuit. At this time, the SRAM has multiple ports so that one port can exchange data with DRAM through multiple inputs and outputs, while the other port can exchange data with logic circuits and less input / output. With the right size of SRAM, the SRAM can be used not only as a buffer between DRAM and logic but also as a temporary storage location. However, since the arrangement and wiring of various components such as SRAM, DRAM, and logic circuit in the memory-logic composite chip as described above are critical factors that determine the performance of the memory-logic composite chip, the area and power consumption of the entire chip. If the SRAM, DRAM, and logic circuits are not placed efficiently, the performance of the entire memory-logic complex chip is reduced, the area of the entire chip is increased, and the power consumption is increased.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor integrated circuit using a static random access memory as a buffer between a dynamic random access memory and a logic circuit, which has improved performance and may reduce an area and power consumption of an entire chip.

1 is a layout view of a semiconductor integrated circuit using a static random access memory as a buffer between a dynamic random access memory and a logic circuit according to an embodiment of the present invention.

2 is a metallization diagram in a memory cell array.

3 is a diagram illustrating a connection between a bit line, an input / output line, and a column select line in a sense amplifier region.

In accordance with one aspect of the present invention, a semiconductor integrated circuit using a static random access memory as a buffer between a dynamic random access memory and a logic circuit includes: a first pad unit including power pads for a dynamic random access memory; An upper memory bank unit disposed adjacent the first pad unit and having one or more dynamic random access memory banks; A lower memory bank unit having one or more dynamic random access memory banks; A data path for dynamic random access memory disposed between the upper memory bank unit and the lower memory bank unit to exchange data with the upper memory bank unit and the lower memory bank unit; A static random access memory unit disposed adjacent to the lower memory bank unit to exchange data with the data path; A logic circuit disposed adjacent to the static random access memory unit and exchanging data with the static random access memory unit; And a second pad unit disposed adjacent to the logic circuit and having power pads and input / output pads for the logic circuit.

The metal line provided in the first layer is called a first metal, and the metal line provided in the second layer located on a plane different from the first layer is called a second metal, and is different from the first layer and the second layer. When the metal line provided in the third layer positioned above is called a third metal, in each memory cell array of the upper memory bank portion and the lower memory bank portion, bit lines are vertically formed using tungsten, and a normal word Line enable lines are horizontally formed using the first metal, and power lines and ground lines for the memory cell array are horizontally formed using the second metal, and are used for input / output lines and the memory cell array. The power lines and the ground lines are formed vertically using the third metal so that the power lines for the memory cell array and the ground lines are connected in a net form. Preferable.

Further, in each sense amplifier region of the upper memory bank unit and the lower memory bank unit, column select lines are horizontally formed by using the first metal and the second metal, respectively, so that the column select lines are formed in each column select line gate unit. Each tungsten bit line connected to a first end and exiting from the memory cell array is connected to a second end of each column select line gate part, and a third end of each column select line gate part is tungsten, a contact, the first end; The first metal, the via, and the second metal may be connected to the input / output node, and the power lines and the ground lines for the memory cell array may be formed in parallel with the column select lines using the second metal.

Hereinafter, a semiconductor integrated circuit using a static random access memory as a buffer between a dynamic random access memory and a logic circuit will be described in detail with reference to the accompanying drawings.

1 is a layout view of a semiconductor integrated circuit using a static random access memory as a buffer between a dynamic random access memory and a logic circuit according to an embodiment of the present invention. The memory used in a typical graphics system has several memory banks. This is because interleaving multiple memory banks in graphics applications is an effective way of increasing bandwidth overall. In the embodiment of the present invention illustrated in FIG. 1, it is assumed that two memory banks of a first memory bank 12 and a second memory bank 16 exist in a DRAM area.

Referring to FIG. 1, a semiconductor integrated circuit using a static random access memory as a buffer between a dynamic random access memory and a logic circuit according to an embodiment of the present invention may include a first pad including DRAM power supply pads 11. The first memory bank 12 including DRAM, the first memory bank 12 including DRAM, the second memory bank 16 including DRAM, and the first memory bank 12 disposed adjacent to the first pad unit 10. ) Is disposed between the second memory bank 16 and the data path 14 for DRAM that exchanges data with the first memory bank 12 and the second memory bank 16, and the second memory bank 16. SRAM 18 disposed adjacently and exchanging data with the datapath 14, and in the logic circuit 20 and logic circuit 20 disposed adjacent to the SRAM 18 and exchanging data with the SRAM 18. The second pad unit 22 is disposed adjacent to each other and includes power pads for logic circuits and input / output pads.

Referring to FIG. 1, there is a first pad part 10 having power pads 11 for DRAM at the top thereof. The power pads 11 supply power used for DRAM array operation and power required for input / output operation of the DRAM. Under the first pad unit 10, a first memory bank 12, which is one memory bank of a DRAM, is present. The first memory bank 12 includes a row address strobe chain (RAS CHAIN) for row control and a row decoder (R / D) and a sense amplifier region 24 for activating a specific word line selected from an input row address. There are column decoders C / D for controlling the column select signal of the column select lines M1 & M2 CSL to be wired. The bit line (WB / L in FIG. 2) wired on the memory cell array 26 is controlled by the column select signal of the column select lines M1 & M2 CSL wired to the sense amplifier area 24 so as to be sensed. ) Is connected to the input / output line M3 I / O, and the input / output line M3 I / O is wired on the memory cell array 26 using the upper metal in the same direction as the bit line WB / L to be connected to the first cell. It is connected to a data path 14 existing between the memory bank 12 and the second memory bank 16. The bit lines existing in the second memory bank 16 are also connected to the data path 14 through the input / output lines M3 I / O in the first memory bank 12. It is connected to the datapath 14 in the same way. Meanwhile, reference numeral 34 denotes a multiplexer for connecting the input / output line of the first memory bank 12 or the second memory bank 16 to the global input / output line 33 according to the bank control signal.

The input / output line M3 I / O coming from the first memory bank 12 and the input / output line M3 I / O coming from the second memory bank 16 are global input / output through the multiplexer 34 in the data path 14. The global input / output line 33 is connected to the input / output circuits, i.e., the input / output sense amplifier I / OS / A and the write driver WRDV. Accordingly, the data path 14 shows the output of the input / output sense amplifiers I / O S / A connected to the SRAM 18 and a data input port for receiving data from the SRAM 18.

On the other hand, under the second memory bank 16, a multi-port SRAM (transmitting / receiving data through the data path 14 and the DRAM input / output line (M4 DRAM DIN / DOUT) and also exchanging data with the logic circuit 20 ( 18 is disposed, and under the SRAM 18, there is a logic circuit 20 that exchanges data with the SRAM 18. Below the logic circuit 20, a second pad portion 22 including logic power pads and logic input / output pads is disposed.

As shown in FIG. 1, a semiconductor integrated circuit using a static random access memory according to an embodiment of the present invention as a buffer between a dynamic random access memory and a logic circuit includes a data path 14 between the memory banks 12 and 16. ), The SRAM 18 under the second memory bank 16, the logic circuit 20 under the SRAM 18, and the power pads 11 for the DRAM are disposed in the upper memory bank 12. ) And by placing the power supply pads and input / output pads for the logic circuit under the logic circuit 20, it is possible to reduce the area and power consumption of the entire chip by optimizing the data path between the corresponding components to send and receive data, It has a structure that can greatly improve performance.

FIG. 2 is a metal wiring diagram in the memory cell array 26, showing the wiring of main signal lines. The wiring in the memory cell array 26 will be described with reference to FIG. 2. First, the first metal, the second metal, the third metal, and the fourth metal are assumed to be metal lines formed on different planes, and the vertical direction is parallel to the bit line (WB / L) and the horizontal direction is normal word. Define the direction parallel to the line enable line (M1 NWE). In FIG. 2, the bit line W B / L uses tungsten metal. Tungsten metal is connected to the cell transistor using direct contact (hereinafter referred to as DC) in the memory cell array 26. The tungsten bit line (WB / L) wired over the memory cell array 26 is connected to the first junction of the column select line gate transistor 38 via a sense amplifier 36 via DC, and the column select line gate transistor. The second junction of 38 is connected to the first metal M1 by DC and tungsten metal and contacts. The first metal M1 is connected to an input / output line M3 I / O of a third metal that is vertically wired on the memory cell array 26.

FIG. 3 shows a circuit diagram in which the bit line W B / L and the input / output line M3 I / O are connected by column selection lines M1 CSL and M2 CSL in the sense amplifier region 24. Here, an example is shown when 16 consecutive bit line pairs share one input / output line, that is, the column address is 4 bits. As illustrated in FIGS. 2 and 3, the column select lines M1 CSL and M2 CSL connected to the gate of the column select line gate transistor 38 may be formed by mixing the first metal and the second metal. In such a case, since the column select line of the sense amplifier region 24 can be formed within the 5-line pitch without using all eight line pitches, the area occupied by the column select line of the sense amplifier region 24 can be reduced.

Referring back to FIG. 2, all of the sense amplifier control signals wired to the existing sense amplifier region 24 in FIG. 2 are horizontally wired using the first metal M1. Input / output lines of the first metal M1 connected to the column select line gate transistor 38 are connected to the first metal M1 by successive bit lines sharing the data input / output line M3 I / O (see FIG. 3). It is connected horizontally in the region 24. An input / output node formed of the first metal M1 in the sense amplifier region 24 is connected to the second metal layer in the sense amplifier region 24 through a first via (not shown). That is, the tungsten bit line W B / L in the sense amplifier region 24 is electrically connected to the input / output node of the second metal layer through the column select line gate transistor 38.

Subsequently, an input / output node connected to the second metal layer of the sense amplifier region 24 passes through the memory cell array 26 to the data path 14 disposed in the middle of the two memory banks 12, 16 (see FIG. 1). The method and the power supply method in the memory cell array 26 will be described.

First, on the memory cell array 26, the first metal has a normal word line enable line M1 NWE wired horizontally and is connected to a secondary word line driver (not shown). In FIG. 2, the input / output line M3 I / O wired on the memory cell array 26 uses a third metal. In this case, since the input / output line only needs to wire two lines IO and IOB on the pitches of 16 consecutive bit line pairs, there is a relatively free space. Therefore, the internal power line M3 ARRAY POWER and the ground line M3 ARRAY GROUND for the memory cell array are alternately wired between the IO line and the IOB line M3 I / O. Accordingly, the I / O line M3 I / O, the power supply line M3 ARRAY POWER and the ground line M3 ARRAY GROUND for the memory cell array are wired on the memory cell array 26.

The I / O line M3 I / O of the third metal wired on the memory cell array 26 is connected to the input / output node in the sense amplifier area 24 which is wired to the sense amplifier area 24 and is raised to the second metal layer. Connected via a second via (not shown). In this way, vertically wired I / O lines M3 I / O of the third metal may be connected to the input / output nodes of all the sense amplifier regions 24, and the third metal lines thus connected may be connected to the memory cell array region 26. The data path 14 existing between the two memory banks 12 and 16 is connected through a multiplexer (not shown).

Subsequently, a power and ground connection method of the memory cell array 26 will be described. A column selection line and an input / output node are formed in the sense amplifier area 24 as the second metal. Therefore, the power line and the ground line for the memory cell array are wired horizontally using the second metal, and in the sense amplifier region 24, the third metal power line, which is alternately wired vertically over the memory cell array 26, and The power line and the ground line for the memory cell array formed of the second metal are connected to the ground line, respectively. The second metal, which is wired horizontally, is connected to a power supply line (not shown) of the LA driver which exists in a conjuction area (not shown) which is an intersection of the sense amplifier area 24 and the sub word line driver area. The LA driver is a circuit for supplying power to the bit line sense amplifiers present in the sense amplifier region 24.

The normal word line enable line M1 NWE is horizontally wired to the first metal on the memory cell array 26, and the third metal is vertically wired to the power line and the ground line for the input / output line and the memory cell array. 2 metals were not used. Therefore, the memory cell array power line M2 ARRAY POWER and the ground line M2 ARRAY GROUND are alternately wired alternately and alternately vertically wired using the second metal. It is connected to the line M3 ARRAY POWER and the ground line M2 ARRAY GROUND, respectively. When the power line and the ground line are connected as described above, the power source and the ground for the memory cell array are connected in a mesh form in the memory cell array, and the power source is a metal plate having a thick width on the memory cell array instead of the metal metal line. This has the effect of significantly improving bitline sensing, which in turn improves the low access speed of DRAM.

Now data buses coming out of the datapath 14 between the two memory banks 12 and 16 are connected to the SRAM 18 that crosses over the second memory bank 16 and is below the second memory bank 16. Since up to the third metal is used in the memory cell array 26, it is connected using a DRAM input / output line (M4 DRAM DIN / DOUT) using the fourth metal. The logic circuit side port of the SRAM 18 may use any metal, and the connection from the power supply pad 11 for DRAM to the power supply port of the DRAM is performed using a fourth metal.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. For example, in the exemplary embodiment of the present invention, it is assumed that two memory banks of the first memory bank 12 and the second memory bank 16 exist in the DRAM area, but the present invention is not limited thereto. The present invention is also applicable to a memory-logic composite chip in which a plurality of memory banks each exist. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the semiconductor integrated circuit using the static random access memory according to the present invention as a buffer between the dynamic random access memory and the logic circuit can reduce the area and power consumption of the entire chip and reduce the power supply and ground of the memory cell array. There is an advantage that can be enhanced to improve the performance of the entire chip.

Claims (3)

A first pad section having power pads for dynamic random access memory; An upper memory bank unit disposed adjacent the first pad unit and having one or more dynamic random access memory banks; A lower memory bank unit having one or more dynamic random access memory banks; A data path for dynamic random access memory disposed between the upper memory bank unit and the lower memory bank unit to exchange data with the upper memory bank unit and the lower memory bank unit; A static random access memory unit disposed adjacent to the lower memory bank unit to exchange data with the data path; A logic circuit disposed adjacent to the static random access memory unit and exchanging data with the static random access memory unit; And And a second pad portion disposed adjacent to the logic circuit and having power pads and input / output pads for the logic circuit. The method of claim 1, wherein the metal line provided in the first layer is called a first metal, and the metal line provided in the second layer located on a plane different from the first layer is called a second metal. When the metal line provided in the third layer located on a plane different from the second layer is called a third metal, in each memory cell array of the upper memory bank part and the lower memory bank part, the bit lines are vertical using tungsten. Normal word line enable lines are horizontally formed using the first metal, power lines and ground lines for the memory cell array are horizontally formed using the second metal, and input / output lines And the power lines and the ground lines for the memory cell array are vertically formed using the third metal such that the power lines and the ground lines for the memory cell array are meshed. That result a semiconductor integrated circuit according to claim. 3. The column select lines of claim 2, wherein the column select lines are horizontally formed using the first metal and the second metal, respectively, in the sense amplifier regions of the upper memory bank unit and the lower memory bank unit. Each tungsten bit line from the memory cell array is connected to a second end of each column select line gate part, and a third end of each column select line gate part is tungsten, The contact line is connected to an input / output node through the first metal, the via, and the second metal, and the power lines and the ground lines for the memory cell array are formed in parallel with the column select lines using the second metal. Semiconductor integrated circuit, characterized in that.