JPS6115347A - Semiconductor ic device - Google Patents

Abstract

PURPOSE:To contrive the reduction of wirings and the relaxation of congestion by a method wherein the part above a special block arranged in the side section rectangularly to logic cell arrays of a functional block is utilized as the region of the wiring between the functional block and input and output cells. CONSTITUTION:The functional block 2 consisting of logic cell arrays 11-1N and the special block in its side section are arranged, and input and output cells 4 are formed in the periphery of the chip by surrounding these blocks. In the region of the block 2, using the first layer metallic wiring as the lateral wiring, the passing wiring above a block 3 is made as the second layer metallic wiring. This manner can easily realize the connection of the block 2 and the cells 4 by unified handling in the CAD program if a required number of the second layer metallic wirings are kept provided on the block 3 at the step of the design.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of Defense) The present invention relates to a semiconductor integrated circuit device configured by arranging pre-designed logic cells.

[Technical defamation of inventions and their problems]

The master slice method, standard cell method, etc. are known as methods for configuring semiconductor logic integrated circuits. In these methods, logic gates, Noritsu flops, and the like are registered in advance as logic cells. Manufacturers configure desired logic circuits by arranging and wiring logic cells according to customer requirements.

Recently, in order to increase element density and circuit performance, and to reduce cost by reducing the dip size, designs have been made that incorporate special blocks in addition to functional blocks in which logic cell arrays are arranged. In such a conventional example, a portion where a plurality of logic cell arrays are arranged constitutes a functional block. In addition to this functional block, a special block is provided at the end of the chip. There are input/output cells around the chip.

Specialized bootstraps are circuit designs that are difficult to design or do not provide high performance using conventional logic cells, and require a high degree of human optimization in their design. As an example, RAM (Random Access TV)
mory), ROM(Read 0nly tvl
emory>, PLA(progr, ammabloe
A('Programmable Logic A
rray), ALU(,A,rithmetic L
ologic 1Jnit).

When such special blocks are arranged, wiring between input/output cells and functional blocks arranged around the chip becomes difficult. In other words, it is designed to bypass the functional blocks and input/output self, resulting in congested wiring.

Furthermore, as the signal wiring becomes longer, delay time increases and circuit performance deteriorates.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to shorten wiring length and alleviate wiring congestion in a semiconductor integrated circuit including special blocks, thereby improving circuit performance.

[Summary of the invention]

The present invention is characterized in that the special block is arranged on the side of the functional block in the direction orthogonal to the logic cell array, and the upper part of the special block is used as a signal wiring area between the functional block and the input/output cell. shall be. This can be done, for example, by providing pass-through wiring in advance in the design of a special block and using this to connect the functional block and input/output cells.2 [Effects of the Invention] According to the present invention, the inside of the integrated circuit can be The wiring between the functional blocks and the input/output cells is shortened, the congestion of the wiring is alleviated, and the wiring length is further shortened, resulting in improved circuit performance.

[Embodiments of the invention]

FIG. 1 shows the configuration of an embodiment of the present invention. A functional block 2 consisting of logic cell arrays 11, 12, . . The difference from the conventional example is that special block 3,
Here, the passing wiring 5 disposed across the top of the RAM (custom IC) is used as part of the connection wiring between the low-performance block 2 and the input/output cell 4. Reference numeral 6 denotes an auxiliary cell array used for testing the operation of the special block 3, but this is not necessarily required depending on the application.

In this embodiment, in the area of functional block 2, the first layer metal wiring is vertically (longitudinal direction of the logic cell array) wiring,
The second layer metal wiring is used as the horizontal wiring, and the passing wiring 5 on the special block 3 is used as the second layer metal wiring. As a result, if a predetermined number of second layer metal wirings are provided on the special block 3 at the design stage, the connection between the functional block 2 and the input/output cell 4 can be easily made through unified handling in the CAD program. It can be realized.

The input/output circuit is an input buffer shown in FIG. 2(a).

Output buffer shown in (b), 3 steps shown in (C) = 1~
An output huffer, a bidirectional buffer shown in (d), etc. can be used. (e) is (C).

It is a circuit diagram of the block shown by A, E, P, and N terminal in (d).

As a result of simulating the capacitance of the second layer metal wiring, the capacitance on the wiring area 7 between the logic cell arrays is 0, 14.
pF, 'yun, logic cell array 11.1'2°-,1
0.161) Fy'mm on N, and 0.161) Fy'mm on special block 3 due to congestion of lower layer wiring. It was 21 pFy'mm. In this way, the present example is designed to avoid signal delay due to the incidental capacitance of the passing wiring 5 due to the provision of the passing wiring 5 on the special block 3. That is, all driver r bars of the input circuit are formed in the input/output cells 4, and in the output circuit, each driver is formed using a logic cell, so that the output signal line passes through the driver before passing through the special block 3. This is what I did. That is, the cells surrounded by broken lines in FIG. 2 are formed within the input/output cells 4 around the chip, and the others are formed by combining logic cells before passing through the special bronze 93. Figure 1 is designed according to these rules.

It is preferable that the pre-passage l3il number provided on the special block 3 is determined as follows for smooth connection of the input/output cells 4 to the functional block 2.

The wiring between the input/output cells and the functional block 2 is 3 wires, 1 wire per input/output cell such as input buffer and output buffer.
There are two in the stay 1-output buffer and three in the bidirectional buffer. Therefore, the length of the input/output cell 4 corresponding to the length in the vertical direction of the special block 3 is changed to n, and the number of horizontal passing wirings on the special block 3 is selected so as to satisfy n≦T≦3n. If such a range is selected, there will be no significant excess or deficiency when using the horizontal passing wiring 5 on the special block 3 for connecting the functional block 2 and the input/output cell 4.

As described above, according to the present invention, wiring of a semiconductor logic integrated circuit having a special block can be shortened and congestion can be alleviated, and as a result, circuit performance can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a semiconductor integrated circuit according to an embodiment of the present invention, and FIGS. 2(a) to 2(e) are diagrams showing examples of input/output and cell configurations thereof. 12.12. ..., 1N... logic cell array, 2.
... Functional block, 3... Special block, 4... Input/output cell, 5... Pass-through wiring, 6... Auxiliary cell array. Applicant's agent Patent attorney Suzue Niten Figure 1 Figure 2

Claims (2)

[Claims] (1) A semiconductor formed by integrating a functional block formed by arranging multiple rows of logic cell arrays consisting of a plurality of pre-designed logic cells on a semiconductor substrate, and a special block with more advanced functionality than this functional block. In the integrated circuit device, the special block is arranged on a side of the functional block in a direction orthogonal to the logic cell array, and a passing wiring that crosses over the special block is provided as part of the connection wiring between the functional block and the input/output cells. A semiconductor integrated circuit device characterized by using the (2) The semiconductor integrated circuit device according to claim 1, wherein a driver is arranged before the passing wiring, which is the output signal line, crosses the special block.