JPH05152439A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a layout and a standard cell adapted for a high integration by utilizing two-layer interconnections in the layout of a data path type by arraying a plurality of functional cell arrays in a direction for propagating data and communicating data between the arrays. CONSTITUTION:A plurality of functional cells 11 are arrayed in an X direction to form a functional cell array 12. The arrays 12 are arranged in a Y direction for propagating data. A plurality of control signal lines 14 are arranged between the cells 12 in the X direction, and formed of first layer metal interconnections. A data bus line 16 and a power source line 17 for communicating data between the cells 11 are formed of second layer metal interconnections, and extended through the cells 11 in the Y direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a plurality of functional cell arrays arranged in a data propagating direction.

[0002]

2. Description of the Related Art Generally, a microcomputer or the like has a plurality of functional blocks such as an arithmetic logic unit (ALU) and an accumulator (ACC) for exchanging data with each other. FIG. 3 shows an example of a layout for exchanging data between such functional blocks.

As shown in the figure, each functional block is composed of a functional cell array (2) having a plurality of functional cells (1) arranged in parallel for the number of bits for which data processing is performed in parallel. A desired signal is taken into each functional cell (1) from the control signal line (3). Data transfer between the functional cell arrays (2) is performed via a plurality of data bus lines (4) provided around the functional cell arrays (2).

In the layout method described above, as the number of bits to be processed in parallel increases, the number of data bus lines (4) increases correspondingly and a larger chip area is required, so that the degree of integration is increased. Was difficult. Also,
In the case of exchanging data between the functional cell arrays (2) that are distant from each other in distance, there is also a drawback that the propagation delay of data is large because the wiring length thereof is considerably long.

Therefore, a data path type layout in which the functional cell array (2) is arranged in parallel with the data propagation direction has been considered. A layout example of the data path method according to FIG. 4 is shown. According to this method, the functional cell array (2) is arranged in parallel with the data propagation direction, and the data is transmitted and received between the adjacent functional cells (1). The wiring area can be greatly reduced and the data processing speed can be improved.

[0006]

By the way, in the functional cell (1), the power supply line (5) is generally composed of the first layer metal wiring. However, control signal line (3) and power line (5)
It is difficult to realize an efficient layout in the data path type layout in which a large number of portions where and intersect at right angles occur. That is, in this case, the control signal line (3)
If the first layer metal wiring is also used, it is necessary to provide a wiring portion of another layer (for example, a polysilicon layer) at the intersecting portion in order to prevent a short circuit, which is not preferable in terms of pattern area or signal delay characteristics. On the other hand, it is conceivable to configure the control signal line (3) with the second layer metal wiring. However, this has the drawback that the wiring area occupied by the control signal line (3) is generally very large. This is because the minimum line width and line spacing allowed in the design rule for the second layer metal wiring are generally considerably larger than those for the first layer metal wiring.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and includes a plurality of functional cell arrays each having a plurality of functional cells arranged in a data propagating direction, and the above-mentioned functions. A plurality of data bus lines and a plurality of power supply lines provided in a wiring region between the cell arrays in a direction parallel to the data propagating direction, and the control signal line is formed of a first-layer metal wiring; The data bus line and the power supply line are composed of the second layer metal wiring.

Further, the present invention is characterized in that, in the above-mentioned configuration, each functional cell is composed of a plurality of standard cells each having the same cell length in a direction orthogonal to a data propagating direction.

[0009]

According to the above-mentioned means, in the data path layout, the control signal line is composed of the first layer metal wiring, and the data bus line and the power supply line extending in the direction parallel to the data propagating direction. Is composed of the second-layer metal wiring, it is possible to achieve higher integration than the conventional data path layout.

Furthermore, since each functional cell is composed of standard cells having the same cell length in the direction orthogonal to the data propagation direction, the functional cells in parallel are arranged in the orthogonal direction. The length is determined by an integral multiple of the cell length. As a result, even if the functional cell arrays are designed independently of each other, a layout mismatch does not occur, which can contribute to the rationalization of the design.

[0011]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a layout diagram according to an embodiment of the present invention. (11) is a functional cell having, for example, an arithmetic operation function or a temporary storage function, and is arranged by the number of bits (for example, 32 bits) to be processed in parallel in the X direction in the drawing, and the functional cell array (12 ) Is configured. A plurality of functional cell arrays (12) are arranged in the data propagating direction (that is, the Y direction) with a certain distance therebetween. In the wiring region (13) between the functional cell arrays (12), a plurality of control signal lines (14) are arranged in the X direction. The control signal line (14) is composed of the first-layer metal wiring, is contact-connected to the polysilicon wiring (15), and is incorporated in the internal circuit of the required functional cell (11). Data is exchanged between the functional cell arrays (12) for each bit by a data bus line (1
6) and the input / output terminals of each functional cell (11) are connected. The power supplied to each functional cell (11) is supplied by a power supply line (17) extending in the Y direction in parallel with the data bus line (16). The data bus line (16) and the power supply line (17) are composed of a second layer metal wiring. As for the internal wiring of the functional cell (11), the first-layer metal wiring is conventionally used.

According to the layout method described above, the data bus line (16) and the power supply line (17) are connected to each functional cell (1).
1) Since it can be wired in a straight line through the inside and can intersect with the control signal line (14) without short-circuiting, the problems associated with the layout of the conventional data path method can be solved, and efficient integration can be achieved. A highly integrated semiconductor integrated circuit can be realized.

FIG. 2 shows an example of a CMOS type standard cell constituting the functional cell (11) described above. In the figure, two standard cells are shown.
The power supply line (17) of these standard cells is composed of the second layer metal wiring, and the other internal wiring is composed of the first layer metal wiring. Then, by connecting the standard cells in the data propagation direction (that is, the Y direction in the drawing), a desired functional cell (11) can be formed. These standard cells have a cell length l in the X direction.
Are preconfigured to be equal.

As a result, when the functional cell (11) is formed, the cell lengths of the functional cells (11) in the X direction become equal, and the functional cell array (12) also has the cell length in the X direction. It is determined by an integer multiple of Generally, since the functional cells (11) are arranged in parallel for the number of bits, it is guaranteed that the functional cell arrays (12) have the same length in the X direction. Therefore, since the lengths of the plurality of functional cell arrays (12) in the X direction are predetermined in the pattern designing stage, the consistency with the sizes of different functional cells (11) is examined as in the conventional case. Since it is not necessary to design and each functional cell (11) can be designed completely separately, the design period can be significantly shortened.

[0015]

As described above, according to the present invention, the plurality of control signal lines (14) extending in the X direction in the data path type layout are formed of the first layer metal wiring, and the Direction parallel to the propagation direction (Y direction)
Data bus line (16) and power line (17) extended to
With regard to the above, since it is constituted by the second layer metal wiring, a semiconductor integrated circuit having a high degree of integration can be realized.

Further according to the invention, the functional cell (11)
Since standard cells having the same cell length in the X direction are connected in the Y direction, layout consistency is guaranteed in advance, and each functional cell (11)
Have the advantage that they can be designed independently of each other.

[Brief description of drawings]

FIG. 1 is a layout diagram according to an embodiment of the present invention.

FIG. 2 is a pattern diagram of a standard cell according to an embodiment of the present invention.

FIG. 3 is a first layout diagram according to a conventional example.

FIG. 4 is a second layout diagram according to a conventional example.

Claims (2)

[Claims] 1. A plurality of functional cell arrays which are composed of a plurality of functional cells and are arranged in a data propagating direction, and a plurality of functional cell arrays which are provided in a wiring region between the functional cell arrays in a direction orthogonal to the data propagating direction. A control signal line, a plurality of data bus lines and a plurality of power supply lines provided in a direction parallel to the data propagation direction, and the control signal line is formed of a first layer metal wiring, A semiconductor integrated circuit in which a bus line and a power supply line are composed of a second layer metal wiring. 2. The semiconductor integrated circuit according to claim 1, wherein each of the functional cells is composed of a plurality of standard cells each having the same cell length in a direction orthogonal to a data propagation direction.