JPH0675930A - Parallel processor system - Google Patents

Abstract

PURPOSE:To provide a parallel processor system capable of remarkably improving the capacity of plural number of communication between PEs and the network communication with a host computer. CONSTITUTION:This parallel processor system is provided with an element column composed of a multi-port memory 2 having plural processors (PE) 1 arrayed two-dimensionally and more that at least three ports input/output parts. In the system, the multi-port memory 2 is arranged leticulately, and a first, second ports of this multi-port memory 2 are connected with a reticular data buses 4, 5, respectively and the third port is connected with the corresponded processor 1 and a reticular network is constituted on a single chip. Therefore, a parallel/super parallel super computer which is essentially suitable to a VLSI computer can be constituted, and the capacity of plural number of the communication between PEs and the network communication with a host computer can be remarkably improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processor system suitable for parallel / massively parallel computers.

[0002]

2. Description of the Related Art First, the necessity of the parallel processor system of the present invention will be described.

Generally, the improvement in the performance of a VLSI computer is largely due to the improvement in the degree of integration of the VLSI itself and the accompanying performance improvement. For example, 1.0μ
If the performance of a VLSI computer created with VLSI using the m processing technology and the performance of a VLSI computer created with VLSI using the 0.2 μm processing technology are compared in general terms, it is possible that the latter technology is used. The performance / price ratio should be better.

However, when the structure of the computer is basically the same and only the miniaturization by the processing technology is performed without changing the architecture of the computer, the LSI by the processing technology of 1.0 μm and the LSI by the processing technology of 0.2 μm are used. The density comparison is simply (1.0) ² / (0.2)
² = 25 (times), and if the LSI chip cost remains unchanged, the LSI total cost ratio between the two is 25:
It becomes 1.

On the other hand, in terms of performance, since the system divided into 25 is integrated into one chip, the loss related to inter-chip transmission (I / F) is greatly reduced,
It is expected that the efficiency (performance improvement) will be 1.5 to 2.0 times.
Furthermore, the speed of each element part in the chip has also increased with the miniaturization, and in the LSI obtained by the processing technology of 0.2 μm, the LSI obtained by the processing technology of 1.0 μm is 3
A clock frequency improvement of ~ 4 times is expected.

Therefore, for example, in a computer architecture of a single processor system, the LSI cost can be as high as Min 1/25 due to high integration of the LSI, but the performance is at most (1.5 to 2.0) × (3 ~
4) = 3 to 8 (times).

On the other hand, the pace of improvement in LSI integration is
If it takes more than 10 years from the era of 1.0 μm technology to the era of 0.2 μm technology, the performance of a VLSI computer will be 3 to 10 years at most if only high integration is achieved without changing the architecture. It will only improve 8 times. That is, with a single processor,
You will not be able to expect dramatic technological improvements.

[0008] Therefore, it has been considered to be an effective means to improve the performance by changing the architecture from a single processor to a parallel / super parallel processor. For example, one 32-bit processor processed by the 1.0 μm processing technology is configured on one chip, but 25 32-bit processors can be configured on one chip by the 0.2 μm processing technology.

That is, even if it is difficult for all of these 25 32-bit processors to operate efficiently in parallel at the same time, assuming that the parallel degree is 1/2 and 12 processors always operate in parallel, it is high. Assuming that the speedup of each element (clock level) due to integration is 3 to 4 times as described above, the performance improvement due to the parallel architecture is Total 12 × (3 to 4) = 36 in 10 years.
It will be improved to 48 times.

As described above, the architecture of the parallel / massively parallel processor greatly contributes to the improvement of the performance such as the processing speed as compared with that of the single processor, but the communication between the divided / parallelized processors, There are many problems to be solved in terms of data exchange. In particular, PE (Proc
There are various connection topologies with regard to inter-element connections, and there are various connection topologies, and the average frequency of communication, the amount of data (long) per communication, the randomness of communication partners, synchronous / asynchronous communication, and the average of communication. Due to the balance of distance (wide area communication) and the like, the connection form is mainly selected by the above-mentioned character of the application.
However, although it is possible to improve this computer for each application and for each program and optimize the connection topology between PEs respectively, in reality, this is not a good measure from an economical point of view.

On the other hand, regarding the VLSI and the module, considering the ease of implementation (manufacturability), it is important to keep both in a two-dimensional space as much as possible. For example, when comparing a cubic structure (hereinafter, referred to as N cube) such as a per-par N cube and a two-dimensional mesh structure (hereinafter, referred to as mesh structure), it is possible to realize the former connection between PEs on a two-dimensional surface. , The number of PEs (N) exceeds 100, it becomes extremely complicated. Therefore, in the N-cube, the wiring amount (length) of the chip-to-chip connection becomes large due to this complexity,
In the case of N> 1000, the wiring amount is 50 to 1 as compared with a case where adjacent chips are simply connected in a mesh structure.
It will be 00 times. That is, the ratio of the PE-to-PE connection wiring length in the N cube to the mesh structure reaches Max50.

Now, assuming that the difference in the wiring length (quantity) makes the transmission rate between chips five times, for example, the transmission time with an adjacent PE in the mesh structure is 10 ns (100 Mb /
s), which is 5 times 50 ns (20
Mb / s). Here, the number of PEs is 1024 (= 3
2 × 32), the longest transfer time in the N-cube structure is log ₂ N × τ ₁ = log ₂ 1024 × 50 (ns).
= 500 (ns), and a 100 MHz (10 ns) clock requires 50 cycles. On the contrary,
With a mesh structure, at worst (N) ^1/2 x τ ₂ = 102
4 ^1/2 × 10 (ns) = 320 (ns), 100
A clock of MHz requires 32 cycles. That is, although the N-cube structure has a smaller number of stages required for transfer, the total transfer time is shorter in the mesh structure. As described above in detail, it has been found that the two-dimensional mesh structure is effective for the architecture of parallel / super-parallel computers.

As shown in FIG. 6, a parallel processor system that constitutes a conventional parallel / super parallel computer having a two-dimensional mesh structure has processor elements (PEi, PEj ...) (Pro) having memories (Mi, Mj ...) As shown in FIG.
The processor element is X bus (Xi, Xj)
,), And a plurality of Y buses (Yi, Yj ...).

Each PE which is the key point of this conventional system
Communication between PEs is the same among PEs, and memory (M) is attached to each PE, and communication between memories is always PE.
Is done through.

This is because the memory of the conventional system is mainly for single-port input / output, and is dedicated to the exchange with the corresponding PE. However, essentially, as a communication factor between the PEs, the main task is to refer to and exchange the content data of the memory belonging to each PE.

In such a conventional parallel processor system of parallel / super parallel computers having a two-dimensional mesh structure, since the processor (PE) has an exclusive entrance / exit of the memory (M), the memories communicate with each other. There is no way to do it, and everything is done under the control of the responsible processor. That is,
This processor has its own work, and the exchange of this memory is also performed through the software of the processor. The mutual communication between the memory Mi and the memory Mj is performed by the memory Mi → processor PEi → processor PEj → memory M.
j route. As described above, the communication between the memories always requires a predetermined communication time for passing through the PE, and an appropriate waiting time is required for each step, so that the overall required time is eventually increased. Will take dozens of times longer than a single processor system. Moreover, PEi and PEj in charge of each transfer
This penalty (pen
alty) is also very large. The execution speed of PEi and PEj depends on the frequency of communication, but PEi waiting for the data is delayed several times, and PEj just waiting for the data to pass is 1.5.
~ 3 times slower.

[0017]

SUMMARY OF THE INVENTION The present invention is an improvement over the above-mentioned drawbacks of the prior art. In a parallel processor system of a parallel / massively parallel computer, which is essentially suitable for a VLSI computer, communication between a plurality of PEs is performed. Another object of the present invention is to provide a parallel computer capable of greatly improving the capability of network communication with the host computer.

[0018]

The present invention can solve the above-mentioned problems of the prior art by the following configurations.

That is, the configuration of the present invention comprises an element array in which a plurality of processor units each including a processor and a memory are two-dimensionally arranged, and the memory is provided with an input / output unit having at least three ports. A multi-port memory having the same, and the multi-port memories are arranged in a mesh, and the first and second ports of the multi-port memory are connected to a mesh data bus, and the third port is connected to a corresponding processor. It is a parallel processor system in which a mesh network is constructed on a single chip. Further, it is a parallel processor system in which the input / output Xi and Yi buses of this multi-port memory are directly connected to the external terminals of the chip through peripheral circuits in the four sides.

Furthermore, the input / output X of the multi-port memory
Transfer to the i, Yi buses is performed by group transfer of a plurality of data in row units according to the row structure inside the multi-port memory, and the address counters for the input / output Xi, Yi buses are shared, It is a parallel processor system configured to transfer simultaneously with the input / output Xi, Yi bus to a peripheral circuit and an external terminal via the input / output Xi, Yi bus or the input / output Xi, Yi bus.

Furthermore, a parallel processor system in which a plurality of the multi-port memories are arranged and the mutual data exchange between the multi-port memories is independently performed in parallel with the operation of each processor arranged in a mesh pattern. is there.

Further, a plurality of processors arranged in a two-dimensional and mesh pattern, a package accommodating the processors, input / output Xi, Yi, Zi buses for direct input / output to / from the processor, and the package A parallel processor system, which is arranged on one surface and which receives and emits data in the Z direction from the processor group to an external terminal via the Zi bus and transfers a plurality of data. .

Further, in a device comprising a plurality of processor units each including a processor and a memory arranged two-dimensionally, the memory is a multi-port memory having an input / output unit of at least three ports. , The multi-port memories are arranged in a mesh, and the first and second ports of the multi-port memory are connected to a mesh data bus and the third port is connected to a corresponding processor. Forming a network, the input and output X
The i and Yi buses are each time-divided, the Xi bus is connected to the memory during the CLOCK period, the Yi bus is connected to an external terminal and peripheral circuits, the Yi bus is connected to the memory during the CLOCK period, and the Xi bus is connected to the external terminal. It is a parallel processor system connected to peripheral circuits.

[0024]

The parallel processor system of the present invention has a plurality of two processors.
A multi-port memory comprising a multi-port memory having an array of processors and a multi-port memory having at least three-port input / output units, wherein the multi-port memory is arranged in a mesh pattern. By connecting one port to a mesh data bus and connecting the second port to a corresponding processor to form a mesh network on a single chip, communication between a plurality of PEs and a host computer The ability of network communication with can be greatly improved.

[0025]

EXAMPLES Examples of the present invention will be described below. FIG. 1 shows a parallel processor system which is an embodiment of the present invention. As shown in FIG. 1A, this parallel processor system includes a PE (1) having a 32-bit configuration and the PE (1).
32 bit X, Y bus (4)
16KB3PORT high-speed RAM connected to (5)
A plurality of PE units (3) each consisting of (2) are arranged in a mesh pattern, and the PE (1) is connected to the high-speed RAM (2) while the external host computer (6) receives a broadcast buffer ( 7) and the B (broadcast) port (8) of the optical broadcast network. These PE units (3) include RE + RAM as a set (2 ^N ) Two pieces (here, 16 pieces are arranged with N = 2) are arranged in a mesh shape, and one LS is formed as shown in FIG.
The I / O device (11) is composed of one chip (10), and the X and Y buses (3) and (4) that run vertically and horizontally in the chip are X and Y buses.
Through the Y I / O port buffer (12), the chip (1
0) Output (input) to external port (I / O pin) (13)
To be done. The number of input / output pins of this I / O pin (13) is
32 × 4 = 128 (pieces) for one channel (1ch)
Thus, the total of four sides is 128 × 4 = 512.

The Z bus (14) extending from the top of each PE (1), that is, in the Z direction is connected to the broadcast ring bus (15) in the chip (10), and further,
It is connected to a broadcast bus common to external systems. This external system-wide broadcast bus is an optical broadcast network (8).
An optical coupling link using an optical cable (16) is provided inside, and each chip (10) is connected to a host computer (6) via a broadcast buffer (7) by one or more optical cables. . Where PE
A detailed structure of the unit (3) is shown in FIG.
(A) is an enlarged view of one of the PE units arranged in a mesh. In addition, FIG.
PE (processor element) in the unit (3)
The relationship in which the memory (2) of (1) directly exchanges data with another memory (2) is schematically shown by omitting the XY bus. That is, the memory (2) is connected to the high-speed multiport R
With the AM configuration, the memories can directly exchange high-speed data directly between the memories, so that the data communication with the PEs in the other PE units can be performed quickly.

Next, the configuration when the parallel process system of the present invention is applied to a large parallel supercomputer will be described. FIG. 3 shows a case where the LSI device (11) of the parallel process system of the present invention is configured by combining 64 chips. That is, the PE shown in FIG.
Although not shown, all of the LSI devices (11) mounted with one chip, which are configured by combining 16 PE units (3) each including (1) and a 3-port memory (2), are arranged in 8 rows and 8 columns ( (8 × 8 = 64 chips).
That is, it is configured to include 1024 PE units.

In the LSI device (11), the Xi bus and Yi bus of the chip (10) shown in FIG. 1B are N, E, W and S.
Are connected to an external pin (13) via a buffer (12) and an I / F circuit (not shown) provided in each direction of the respective LSI devices (11),
Through these external pins (13), these LSI devices (1
1) xi of external buses (17, 18) provided outside
It is connected to the bus and yi bus. That is, the chip (10) in the LSI device (11) is connected to the external bus (17, 1).
According to 8), 64 pieces are connected in parallel in a mesh shape. The input / output in the Z direction of the LSI device (11) is performed by the optical cable (16) from the respective LSI devices (11) via the broadcast bus (8) common to the system described above (FIG. 1) via the broadcast buffer (7) to the host. It is connected to a computer (6).

The Xi bus of the on-chip buses (4, 5),
Yi bus and xi bus of external bus (17, 18), yi
The relationship with the bus is as shown in FIG.
K is set to two phases (phase) of CLK and / CLK according to the phase so that buses of both X and Y axes do not collide. For example, xi of the chip internal bus
The bus becomes a bus path in the order of xi → Xi → xi + 1 and also functions as a connection bus between PEs in the chip. In this way, by making the entire transfer into two phases and alternating the operations, the system configuration is simplified without lowering the overall transfer efficiency.

A massively parallel supercomputer is constructed in this way. When a part of this configuration is roughly seen, as shown in FIG. 5, input / output in the Z direction from each chip (10) is performed by an optical cable (16) via an optical connection device (19) to a host computer or the like. Connected with.

[0031]

According to the present invention, a parallel / super-parallel supercomputer essentially suitable for a VLSI computer can be constructed, and the ability of communication between a plurality of PEs and network communication with a host computer can be greatly improved. it can.

[Brief description of drawings]

FIG. 1 is a block configuration diagram illustrating a system of the present invention.

FIG. 2 is a block diagram illustrating a part of a main part of the present invention.

FIG. 3 is a system configuration diagram when the system of the present invention is applied to a massively parallel supercomputer.

FIG. 4 is an operation explanatory diagram of the system shown in FIG.

FIG. 5 is a partial external view of a massively parallel supercomputer to which the system of the present invention is applied.

FIG. 6 is a block diagram of a conventional parallel processor system.

[Explanation of symbols]

 1 PE 2 memory 3 PE unit 4 X bus 5 Y bus

Claims (6)

[Claims] 1. A multi-port memory having a plurality of processor units each including a processor and a memory, the array of elements being arranged two-dimensionally, wherein the memory is a multi-port memory having at least three input / output ports. Moreover, the multi-port memories are arranged in a mesh pattern, and the first and second ports of the multi-port memory are arranged in a mesh data bus,
A parallel processor system characterized in that a mesh-like network is formed on a single chip by connecting each of the third ports to a corresponding processor. 2. A parallel processor system in which the input / output Xi and Yi buses of the multi-port memory according to claim 1 are directly connected to external terminals of the chip in the four sides via peripheral circuits. 3. The input / output Xi and Yi buses of the multiport memory according to claim 1 are transferred by grouping a plurality of data in row units according to a row structure inside the multiport memory, and The input / output Xi, Yi bus is shared with the input / output Xi, Yi bus or the input / output Xi, Yi bus to the peripheral circuit and the external terminal to simultaneously transfer the input / output Xi, Yi bus. A parallel processor system characterized by being configured to perform. 4. A multi-port memory according to claim 1, wherein a plurality of multi-port memories are arranged, and the mutual data transfer between the multi-port memories is independently performed in parallel with the operation of each processor arranged in a mesh. A parallel processor system. 5. A plurality of processors arranged in a two-dimensional and mesh pattern, a package accommodating the processors, and inputs / outputs Xi, Y for directly inputting / outputting to / from the processor.
i, Zi buses, and a light receiving / light emitting element which is arranged on one surface of the package and which transfers data in the Z direction from the processor group to external terminals via the Zi bus and transfers a plurality of data. A parallel processor system characterized by the following. 6. A multi-port memory having a plurality of processor units each including a processor and a memory, the array of elements being arranged two-dimensionally, wherein the memory is a multi-port memory having at least three ports of input and output, and The multiport memory is arranged in a mesh, and the first and second ports of the multiport memory are connected to a mesh data bus, and the third port is connected to a corresponding processor to form a mesh network. The input / output Xi and Yi buses are time-divided, the Xi bus is connected to the memory during the CLOCK period, the Yi bus is connected to the external terminal and the peripheral circuit, and C
A parallel processor system characterized in that a Yi bus is connected to the memory and a Xi bus is connected to an external terminal and a peripheral circuit during a LOCK period.