JPH02302058A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH02302058A
JPH02302058A JP12351389A JP12351389A JPH02302058A JP H02302058 A JPH02302058 A JP H02302058A JP 12351389 A JP12351389 A JP 12351389A JP 12351389 A JP12351389 A JP 12351389A JP H02302058 A JPH02302058 A JP H02302058A
Authority
JP
Japan
Prior art keywords
terminals
functional block
overall
central part
reduced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12351389A
Other languages
Japanese (ja)
Inventor
Tetsuo Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP12351389A priority Critical patent/JPH02302058A/en
Publication of JPH02302058A publication Critical patent/JPH02302058A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To shorten the overall wiring length to make wiring efficiency good and to reduce a chip area by a method wherein, out of a plurality of functional blocks, terminals of at least one functional block are concentrated and arranged in the central part of the functional block.
CONSTITUTION: Terminals 12b to 16b for input use or for output use are arranged in the central part of a large-scale functional block 11b. When the terminals of the large-scale functional block are arranged in the central part, an overall interterminal distance to terminals of other functional blocks becomes shorter than that in conventional semiconductor integrated circuits when wiring parts are designed automatically by means of a CAD. Consequently, an overall wiring length becomes short; as a result, a signal delay time between terminals is reduced, and an irregularity in the signal delay time is reduced. Since the overall wiring length becomes short, a wiring efficiency is made good and a chip area is reduced. This becomes more effective with an increase in a scale of the functional block.
COPYRIGHT: (C)1990,JPO&Japio
JP12351389A 1989-05-16 1989-05-16 Semiconductor integrated circuit Pending JPH02302058A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12351389A JPH02302058A (en) 1989-05-16 1989-05-16 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12351389A JPH02302058A (en) 1989-05-16 1989-05-16 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH02302058A true JPH02302058A (en) 1990-12-14

Family

ID=14862470

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12351389A Pending JPH02302058A (en) 1989-05-16 1989-05-16 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH02302058A (en)

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