JPS61198759A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate the manufacture of an LSI, by activating signal output wirings in a logic LSI one by one, judging the odd and even numbers of the ON and OFF states of switch elements on the activated wirings by a parity check circuit, thereby checking the switch information simply. CONSTITUTION:A plurality of circuit blocks 11-1N are formed on one side of the substrate of a programmable LSI. Signal input wirings 3 are connected to the output sides of the blocks 11-1N through activating circuits 9. Switch elements 4 are arranged at the intersections of the wirings 3 and signal output wirings 2. Check-bit switch elements 6 are arranged at the intersections of a check bit wiring 5, which is connected to a parity check circuit 8, and the wirings 2. The wirings 2 in the LSI are activated by the circuits 9 one by one. The odd number and the even number of the ON and OFF states of the elements 4 on the activated wirings 2 are judged by the circuit 8. The switch information is checked simply, and the design and the manufacture of the LSI are facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit whose chip functions are programmable.

[Technical background of the invention and its problems]

In recent years, with the demand for semiconductor integrated circuits in small quantities and in a wide variety of products, the following LSIs have appeared.

(1) Circuit blocks used in a standard cell type LSI are registered in advance in a computer, and the computer automatically processes these circuit blocks to arrange and route them to obtain a desired final product.

(2) Gate array method The basic circuits constituting the logic gate are arranged and formed in an array on the substrate in advance, and the desired LSI is obtained by determining the wiring pattern by automatic wiring as in the standard cell method. .

These have the advantage that the development period is shorter than LSIs that are completely hand-designed. However, even these methods require a manufacturing process using lithography technology, and there is a problem that it takes several weeks to several months from the completion of the design to the completion of the LSI.

In response to this, the present applicant has previously proposed an LSI system in which the chip functions are completely field programmable (Japanese Patent Application No. 157718/1982). Its basic configuration is shown in FIG.

In the figure, circuit blocks 11, 12 . ..., 1N is pre-dedicated 1G
After the wiring process is completed, it is fabricated on the board using this method. A wiring area is provided adjacent to this circuit block area 1, and a signal input wiring group 3 and a signal output wiring group 2 that cross each other are arranged here. Each signal input wiring 3 is directly connected to the signal input terminal of the circuit block.

Each signal output wiring 2 is connected to a signal output terminal of a circuit block by a branch wiring forming one crossroad. Then, at each intersection of the signal output wiring group 2 and the signal input wiring group 3 in this wiring area, an electrical ON/OFF state for connecting the signal output wiring and the signal input wiring is written. A switch matrix is formed by providing switch elements 4 that can perform the following steps. The switch element 4 is, for example, E2
This is a MOSFET equipped with PROM or 1-bit memory.

According to this method, the functions of the chip are field programmable, so the user can electrically control the logic functions with his or her own hands, allowing the user to obtain a desired LSI with high logic functions extremely quickly. I can do it. Moreover,
It is possible to design an LSI by connecting input signals and output signals of circuit blocks having a certain logic function, and it is easy to understand even for a designer who is accustomed to logic design on a board.

By the way, with this new method, if it is possible to easily check whether the ON/OFF information on the switch matrix is written correctly, it will be useful for logic design and for checking circuit operation after the design is completed. be.

[Purpose of the invention]

In view of the above-mentioned points, it is an object of the present invention to provide a programmable LSI using a switch matrix, which is a semiconductor integrated circuit in which ON/OFF information of the switch matrix can be easily checked.

[Summary of the invention]

The present invention provides an LSI in which the functions of the chip are programmable using the above-mentioned switch matrix, and is provided with a circuit that activates the signal output wiring one by one, and turns on or off the switch elements on the activated signal output wiring. OFF
A feature is that a parity check circuit is provided to determine whether the number of states is odd or even.

〔Effect of the invention〕

According to the present invention, the switch matrix is turned on.

A programmable LSI can be obtained in which OFF information can be easily checked and is useful both for logic design and for checking circuit operation after design.

[Embodiments of the invention]

The present invention will be explained in detail below.

FIG. 1 shows the basic layout of a programmable LSI according to an embodiment. Parts corresponding to those in FIG. 3 are given the same reference numerals as in FIG. 3. As shown in the figure, a plurality of circuit blocks 11, 12, . . . , IN are formed on one side of the S1 wafer to form a circuit block region 1. Each circuit block is comprised of one or more logic functional elements, such as a 4-input NAND gate. This logic function element has, for example, an 0MO8 configuration, and is a dedicated IC, that is, a hand-drawn standard cell in a standard cell system, or a pre-wired gate array. Complex logic functional elements may be formed by interconnecting various standard cells in a standard cell manner.

A specific example of the configuration of the circuit block area is as follows.

(1) Block with two 4-input NAND gates 15 pieces (2) Block with four 2-input NAND gates
...14 pieces (3) 8 inputs N
Block with one ANO gate
...1 block (4) 100 blocks with 4 inverters (5) 8-bit register block ...19
(6) Block with two D type flip-flops...19 locks
...17 pieces (8) 2 to 1
Block with 4 data selectors
・・・・・・
... 13 (9) 4-bit binary counters, 2
Tsumtsu block ・・・・・・１
1 (10) Block with two 2-4 line decoders... 7 (11) Block with 3-8 line decoders...
...Block with two 3 (12) 4-1 selectors...
・Block with 5 (13) 8-1 selectors...
4 (14) blocks with 8-bit serial parallel output shift registers...3 (14) blocks with 8-bit serial parallel output shift registers
5) Block with 8-bit parallel input and serial output shift registers...3 pieces (16) 8
Block with bit serial input/serial output shift register 2 pieces (17) Block with 2 monostable multivibrators
・・・・・・4 (18) Blocks with 4 2-input OR gates
・・・・・・4 pieces (19
) Block with four 2-input NOR gates
・・・・・・3 pieces < 20) AND
-Block with two OR inverters
...
... 3 (21) 64-bit RAM blocks
・・・・・・3 pieces (22>2 input EXCLUS
A block with four IME-OR gates...
...2 pieces <23> 4-bit comparator block...3 pieces (24) Block with two flip-flops on J-

・・・・・・ 4 (25) 9-bit even/
Odd parity generator/checker block
...3 pieces (26) 4-bit binary full adder block ...2 pieces (27) Block with 4 2-input multiplexers ...5 pieces (2B
) Block with 4 S-R latches...2 pieces (
29) ALU block ・・・・・・1
(30) 8-bit addressable latch blocks
...1 piece (31) Look-ahead carry generator block ...1 or more, 27
A circuit block consisting of four MSIs is formed in circuit block area 1, and can be used as a type of chip to an LS with various functions.
It is now possible to create I. The average number of inputs and outputs of each circuit block is 8 and 4, respectively. The input section and output section of the logic functional element serve as the input section and output section of the circuit block, and each output section is provided with an output buffer (not shown).

The output portion is fixedly connected to the signal output wiring 2 so as to form a T-junction, and the input portions are respectively connected to the signal input wiring 3 that intersects with the output wiring 2. A switch element 4 is provided at each intersection of the signal output wiring 2 and the signal input wiring 3 to form a switch matrix.

This switch element 4 is turned ON by external control, for example.
, is an E2 FROM in which an OFF state can be electrically written, and thereby the signal output wiring 2 and the signal input wiring 3 can be connected. In other words, the wiring of the input/output section basically requires only one switch, and as is clear from Figure 1, the length of the equipotential wiring associated with one current path is 2 on average when the length of the side of the wiring area is 2. It will be .5a.

In the present invention, in such a programmable LSI,
A circuit is provided to determine ON/OFF information of the switch matrix. That is, a check bit wiring 5 is provided that runs parallel to the signal input wiring 3, and a switch element 6, which is the same as the switch element 4 on the switch matrix, is provided at the intersection of this wiring 5 and each signal output wiring 112. A check bit switch element array 7 is prepared. The switch elements 6 on this switch element array 7 are turned on so that the number of ON or OFF states of the switch elements on each signal output wiring 2 is an odd number or an even number.

The OFF state is set. That is, the ON and OFF states of the switch elements 6 on the switch element array 7 are used as checks and bits. Reference numeral 8 denotes a parity check circuit, in which a signal input wiring 3 and a check hit wiring 5 are connected in parallel to an input terminal. 9 is for performing a parity check for each signal output wiring 2.
This circuit activates the signal output wiring 2 one by one, and is provided between the circuit block area 1 and the switch matrix.

FIG. 2 shows a specific configuration of the activation circuit 9. As shown in FIG.

This activation circuit 9 is an example in which a shift register is used to sequentially select the signal output wiring 2, and only a portion corresponding to one circuit block 11 is specifically shown in the figure. Similar configurations are repeated for the configurations of portions corresponding to other circuit blocks. As shown in the figure, the output terminal of the shift register 91 and the output terminal 10 of the circuit block 11
0 and lead to terminal 99, AND
Gates 92, 93, inverter 94 and OR gate 95
has. 96 is a control terminal for parity check, 97
is an input terminal of the shift register 91, and 98 is a clock terminal of the shift register 91.

With such a configuration, the desired logic function is determined by turning on and off the switch elements 4 on the switch matrix as described above.
It is programmed by setting F. Further, the switch elements 6 on the check bit switch element array 7 are set so that the number of ON or OFF states of the switch elements on the signal output wiring 2 is an odd number or an even number.

In normal logic operation, the control signal applied to the parity check control terminal 96 is set to "O". As a result, the AND gate 92 is disabled, and the AND gate 93 is disabled.
becomes conductive, and the information at the output terminal 100 of the circuit block passes through the activation circuit 9 and is transmitted to its output terminal 99. In this way, the output signal of each circuit block is
The signal is supplied to the signal output wiring 2 on the matrix, and a desired logical operation is performed. Turn on the switch matrix.

When checking the OFF information, 1" is applied to the parity check control terminal 96. As a result, the AND gate 92 becomes conductive and the AND gate 93 becomes disabled. Then, 1" is input to the shift register 91. By sequentially shifting this, the output terminal 9 of the activation circuit 9
The signal output wirings 2 on the switch matrix are activated one by one by sequentially outputting "°1".When the switch elements on the activated signal output wirings 2 are in the ON state, 1'' is input to the parity check circuit 8, and at the OFF position, °O'' is input to the parity check circuit 8, respectively.

In this way, the parity check circuit 8 sequentially determines whether the number of ON or OFF states of the switch elements arranged along each signal output wiring 2 is odd or even, and whether the ON or OFF information of the switch matrix is correct. It can be determined whether or not.

As described above, according to this embodiment, it is possible to determine whether or not the ON/OFF information pattern on the programmed switch matrix is correct by adding a relatively simple circuit, thus facilitating logic design. This makes it possible to realize a programmable LSI in which circuit operation can be easily checked after logic design.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, a shift register is built in as an activation circuit for parity check, but a selector is built in instead of a shift register, and a single signal output wiring is used for parity check. It can also be configured to activate.

In addition, the present invention can be modified in various ways without departing from its spirit.

[Brief explanation of drawings]

FIG. 1 shows a programmable LSI according to an embodiment of the present invention.
2 is a diagram showing the specific configuration of the activation circuit, and FIG. 3 is a diagram showing the layout of the basic programmable LSI according to the earlier application. 11.12. ..., 1N... circuit block, 2...
・Wiring for signal output, 3... Wiring for signal input, 4...
Switch element, 5... Check bit wiring, 6.
... Switch element for check bit, 7... Switch element array for check bit, 8... Parity check circuit, 9... Activation circuit, 91... Shift register, 92.93...・AND gate, 94... Inverter, 95... OR gate, 96... Control terminal for parity check, 97... Shift register input terminal, 97... Clock terminal, 99... Activation Circuit output terminal, 100...Circuit block output terminal. Applicant's representative Patent attorney Takehiko Suzue Figure 2::;: Figure 3

Claims (2)

[Claims] (1) Built into the board, it has its own logical function;
and a plurality of circuit blocks having a signal input section and a signal output section, and a wiring region formed on the substrate adjacent to a circuit block region including the plurality of circuit blocks, the circuit block region is composed of a set of multiple types of logic functional elements, the wiring area is composed of a signal input wiring group and a signal output wiring group that intersect with each other, and the signal input wiring group is connected to the signal input section of each circuit block. The signal output wiring group is connected to the signal output section of each circuit block, and these connections are made in the wiring area adjacent to the circuit block, and the signal input wiring group is connected to the wiring area where the circuit block is adjacent to the signal output wiring group. A switch element is provided at each intersection of the group and the signal output wiring group, and by controlling the ON/OFF state of this switch element, the input/output relationship between each circuit block is determined and a desired logic circuit is created. The integrated circuit to be constructed is provided with a circuit that activates the signal output wiring one by one, and a parity circuit that determines whether the number of ON or OFF states of the switch elements on the activated signal output wiring is odd or even. - A semiconductor integrated circuit characterized by having a check circuit. (2) A check bit wiring is provided parallel to the signal input wiring, and a switch element in which an ON or OFF state is written as a check bit is provided at the intersection of the check bit wiring and each signal output wiring. A semiconductor integrated circuit according to claim 1.