JPH0566744B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A gate array equipped with RAM.
The length of the channel wiring is shortened by dividing the section into several parts and providing channel regions at the boundaries.

[Industrial application field]

The present invention relates to a gate array equipped with RAM,
In particular, the RAM section (hereinafter, including cells, sense amplifiers, write amplifiers, drivers, decoders, etc.)
This invention relates to improvement of channel wiring in a configuration in which a RAM area (RAM area) is provided around the chip 1 and a gate array is provided in the center.

Figure 5 shows an example layout of the RAM and gate array, with four RAMs located around the chip.
3, and a gate array section 2 is arranged in the central part. 4 represents pad. By arranging the gates in one place and preventing them from being cut in the RAM section in this way, there is an advantage that the degree of freedom in interconnection of the gate array can be ensured.

[Conventional technology]

In recent years, the RAM section has been increasing.
The RAM section occupies a large area, and in particular, in the arrangement shown in FIG. It is often necessary to wire the internal gate 5 on the array side. Therefore, a situation occurs in which the channel wiring length becomes long.

[Problem that the invention seeks to solve]

As the channel wiring becomes longer, stray capacitance and wiring resistance increase, which hinders the increase in operating speed and causes fluctuations in input and output voltage levels.

[Means for solving problems]

In the present invention, as conceptually shown in FIG. 1, the RAM section 3 is divided into several parts (in this case, two) in terms of layout, a channel area 7 is provided at the boundary between the parts, and the length of the channel wiring 6 is determined. The above problem is solved by making it shorter.

As for how to divide the RAM section, even if the circuit itself is the same as the conventional RAM section, the memory cell area,
Channels can be easily secured by dividing the area into a decoder area, driver area, amplifier area, etc. in terms of layout.

The structure of the present invention is as shown below. That is,
The present invention provides a RAM section having a gap at least at one location between a memory cell region and an attached region other than the memory cell region such as a decoder region, a driver region, a sense or write amplifier region, or a hold circuit region; It has a configuration as a RAM-mounted gate array characterized by having signal wiring that is formed in a wiring layer above the RAM part forming area and that penetrates the RAM part.

[Effect]

As mentioned above, by dividing the RAM section and providing channel areas at the boundaries, the channel wiring can be shortened, its stray capacitance and wiring resistance reduced, speeding up the circuit, and improving the input/output level. This makes it possible to reduce fluctuations in

〔Example〕

FIG. 2B shows an embodiment in which wiring is provided from pads 4 around the chip 1 shown in FIG. 2A to the gate array section 2 across the RAM section 3.

In FIG. 2B, 9A and 9B are RAM cell areas, in which an X (column) decoder area 15 and an X driver area 16 are arranged in the center, and a Y decoder area 17 is also arranged. RAM cell section 9
Hold circuits 10A and 10 are on the left and right of A and 9B.
Y driver areas 12A and 12B connected to bit lines are arranged on the row side of RAM cells 9A and 9B.
12B and sense/write amplifier areas 11A, 11
B is placed. 4A is a pad for inputting the RAM, 5 is an internal gate (configured in the gate array section 2), and 13 is an input port of the RAM.
4B is a pad for outputting the RAM, 8 is an output gate, and 14 is an output port of the RAM.

These arrangements and configurations themselves are common and will not be particularly explained.

In the embodiment of the present invention, the X decoder 15, the
A gap is provided between the B and Y drivers 12A, 12B and the sense/write amplifiers 11A, 11B to form channel regions 7A, 7B (shaded areas).

The cell area 9 crosses the channel areas 7A and 7B.
The only wiring that connects A, 9B and the X driver area 16 is the word line W, so only one layer of wiring is required.
The wiring connecting 2A and 12B can also be combined into one layer of wiring. Other channel areas 7A, 7B
Since there is no wiring that needs to cross the channel area, the wiring that crosses the channel area can be combined into, for example, the first layer wiring, and the second layer wiring can be reserved for the channel areas 7A and 7B.

Thereby, as shown in FIG. 2B, it becomes possible to pass the wiring 6A from the input pad 4A to the internal gate 5 via the channel region 7A without bypassing the RAM section.

On the other hand, the pad 4B on the output side of the RAM can be connected to the output gate 8, and its output can be connected to the output port 14 of the RAM via the channel region 7B with a wiring 6B.

FIG. 3 shows another embodiment of the invention. FIG. 2B shows an embodiment in which wiring is routed from the pad 4 on the chip 1 shown in FIG. A to the gate array section 2 over the RAM section 3.

In FIG. 3B, the same parts as in FIG. 2B are designated with the same numbers. In this case, as is clear from the figure, the arrangement of the cell parts 9A and 9B and the X decoder region 15 and the X driver region 16 in the center thereof is the same as in the conventional case.
A, 9B and Y driver area 12A, 12B and X
A space is provided between the driver 16 and the Y decoder 17 to ensure a channel area 7C.

Y driver areas 12A, 12B, sense/write amplifier areas 11A, 11B shown above
RAM cell areas 9A, 9B are bit lines 19A,
Since they are only connected by 19B, only one layer of wiring is required. Therefore, for example, it is possible to combine the bit lines 19A and 19B to be connected into only the second wiring layer and secure the channel region 7C in the first wiring layer, and by passing the signal line through the region 7C, wiring can be performed. The length can be shortened.

Although the embodiments have been illustrated and described above, various modifications can be made to the present invention. For example, channel regions 7A, 7B, and 7C in FIG. 2B and FIG. 3C can be used together.

For example, secure 7A and 7B in the second wiring layer,
It is sufficient to secure 7C that intersects this in the first wiring layer. However, care must be taken to avoid crossing power lines.

Furthermore, the division of the RAM section can be considered in ways other than the above example. For example, hold circuit areas 10A and 10B are connected to cell areas 9A and 9B only by word lines.
A channel area can also be secured by providing a gap between them.

In the present invention, the width of the above-mentioned channel region secured across the RAM section is formed as narrow as necessary to suppress the increase in the length of word lines and bit lines due to division of the RAM section. to prevent a decrease in operating speed.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, in a gate array equipped with RAM, channel wiring can be formed without bypassing the RAM section. This makes it possible to reduce fluctuations in the output voltage level.

[Brief explanation of the drawing]

Fig. 1 is a conceptual diagram of the present invention, Fig. 2 A and B are a plan view and a layout diagram of main parts, respectively, for explaining an embodiment, and Fig. 3 A and B are for explaining the configuration of another embodiment. FIG. 4 is a schematic diagram of a conventional example, and FIG. 5 is a plan view showing an example of the layout of a conventional gate array equipped with a RAM. (Main code), 1...chip, 2...gate/
Array, 3... RAM section, 4... Pad, 5...
Internal gate, 6, 6A, 6B...channel wiring,
7,7A to 7C...channel area.

Claims (1)

[Claims] 1. There is a gap in at least one place between the memory cell area and an attached area other than the memory cell area such as a decoder area, a driver area, a sense or write amplifier area, or a hold circuit area. A gate array equipped with a RAM, comprising a RAM section and a signal wiring that is formed in a wiring layer above the RAM section forming area and that penetrates the RAM section.