JP2996324B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a dynamic random access memory (DR).
AM) etc. relates to a layout configuration of a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Several layouts have been proposed by companies for 64MDRAM. FIG. 3 is a layout diagram showing an example of such a case, in which a peripheral circuit section 34 that is long in the short side direction is arranged at the center of the chip 30 in the long side direction.
Other circuits are symmetrically arranged on the left and right sides of the peripheral circuit section 34.

That is, on the left and right sides of the peripheral circuit section, a cell array section 31 having sense amplifiers and 16M cells is arranged in a vertical direction (short side direction) with a row address decoder 32 interposed therebetween.
In two layers. A column decoder 33 is provided between each cell array unit 31 and the peripheral circuit unit 34.
Are provided, and pad regions 35 are arranged outside the respective cell array portions in the short side direction along the long side of the chip.

In this layout example, a column address decoder 33 is provided for each cell array section 31, but a row address decoder 32 is commonly used for upper and lower cell array sections.

FIG. 4 is a diagram showing another layout example of a 64MDRAM. In this example, a pad region 45 extending in the long side direction is arranged at the center of the chip 40 in the short side direction, and peripheral regions are provided above and below the chip region. A circuit section 44 is provided, and other circuits are arranged symmetrically with respect to the pad area.

That is, cell arrays 41 having 16M cells and sense amplifiers are arranged at four corners of a chip 40,
In the long side direction, a column address decoder 43 is arranged between the two sets of cell array units 41, and a row address decoder 42 is arranged between each cell array unit 41 and the peripheral circuit unit 44.

In this layout example, the row address decoder 42 is provided for each cell array section 41, but the column address decoder 43 is commonly used for the left and right cell array sections.

In this example, since the pads are arranged in the center of the chip, when assembling the package, a lead frame having a LOC (lead-on-chip) structure in which the leads are extended on the chip is provided. Is used. That is, the lead frame is mounted on the chip, and the signal lead 1a, the power supply ( _VCC or GND) lead 1b, and the pad on the chip are connected by the bonding wire 2.

[0009]

In the above-mentioned first conventional example, two pad areas are arranged on the upper and lower sides, and in the second conventional example, the row address decoder is divided into two places in the short side direction. This disadvantageously increases the size in the short side direction.

Further, in the conventional example, since the row address decoder extends in the long side direction, that is, the word line runs in the short side direction, the structure is difficult to reduce in the short side direction. . Normally, polysilicon is used for the word line. However, in order to reduce the resistance of the word line, it is necessary to arrange an Al wiring on the polysilicon and connect it to the wiring at a plurality of locations. This is because it is necessary to secure in the short side direction.

As a result, in the conventional example, the size in the short side direction is 12 to 13 mm, and it has been difficult to store it in a 500 mil package. In the first conventional example, LOC
Since it does not correspond to the structure, the package has also been enlarged accordingly.

Further, in the second conventional example, the LOC
When assembling a package, the bonding between the input / output signal lead 1a and the pad must be performed across the power supply lead 1b, resulting in an increase in the thickness of the package, resulting in a TSOP (Thin Small Outline Package). It has a structure that is difficult to mount on a thin package such as the above.

[0013]

A semiconductor integrated circuit device according to the present invention is provided with a peripheral circuit region and a pad region which do not include a decoder occupying almost the entire length in the short side direction at the center in the long side direction. A plurality of divided cell array sections are stacked in two stages with a column address decoder sandwiched in the short side direction, and a cell array section sandwiched with a row address decoder in the long side direction.
Rays are arranged in pairs .

[0014]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a layout diagram of an MDRAM. As shown in the drawing, in the present embodiment, a peripheral circuit portion 14 extending in the short side direction is arranged at the center of the chip 10 in the long side direction, and the pad region 1 is formed.
5 are disposed on both the left and right sides of the peripheral circuit section 14.

The other circuits are arranged in a left-right symmetrical area with the pad area 15 and the peripheral circuit section 14 interposed therebetween. That is, on each side, the cell array units 11 are arranged in two stages with the column address decoder 13 extending in the long side direction in the short side direction, and similarly, the row address decoders 12 extending in the short side direction in the long side direction. , Cell array units 11 are arranged in two stages. Here, in each cell array section 11, memory cells for 8M and sense amplifiers attached thereto are arranged. A row address predecoder 16 provided on the upper side of the chip as needed.
Is arranged.

In this embodiment, each row address decoder 1
2 is commonly used by the two cell array units 11 on the left and right, and each column address decoder 13 is shared by the two cell array units on the upper and lower sides.

In this embodiment, no pad region is provided in the short side direction, and only one column address decoder exists in this direction, so that the size in the short side direction can be reduced. it can. In this embodiment,
Since a word line which needs a contact with a reinforcing wiring for low resistance runs in the long side direction, the configuration is more advantageous for reduction in the short side direction. Therefore, according to the present embodiment, the size in the short side direction can be made 11 mm or less, and can be easily accommodated in a 500 mil package.

When the present embodiment is mounted on a LOC package, the bonding wires 2 connecting the signal leads 1a of the lead frame and the bonding pads can be wired so as not to extend over the power leads 1b. Therefore, it can be easily accommodated in a thin package such as TSOP.

FIG. 2 is a layout diagram showing a second embodiment of the present invention. In the figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals with the same last digit. In this embodiment, a pad region 25 extending in the short side direction is provided at the center of the chip 20 in the long side direction, and the peripheral circuit section 24 is arranged on both left and right sides thereof.

A cell array section (including sense amplifiers), a row address decoder, and a column address decoder, which form a repetitive circuit on the left and right sides of the pad area 25 and the peripheral circuit sections 24 on both sides thereof, are arranged symmetrically. That is, on each side, the cell array unit 21 having 4M memory cells is arranged at the center of the column address decoder 2 in the short side direction.
3, two pairs are arranged on the upper and lower sides of the row address decoder 22 in the long side direction. An additional peripheral circuit section 24 is provided between the cell array sections 21 where no row address decoder exists.
And a pad region 25 are provided.

In this embodiment, as in the first embodiment, the row address decoder is shared by the left and right cell array sections. However, the number of cells selected by one word line is the same as that of the first embodiment. Access speed is faster because it is half of the case. In the present embodiment, since the pad region 25 is divided into a chip central portion, a left wing portion, and a right wing portion, the signal lead 1a extending from the far end side of the chip has a left or right wing pad region. Bonding can be performed, and an increase in input / output terminal capacitance due to leads can be suppressed.

[0022]

As described above, in the semiconductor integrated circuit device according to the present invention, the peripheral circuit and the pad region are arranged at the center in the long side direction so as to be long in the short side direction. , A two-stage cell array section is arranged so as to sandwich a column address decoder. There is no pad area in the short side direction, and cells of two cell array sections can be selected by one address decoder. Therefore, according to the present invention, it is possible to reduce the size of the chip in the short side direction, and it is easy to store the chip in a severe package in the short side direction. Further, by providing the pad region at the center in the long side direction, the LOC structure can be mounted. At this time, the connection between the pad and the external lead can be performed without straddling another lead. It can also be stored in a thin package typified by.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a first embodiment of the present invention.

FIG. 2 is a layout diagram of a second embodiment of the present invention.

FIG. 3 is a layout diagram of a first conventional example.

FIG. 4 is a layout diagram of a second conventional example.

[Explanation of symbols]

 1a Lead for signal of lead frame 1b Lead for power supply of lead frame 2 Bonding wire 10, 20, 30, 40 Chip 11, 21, 31, 41 Cell array unit 12, 22, 32, 42 Row address decoder 13, 23, 33, 43 Column address decoder 14, 24, 34, 44 Peripheral circuit unit 15, 25, 35, 45 Pad area 16, 26 Row address predecoder

Claims (3)

(57) [Claims] 1. A central portion of the long side direction, the peripheral circuit portion and a pad region including no decoder substantially entire central region occupying the length of the short side direction is provided, the cell array divided into a plurality, the short side direction two-tiered across the column address decoder, the left of the central region in the longitudinal direction
A semiconductor integrated circuit device arranged in pairs in each of the right regions with a row address decoder interposed therebetween. 2. The right and left sides of the central area in the long side direction.
A plurality of cell array pair is provided in the region of Les, the semiconductor integrated circuit device according to claim 1, wherein the additional peripheral circuit region and a pad region between the Serua <br/> ray unit pairs are provided. 3. A system for a row address along a long side direction.
3. The semiconductor integrated circuit device according to claim 1, further comprising a predecoder .