JP2841398B2 - CMOS integrated circuit - Google Patents
CMOS integrated circuitInfo
- Publication number
- JP2841398B2 JP2841398B2 JP63308202A JP30820288A JP2841398B2 JP 2841398 B2 JP2841398 B2 JP 2841398B2 JP 63308202 A JP63308202 A JP 63308202A JP 30820288 A JP30820288 A JP 30820288A JP 2841398 B2 JP2841398 B2 JP 2841398B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- power supply
- ground
- diffusion layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はCMOS集積回路に関する。Description: TECHNICAL FIELD The present invention relates to a CMOS integrated circuit.
CMOS集積回路は、大規模化，高速化，多ピン化が著し
く、それにつれ出力バッファ等の貫通電流などにより電
源配線や接地配線に発生するノイズで入力バッファ等の
入力レベルの悪化が著しくなってきている。In CMOS integrated circuits, the scale, speed, and number of pins have been remarkably increased, and accordingly, the input level of the input buffer and the like has significantly deteriorated due to noise generated in the power supply wiring and the ground wiring due to the through current of the output buffer and the like. ing.
このような入力レベルの悪化をおさえる従来の技術と
しては、第６図に示すように、周辺の出力バッファに接
続される電源や接地用の金属配線（6,8）と、入力バッ
ファを含んだ内部領域の電源や接地用の金属配線（7,
9）を半導体チップ取り出し部（4,5）から分けて設け、
電源電位や接地電位の均一化をはかるものが一般であ
る。As a conventional technique for suppressing such deterioration of the input level, as shown in FIG. 6, a metal wiring (6, 8) for power supply and ground connected to a peripheral output buffer and an input buffer are included. Power and ground metal wiring (7,
9) is provided separately from the semiconductor chip take-out section (4, 5).
Generally, the power supply potential and the ground potential are made uniform.
上述した従来のCMOS集積回路では、電源配線や接地配
線を半導体チップ上に張りめぐらすことによってノイズ
を低減しようとするものであるが、大規模化，高速化，
多ピン化の動きに十分対応できないという欠点がある。In the conventional CMOS integrated circuit described above, the power supply wiring and the ground wiring are laid on the semiconductor chip to reduce the noise.
There is a drawback that it cannot sufficiently cope with the movement of increasing the number of pins.
本発明の目的はCMOS集積回路における電源配線や接地
配線に発生するノイズの影響を低減することにある。An object of the present invention is to reduce the influence of noise generated on a power supply wiring and a ground wiring in a CMOS integrated circuit.
本発明のCMOS集積回路は、半導体チップに素子領域と
配線領域を交互に配置してなるCMOS集積回路において、
電源配線（又は接地配線）に接続されたＮ（又はＰ）型
拡散層であってＰ（又はＮ）型半導体基板に選択的に設
けられたもの又は接地配線（又は電源配線）に接続され
たＰ（又はＮ）型拡散層であってＰ（又はＮ）型半導体
基板に設けられたＮ（又はＰ）ウェルに選択的に設けら
れたものを前記配線領域に備えているというものであ
る。A CMOS integrated circuit according to the present invention is a CMOS integrated circuit in which element regions and wiring regions are alternately arranged on a semiconductor chip.
An N (or P) type diffusion layer connected to a power supply line (or a ground line) selectively provided on a P (or N) type semiconductor substrate or connected to a ground line (or a power supply line) The wiring region includes a P (or N) type diffusion layer selectively provided in an N (or P) well provided in a P (or N) type semiconductor substrate.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）は本発明の関連技術のもののレイアウト
図、第１図（ｂ）は第１図（ａ）の接地配線で挟まれた
配線領域の拡散層のレイアウト図、第１図（ｂ）は第１
図（ａ）の電源配線で挟まれた配線領域の拡散層のレイ
アウト図である。FIG. 1 (a) is a layout diagram of a related art of the present invention, FIG. 1 (b) is a layout diagram of a diffusion layer in a wiring region sandwiched between ground wirings in FIG. 1 (a), and FIG. b) is the first
FIG. 3 is a layout diagram of a diffusion layer in a wiring region sandwiched between power supply wires in FIG.
この関連技術のものは、半導体チップに素子領域と配
線領域を交互に配置してなるＮウェル方式のCMOS集積回
路において、接地配線109−1,109−２にコンタクト穴を
介して接続されたＮ型拡散層113であってＰ型半導体基
板118に選択的に設けられたもの及び電源配線107−1,10
7−２にコンタクト穴を介して接続されたＰ型拡散層117
であってＰ型半導体基板118に設けられたＮウェル115に
選択的に設けられたものをそれぞれ領域110−１及び110
−２に備えているというものである。This related art is an N-well type CMOS integrated circuit in which element regions and wiring regions are alternately arranged on a semiconductor chip, and an N-type diffusion connected to ground wirings 109-1 and 109-2 through contact holes. A layer 113 selectively provided on the P-type semiconductor substrate 118 and the power supply wirings 107-1 and 107;
P-type diffusion layer 117 connected to contact point 7-2 via a contact hole
And selectively provided in an N well 115 provided in a P-type semiconductor substrate 118, in regions 110-1 and 110, respectively.
-2.
なお、配線領域110−１はＮチャネル領域111−1nと11
1−2nにはさまれた、第１の金属配線112−１及び第２の
金属配線112−２のみで専有される配線領域、配線領域1
10−２はＰチャネル領域111−2pと111−3pにはさまれ
た、第１の金属配線及び第２の金属配線のみで専有され
る配線領域である。配線領域110−１には、図の上下に
それぞれあるＮチャネル領域に存在する接地配線109−
１と109−２との間に、Ｐ型半導体基板118内にＮ型拡散
領域113を有している。又配線領域110−２には、図の上
下にそれぞれあるＰチャネル領域に存在するＰ型半導体
基板内に設けられたＮウェルを拡張してなるＮウェル11
5内にＰ型拡散領域117を有している。Note that the wiring region 110-1 is connected to the N channel regions 111-1n and 11-1n.
A wiring region 1 and a wiring region 1 exclusively occupied by only the first metal wiring 112-1 and the second metal wiring 112-2,
Reference numeral 10-2 denotes a wiring region sandwiched between the P channel regions 111-2p and 111-3p and exclusively used by the first metal wiring and the second metal wiring only. The wiring region 110-1 has a ground wiring 109-
An N-type diffusion region 113 is provided in a P-type semiconductor substrate 118 between 1 and 109-2. In the wiring region 110-2, an N well 11 formed by expanding an N well provided in a P-type semiconductor substrate existing in a P channel region above and below the drawing is provided.
5 has a P-type diffusion region 117.
第３図は関連技術のものの等価回路図である。 FIG. 3 is an equivalent circuit diagram of the related art.
R1は電源配線の抵抗、R2はＮウェルの抵抗、R3は接地
配線の抵抗、R4は基板抵抗、C1はＰ拡散層117とＮウェ
ル115間のPN接合容量、C2はＮ型拡散層113とＰ型半導体
基板118間のPN接合容量、ａは出力バッファ等の電流源
を表わしている。R1 is the resistance of the power supply wiring, R2 is the resistance of the N well, R3 is the resistance of the ground wiring, R4 is the substrate resistance, C1 is the PN junction capacitance between the P diffusion layer 117 and the N well 115, and C2 is the resistance of the N type diffusion layer 113. A PN junction capacitance between the P-type semiconductor substrates 118, a represents a current source such as an output buffer.
電源配線とＰ型半導体基板との間、接地配線とＮウェ
ルとの間にそれぞれ大きな容量が入るので、半導体チッ
プ内における電源電位や接地電位の急激な変動は押えら
れノイズが低減する。Since a large capacitance is inserted between the power supply wiring and the P-type semiconductor substrate and between the ground wiring and the N well, rapid fluctuations in the power supply potential and the ground potential in the semiconductor chip are suppressed, and noise is reduced.
Ｐウェル方式の場合は、両側にＮチャネル領域がくる
配線領域には第１図（ｃ）でＰとＮを入れかえ、電源配
線を接地配線と読みかえた図で示されるものを設ければ
よく、両側にＰチャネル領域がくる配線領域には第１図
（ｂ）でＮとＰを入れかえ、接地配線を電源配線と読み
かえた図で示されるものを設ければよいのである。In the case of the P-well system, in the wiring region where the N-channel region is provided on both sides, P and N in FIG. 1 (c) are interchanged, and the power supply wiring may be replaced with the ground wiring as shown in FIG. In the wiring region where the P channel region comes on both sides, N and P are interchanged in FIG. 1 (b), and what is shown in the figure in which the ground wiring is replaced with the power supply wiring may be provided.
第２図（ａ）及び（ｂ）はそれぞれ本発明の実施例を
説明するための図で、第２図（ａ）は接地配線で挟まれ
た配線領域のパターン図、第２図（ｂ）は電源配線で挟
まれた配線領域のパターン図である。第２図（ａ）では
接地配線209−1,209−２で挟まれた配線領域211−１の
中心に電源配線207を一本通過させ、Ｐ型半導体基板内
に設けたＮ型拡散層213に接続している。又は第２図
（ｂ）では、電源配線207−1,207−２で挟まれた配線領
域211−２の中心に接地配線209−10を一本通過させ、Ｐ
型半導体基板内のＮウエル215内に設けたＰ型拡散層217
に接続している。なお、207−10,209−10は第２の金属
配線（第１図（ａ）の112−２に相当する横方向の配線
をとるもの）と同じ層次の金属配線を用いる。2 (a) and 2 (b) are diagrams for explaining an embodiment of the present invention. FIG. 2 (a) is a pattern diagram of a wiring region sandwiched between ground wirings, and FIG. 2 (b). FIG. 4 is a pattern diagram of a wiring region sandwiched between power supply wirings. In FIG. 2 (a), one power supply wiring 207 passes through the center of the wiring area 211-1 sandwiched between the ground wirings 209-1 and 209-2, and is connected to the N-type diffusion layer 213 provided in the P-type semiconductor substrate. doing. Alternatively, in FIG. 2B, one ground wiring 209-10 is passed through the center of the wiring area 211-2 sandwiched between the power supply wirings 207-1 and 207-2, and P
Diffusion layer 217 provided in N well 215 in the semiconductor substrate
Connected to Note that 207-10 and 209-10 use the same metal wiring of the same layer as the second metal wiring (which takes a horizontal wiring corresponding to 112-2 in FIG. 1A).
第４図は本発明の実施例の等価回路図である。 FIG. 4 is an equivalent circuit diagram of the embodiment of the present invention.
この実施例では配線領域内に電源配線又は接地配線を
一本通過させるため、配線領域の面積が増大するが、関
連技術のものが、基板,Nウェル抵抗と電源，グランド配
線抵抗を利用した等価電位間で容量接合であるのに対
し、本実施例では電源接地間での容量接合の為電源接地
間のノイズ低減にはより大きな効果をもつものである。In this embodiment, since one power supply wiring or ground wiring passes through the wiring area, the area of the wiring area is increased. However, the related art is equivalent to the substrate, the N-well resistance and the power supply and ground wiring resistance. In the present embodiment, the capacitance junction between the power supply and the ground is more effective in reducing the noise between the power supply and the ground than the capacitance junction between the potentials.
Ｐウェル方式の場合には、両側にＮチャネル領域がく
る配線領域には第２図（ｂ）でＰとＮを入れかえ、電源
配線と接地配線を入れかえた図で示されるものを設けれ
ばよく、両側にＰチャネル領域がくる配線領域には第２
図（ａ）でＮとＰを入れかえ、電源配線と接地配線を入
れかえた図で示されるものを設ければよいのである。In the case of the P-well system, in the wiring region where the N channel region comes on both sides, P and N are interchanged in FIG. 2 (b), and the wiring shown in FIG. , The wiring region having a P-channel region on both sides
What is necessary is to provide what is shown in the figure which changed N and P in Drawing (a), and changed a power supply wiring and a ground wiring.
以上説明したように本発明は半導体チップ内の金属配
線で専有される配線領域内に電源配線又は接地配線に接
続された拡散層を設け、その拡散層と半導体基板又はウ
ェルトの間で形成されるPN接合容量を半導体チップ内部
の電源配線と接地配間に接続することにより、大規模，
高速，多ピン化等による電源配線や接地配線に発生する
ノイズの影響を低減できる効果がある。なお、このよう
な容量を設けてもチップサイズの増大は伴なわない。As described above, the present invention provides a diffusion layer connected to a power supply wiring or a ground wiring in a wiring area occupied by a metal wiring in a semiconductor chip, and is formed between the diffusion layer and a semiconductor substrate or a welt. By connecting the PN junction capacitance between the power supply wiring inside the semiconductor chip and the ground connection, large-scale,
This has the effect of reducing the effect of noise generated on the power supply wiring and the ground wiring due to high-speed, multi-pin, etc. Note that providing such a capacity does not increase the chip size.
第１図（ａ）は本発明の関連技術のものを示すレイアウ
ト図、第１図（ｂ）は関連技術のものにおけるＮチャネ
ル領域で挟まれた配線領域の拡散層のレイアウト図、第
１図（ｃ）は同じくＰチャネル領域で挟まれた配線領域
の拡散層のレイアウト図、第２図（ａ）は本発明の実施
例におけるＮチャネル領域で挟まれた配線領域の拡散層
のレイアウト図、第２図（ｂ）は本発明の実施例におけ
るＰチャネル領域で挟まれた配線領域の拡散層のレイア
ウト図、第３図及び第４図はそれぞれ関連技術のもの及
び本発明の実施例の等価回路図、第５図及び第６図はそ
れぞれ従来例のチップ外部領域と内部領域を示すレイア
ウト図及び電源配線と接地配線のレイアウト図である。 １……半導体チップ、２……外部領域、３……内部領
域、４……電源ピン、５……接地ピン、６……外部電源
配線、７……内部電源配線、107−1,107−2,207−1,207
−2,207−10……（内部）電源配線、８……外部接地配
線、９……内部接地配線、109−1,109−2,209−1,209−
2,209−10……（内部）接地配線、110−1,110−2,210−
1,210−２……配線領域、111−1,111−2,111−３……素
子領域、111−1n,111−2n……Ｎチャネル領域、111−1
p,111−2p,111−3p……Ｐチャネル領域、112−１……第
１の金属配線、112−２……第２の金属配線、113,213…
…Ｎ型拡散層、114,214……コンタクト穴、115,215……
Ｎウェル、116,216……Ｎ型拡散層、117,217……Ｐ型拡
散層、118……Ｐ型半導体基板。1 (a) is a layout diagram showing a related art of the present invention, FIG. 1 (b) is a layout diagram of a diffusion layer in a wiring region sandwiched between N channel regions in the related art, FIG. FIG. 2C is a layout diagram of a diffusion layer of a wiring region sandwiched by P channel regions, and FIG. 2A is a layout diagram of a diffusion layer of a wiring region sandwiched by N channel regions according to the embodiment of the present invention; FIG. 2 (b) is a layout diagram of a diffusion layer in a wiring region sandwiched between P-channel regions in the embodiment of the present invention, and FIGS. 3 and 4 are equivalents of the related art and the embodiment of the present invention, respectively. 5 and 6 are a layout diagram showing a chip external region and an internal region, and a layout diagram of a power supply line and a ground line, respectively, of a conventional example. 1 ... semiconductor chip, 2 ... external area, 3 ... internal area, 4 ... power supply pin, 5 ... ground pin, 6 ... external power supply wiring, 7 ... internal power supply wiring, 107-1, 107-2, 207- 1,207
-2,207-10 ... (internal) power supply wiring, 8 ... external ground wiring, 9 ... internal ground wiring, 109-1,109-2,209-1,209-
2,209-10 ... (internal) ground wiring, 110-1,110-2,210-
1,210-2: wiring area, 111-1, 111-2, 111-3: element area, 111-1n, 111-2n: N channel area, 111-1
p, 111-2p, 111-3p... P channel region, 112-1... first metal wiring, 112-2... second metal wiring, 113,213.
... N-type diffusion layer, 114,214 ... Contact hole, 115,215 ...
N-well, 116, 216: N-type diffusion layer, 117, 217: P-type diffusion layer, 118: P-type semiconductor substrate.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０１Ｌ 27/092 ──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. 6 Identification code FI H01L 27/092
Claims (1)
に配置してなるCMOS集積回路において、電源配線（又は
接地配線）に接続されたＮ（又はＰ）型拡散層であって
Ｐ（又はＮ）型半導体基板に選択的に設けられたもの又
は接地配線（又は電源配線）に接続されたＰ（又はＮ）
型拡散層であってＰ（又はＮ）型半導体基板に設けられ
たＮ（又はＰ）ウェルに選択的に設けられたものを前記
配線領域に備えていることを特徴とするCMOS集積回路。In a CMOS integrated circuit in which element regions and wiring regions are alternately arranged on a semiconductor chip, an N (or P) type diffusion layer connected to a power supply wiring (or a ground wiring) and a P (or P) diffusion layer is provided. N (P) (or N) selectively provided on a type semiconductor substrate or connected to a ground wiring (or power supply wiring)
A CMOS integrated circuit, characterized in that the wiring region includes a type diffusion layer selectively provided in an N (or P) well provided in a P (or N) semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63308202A JP2841398B2 (en) | 1988-12-05 | 1988-12-05 | CMOS integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63308202A JP2841398B2 (en) | 1988-12-05 | 1988-12-05 | CMOS integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02153562A JPH02153562A (en) | 1990-06-13 |
| JP2841398B2 true JP2841398B2 (en) | 1998-12-24 |
Family
ID=17978148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63308202A Expired - Lifetime JP2841398B2 (en) | 1988-12-05 | 1988-12-05 | CMOS integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2841398B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02231756A (en) * | 1989-03-03 | 1990-09-13 | Nec Corp | Semiconductor device |
| JPH0548020A (en) * | 1991-08-12 | 1993-02-26 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
| JPH0870050A (en) * | 1994-08-29 | 1996-03-12 | Mitsubishi Electric Corp | Semiconductor integrated circuit device and its manufacture |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59225557A (en) * | 1983-06-06 | 1984-12-18 | Toshiba Corp | Complementary mos integrated circuit device |
-
1988
- 1988-12-05 JP JP63308202A patent/JP2841398B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02153562A (en) | 1990-06-13 |
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