JP3009413B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and is particularly effective for use in, for example, a bipolar CMOS (hereinafter abbreviated as BiCMOS) gate array integrated circuit. It is about technology.

[Conventional technology]

There is a Bi-CMOS gate array integrated circuit provided with a logic block including a plurality of cell columns composed of a CMOS (complementary MOS) circuit or a Bi-CMOS circuit.

In these Bi / CMOS gate array integrated circuits, with the development of high-speed integration and miniaturization technologies, the breakdown voltage of circuit elements has become a problem. There have been proposals to pursue by optimizing the voltage according to its characteristics.
In this case, it is necessary to unify the power supply voltage in order to maintain compatibility with the conventional product. For this reason, for example, a + 5V power supply voltage is converted to an + 3.3V internal power supply voltage and converted into a low withstand voltage internal circuit. A step-down circuit for supplying is provided.

For a Bi-CMOS gate array integrated circuit having a step-down circuit, see, for example, “ISSC: International Solid-State C
ircuits Conference) Digest Of Technical Paprs SESSION 1
3 "pages 176 to 177.

[Problems to be solved by the invention]

In a conventional Bi / COMS gate array integrated circuit or the like as described above, the step-down circuit is provided as a common circuit, and is arranged, for example, in a peripheral region of a semiconductor substrate. As is well known, a built-in type step-down circuit has a large output impedance, so that a power supply nozzle is generated at the time of simultaneous operation of internal circuits and the like, and the circuit operation becomes unstable. In order to cope with this, if the output impedance of the step-down circuit is reduced or the step-down circuit is arranged to be dispersed in the internal region of the semiconductor substrate, the required area of the layout of the step-down circuit is significantly increased. The degree of integration decreases. Also, when a plurality of power supply voltages are to be supplied directly from the outside, the integration of the gate array integrated circuit is reduced due to the arrangement of the power supply voltage supply lines.

SUMMARY OF THE INVENTION An object of the present invention is to provide a Bi-CMOS gate array integrated circuit or the like in which a step-down circuit and the like are distributed without lowering the degree of integration. Another object of the present invention is to suppress the level fluctuation of an internal power supply voltage formed by a step-down circuit or the like, to stabilize the operation of a Bi-CMOS gate array integrated circuit or the like, and to enhance its reliability.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
Unify the power supply voltage externally supplied to the Bi-CMOS gate array integrated circuit, etc., and provide a plurality of step-down circuits at substantial power distribution points, that is, for each cell row, It is formed adjacent to and below the power supply voltage supply main line and the ground potential supply main line. Further, a reference potential generating circuit for forming a reference potential required for the step-down circuit is provided in common to all the step-down circuits, and a reference potential supply line for transmitting the reference potential is provided between the power supply voltage supply main line and the ground potential supply main line. Form.

(Operation)

According to the above-described means, a plurality of step-down circuits can be provided in a Bi / CMOS gate array integrated circuit or the like without lowering the degree of integration, the level of the internal power supply voltage can be unified, and the power supply nozzles can be suppressed by suppressing the power supply nozzles. Level can be stabilized.
As a result, the operation can be stabilized and the reliability thereof can be improved while promoting the high integration of the Bi-CMOS game array integrated circuit and the like.

〔Example〕

FIG. 1 is a substrate layout diagram of an embodiment of a Bi-CMOS gate array integrated circuit to which the present invention is applied.
FIGS. 2 to 4 show layout diagrams of one embodiment of the logic blocks LB1 to LB3 of the Bi.CMOS gate array integrated circuit of FIG. 1, respectively. FIG. 5 is a circuit diagram of one embodiment of the step-down circuit VD included in the logic block LB1 of FIG. 2, and FIG. 6 is a diagram of one embodiment of the step-down circuit VD of FIG. A cross section is shown. With reference to these figures, an outline of the configuration and operation of the Bi.CMOS gate array integrated circuit of this embodiment and its features will be described. The circuit elements shown in FIG. 5 and the circuit elements constituting each block shown in FIGS. 1 to 4 are not particularly limited by a known semiconductor integrated circuit manufacturing technique. Formed on the semiconductor substrate. In FIG. 5, the MOSFET with an arrow added to its channel (back gate) portion is a P-channel type, and is distinguished from an N-channel MOSFET without an arrow.

In FIG. 1, the Bi-CMOS gate array integrated circuit of this embodiment is not particularly limited, but has an arithmetic logic unit ALU formed as a macro cell on a semiconductor substrate SUB.
And a multiplication circuit MULT and a register file REG. One read only memory ROM and three random access memories RAM1 to RAM3 are provided.

The Bi-CMOS gate array integrated circuit further includes three logic blocks LB1 to BL3. These logical blocks are
As will be described later, each includes a predetermined number of cell rows, and each cell row includes a number of standard unit cells having a predetermined circuit configuration. Although the logical blocks BL1 to LB3 are not particularly limited,
Together with the arithmetic logic unit ALU, the multiplying circuit MULT and the like, and input / output buffers IO1 and IO2 and the like described later, one digital device such as a microprocessor is constituted.

In this embodiment, the power supply voltage supply bus SBV and the ground potential supply bus SBG are arranged in the shape of an eye around the plurality of macro cells and the logic blocks, although not particularly limited. A region surrounded by the power supply voltage supply bus and the ground potential supply bus is referred to as an internal region IZ of the semiconductor substrate, and the outside thereof is referred to as a peripheral region PZ. Internal area
IZ becomes an electric protection area by being surrounded by the power supply voltage supply bus SBV and the ground potential supply bus SBG having a relatively wide width.

Although not particularly limited, the power supply voltage supply bus SBV is coupled to a power supply voltage supply pad VCC on the upper side of the semiconductor substrate SUB, and the ground potential supply bus SBG is coupled to the ground potential supply pad GND on the lower side. The power supply voltage supply pad VCC is supplied with a power supply voltage Vcc from an external power supply via a predetermined external terminal (not shown) of the package, and the ground potential supply pad GND is similarly supplied via a predetermined external terminal (not shown). It is coupled to the ground potential point. Here, the power supply voltage Vcc is not particularly limited, but is a positive power supply voltage such as +5.0 V. In other words, Bi ·
As will be described later, a CMOS gate array integrated circuit requires a complicated internal power supply voltage, but its operation power supply voltage is unified to only the power supply voltage Vcc.

The power supply voltage supply point and the ground potential supply point of each macro cell and logic block are connected to the corresponding power supply mains SV.
And a ground potential supply bus SB via a corresponding ground potential supply trunk line SG.
It is connected to the proximity point of G. In this embodiment, Bi · CMO
Although not particularly limited, the semiconductor substrate SUB on which the S gate array integrated circuit is formed is provided with three metal wiring layers AL1 to AL3 made of aluminum or an alloy thereof, and includes the power supply voltage supply bus SBV and the ground potential supply bus. The supply trunks such as the SBG and the supply voltage supply trunk SV and the ground potential supply trunk SG have the uppermost aluminum wiring layer AL3 except for the intersection.
Formed by

The Bi-CMOS gate array integrated circuit of this embodiment is not particularly limited, but further includes a peripheral region PZ of the semiconductor substrate SUB.
, Two input / output buffers IO1 and IO2 and a reference potential generating circuit VRG. Of these, the input / output buffers IO1 and IO2 are not particularly limited, but are constituted by a plurality of reference cells dedicated to input or output, and function as an interface circuit with an external device. I / O buffer IO
A plurality of pads PAD used for data input / output and the like are provided outside 1 and IO2.

On the other hand, although not particularly limited, the reference potential generating circuit VRG is formed as one macro cell, and the power supply voltage Vc
A predetermined reference potential Vr is formed based on c. This reference potential V
r is a logic block via a power supply voltage supply bus SBV and a ground potential supply bus SBG or a reference potential supply line SR disposed between the power supply voltage supply trunk SV and the ground potential supply trunk SG.
It is supplied to LB1 to LB3. As a result, the reference potential supply line SR
Is shielded by the power supply voltage supply bus SBV and the ground potential supply bus SBG or the power supply voltage supply trunk SV and the ground potential supply trunk SG, thereby stabilizing the level of the reference potential Vr.

The logic block LB1 includes, but is not limited to, ten cell columns CG1 to CG10S, as shown in FIG. 2, and these cell columns are composed of a large number of unit cells in a CMOS circuit form.
Including CU. The breakdown voltage of each unit cell is reduced by the particles of the element, and the internal power supply voltage Vcd having a relatively small absolute value, such as +3.3 V, is used as the operation power supply. Therefore, in the Bi-CMOS gate array integrated circuit of this embodiment,
Although not particularly limited, two step-down converters that form the internal power supply voltage Vcd based on the power supply voltage Vcc corresponding to the substantial power distribution points of the power supply voltage supply main line SV and the ground potential supply main line SG, that is, each cell row A circuit VD (voltage conversion circuit) is provided.

Here, although not particularly limited, each of the step-down circuits VD basically has a pair of N-channel MOSFETs Q11 and Q12 in a differential form as shown in FIG. MOSF
P is between the drains of ETQ11 and Q12 and the power supply voltage Vcc.
Channel MOSFETs Q1 and Q2 are provided, respectively. MOSF
The gate of ETQ2 is commonly coupled to its drain, and
Coupled to the gate of MOSFET Q1. This allows the MOSFET Q1
And Q2 are in current mirror form and act as active loads on MOSFETs Q11 and Q12.

MOSFETs Q11 and Q12 have a common coupled source and ground potential
N-channel MOS between Vss
FETQ13 is provided. This MOSFET Q13 is always turned on by its gate being coupled to the power supply voltage Vcc,
Thereby, it functions as a current source for supplying a predetermined operating current to the differential MOSFETs Q11 and Q12.

The reference potential Vr is supplied to the gate of the MOSFET Q11 from the reference potential generation circuit VRG via the reference potential supply line SR. The reference potential Vr is not particularly limited, but is a relatively stable level such as + 3.3V.

On the other hand, the commonly coupled drains of MOSFETs Q1 and Q11 are further coupled to the gate of P-channel MOSFET Q3. The source of MOSFET Q3 is coupled to power supply voltage Vcc, and the drain is coupled to the gate of MOSFET Q12 and to internal power supply voltage supply point Vcd.
A power supply smoothing capacitor C1 is provided between the internal power supply voltage supply point Vcd and the ground potential Vss. This allows the MOSFET
Q3 substantially acts as a current supply MOSFET Q for supplying the internal power supply voltage Vcd to the corresponding cell row, and as a voltage control MOSFET Q for controlling the level of the internal power supply voltage Vcd by changing its gate voltage. Works.

For these reasons, when the power supply voltage Vcc is supplied, the differential MOSFETs Q11 and Q12 function as differential amplifier circuits having the MOSFETs Q1 and Q2 as active loads. At this time, the differential amplifier circuit has its non-inverting input terminal, ie, MOSF
The level of the internal power supply voltage Vcd supplied to the gate of the ETQ12 is compared with its inverting input terminal, that is, the reference potential Vr supplied to the gate of the MOSFET Q11, and the level difference is enlarged, and the non-inverting output terminals, that is, the MOSFETs Q1 and Q11 To the gate of MOSFET Q3.
As a result, the level of the internal power supply voltage Vcd is controlled and converged to the reference potential Vr, that is, +3.3 V.

That is, when the level of internal power supply voltage Vcd rises and becomes higher than reference potential Vr, the conductance of MOSFET Q12 increases. For this reason, the gate voltages of the MOSFETs Q1 and Q2 decrease, and the conductance of the MOSFET Q1 increases. Therefore, the gate voltage of MOSFET Q3 increases and its conductance decreases, and as a result, the level of internal power supply voltage Vcd decreases. On the other hand, the internal power supply voltage Vcd
When the level of the power supply drops below the reference potential Vr, the MOSFET
The conductance of Q21 is small. For this reason, MOSFE
The gate voltages of TQ and Q2 increase, and the conductance of MOSFET Q1 decreases. Therefore, the gate voltage of MOSFET Q3 decreases, and its conductance increases, so that the level of internal power supply voltage Vcd effectively increases. As a result, the level of the internal power supply voltage Vcd is converged to the reference potential Vr, that is, +3.3 V, and is stabilized.

In FIG. 2, two step-down circuits VD provided corresponding to each cell column are formed below the power supply voltage supply trunk SV and the ground potential supply trunk SG that vertically pass through both ends of the logic block LB1. That is, as described above, on the semiconductor substrate SUB on which the Bi-CMOS gate array integrated circuit is formed,
Three aluminum wiring layers AL1 to AL3 are prepared, and the power supply voltage supply trunk SV and the ground potential supply trunk SG in the X direction are formed in parallel using the aluminum wiring layer AL3, and the aluminum wiring layer AL2 is formed in the Y direction. And are formed in parallel.
A reference potential supply line SR for transmitting the reference potential Vr is formed between the power supply voltage supply trunk SV and the ground potential supply trunk SG. In this embodiment, as shown in FIG. 6, each circuit element of the step-down circuit VD is directly under the power supply voltage supply trunk SV and the ground potential supply trunk SG formed using the aluminum wiring layer AL2, that is, the semiconductor substrate.
The diffusion layer L formed on the SUB element formation layer SE is the gate layer G.
And so on. On the aluminum wiring layer AL1 thereabove, for example, inter-element connection wirings marked with o in FIG. 5 are formed. The internal power supply voltage Vcd and the ground potential Vss formed by the step-down circuit VD are connected to the internal power supply voltage supply line S formed by the aluminum wiring layer AL1.
It is supplied to a plurality of unit cells CU constituting each cell column via the CD and the ground potential supply line SCG.

In other words, in the Bi-CMOS gate array integrated circuit of this embodiment, the configuration of the step-down circuit VD is relatively simple, and the element coupling wiring is realized by only one aluminum wiring layer AL1. Therefore, the power supply voltage supply trunk line SV and the ground potential supply trunk line SG which have been regarded as invalid areas in the conventional Bi-CMOS gate array
Without using the effective area of the OS gate array integrated circuit,
This can be arranged. As described above, the voltage step-down circuits VD, the power supply voltage supply trunk SV, and the ground potential supply supply trunk SG are provided corresponding to substantial power distribution points, and are arranged close to the corresponding cell columns. However, Bi of this embodiment
In a CMOS gate array integrated circuit, a step-down circuit VD having a relatively large output impedance is provided in close proximity to each cell row without lowering the degree of integration. As a result, the power supply nozzle due to the fluctuation of the operating current is suppressed, and the operation of the Bi-CMOS gate array integrated circuit is stabilized.

Next, the logical block LB2 includes, but is not limited to, six cell columns CG1 to CG6 as shown in FIG.
Although not particularly limited, each cell column includes a number of unit cells CU made of CMOS and a number of unit cells CBU formed above and below these unit cells CU and formed of bipolar transistors.
And Although not particularly limited, the unit cells CU and CBU are functionally coupled via a not-shown inter-element coupling line to form a Bi-CMOS type logic gate circuit.

Although the logical block BL2 is not particularly limited,
A plurality of step-down circuits provided two each corresponding to each cell column
Equipped with VD. Although these step-down circuits are not particularly limited, they have the same circuit configuration as the step-down circuit VD included in the logic block LB1, and have the internal power supply voltage Vcc based on the power supply voltage Vcc.
Form cd. Each step-down circuit VD is connected to a logic block LB.
Power supply voltage supply trunk line S arranged vertically through both sides of 2
The V and ground potential supply trunks SG are arranged in close proximity to substantial power distribution points and are formed below these supply trunks.
As a result, effects similar to those of the above-described logic block LB1 can be obtained with respect to high integration and stable operation of the Bi-CMOS gate array integrated circuit.

By the way, the unit cell CBU of the bipolar circuit type provided in the logic block LB2 requires a power supply voltage Vcc of +5.0 V as its operation power supply, although not particularly limited.
Therefore, in the Bi-CMOS gate array integrated circuit of this embodiment, the substantial input node of the step-down circuit VD, that is, the substantial power distribution point of the power supply voltage supply main line SV and the power supply voltage supply point of each cell column Another power supply voltage supply line SCV is provided therebetween, and the power supply voltage Vcc is supplied to each unit cell CBU via this. In other words, although this Bi.CMOS gate array integrated circuit requires a plurality of internal power supply voltages, only one kind of power supply voltage supply main line is routed inside the semiconductor substrate SUB. By arranging the branch node of the power supply voltage Vcc for the cell column and the output node of the step-down circuit VD close to each other, the level difference between the power supply voltages is reduced. As a result, the integration of the Bi-CMOS gate array integrated circuit is further promoted, and the operation thereof is further stabilized.

On the other hand, the logical block LB3 includes, but is not limited to, five cell columns CG1 to CG5 as shown in FIG.
Each cell row includes a number of unit cells CU made of CMOS and a number of unit cells CBU formed above and below these unit cells CU and made of bipolar transistors. Unit cell CU
The CBU and the CBU are functionally coupled via a not-shown inter-element coupling wire, and constitute a Bi-CMOS type logic gate circuit.

In the logic block BL3, the unit cell CBU formed below the unit cells CU of the cell columns CG1 to CG5 requires an internal power supply voltage Vcs of, for example, +2.5 V, although not particularly limited. For this reason, two logic blocks LB3 are further provided for each cell column, and a plurality of step-down circuits VD1 that form the internal power supply voltage Vcd based on the power supply voltage Vcc are similarly provided in each cell column. A plurality of step-down circuits V correspondingly provided two each to form the internal power supply voltage Vcs based on the power supply voltage Vcc
D2. Among them, the step-down circuit DV1 is not particularly limited, but the step-down circuit VD included in the logic block LB1 is not particularly limited.
And the step-down circuit VD2 has a circuit configuration basically following the step-down circuit VD. Step-down circuit VD
1 and VD2 are a power supply voltage supply main line SV and a ground potential supply supply line SG, which are disposed vertically through both sides of the logic block LB3.
Are disposed in close proximity to the respective substantial power distribution points, and are formed thereunder. Then, the internal power supply voltage Vcs formed by the step-down circuit VD2 is supplied to a plurality of unit cells CBU forming a corresponding cell column via the internal power supply voltage supply line SCS. As a result, the logic block LB3 is
Regarding high integration and stable operation of the gate array integrated circuit, the same effect as that of the above-described logic block LB1 can be obtained, and the same effect as that of the above-described logic block LB2 can be obtained in terms of unifying the power supply voltage. be able to.

As described above, the Bi-CMOS gate array integrated circuit according to this embodiment includes the logic blocks LB1 to LB1 including a plurality of cell columns in addition to the arithmetic logic unit ALU, the multiplication circuit MULT, and the microcells such as the random access memory RAM. Equipped with LB3. A part of the cell rows constituting these logic blocks is constituted by a CMOS circuit which has been miniaturized, and the internal power supply voltage Vcd having a small absolute value is used as an operation power supply. The other part is composed of Bi-CMOS circuit,
Requires Vcc or internal power supply voltage Vcs. Bi of this embodiment
The power supply voltage externally supplied to the CMOS gate array integrated circuit is unified to the power supply voltage Vcc in order to maintain compatibility with the conventional BiCMOS gate array integrated circuit. A step-down circuit VDC or VD1 and VD2 for forming the internal power supply voltages Vcd and Vcs is built therein. In this embodiment, a plurality of step-down circuits are provided corresponding to the substantial power distribution points of the power supply voltage supply main line and the ground potential supply main line, that is, each cell row. The main line and the ground potential supply main line are formed below the aluminum wiring layer AL2. The reference potential Vr required for each step-down circuit is formed by a reference potential generation circuit VRG provided commonly to all step-down circuits, and is arranged to be shielded between the power supply voltage supply main line and the ground potential supply main line. The voltage is transmitted to each step-down circuit via the reference potential supply line SR. As a result, in the Bi-CMOS gate array integrated circuit of this embodiment, a plurality of step-down circuits are provided, and these step-down circuits are substantially connected to the power supply voltage supply main line and the ground potential supply main line without lowering the integration degree. Power distribution points. As a result, while promoting the integration of Bi-CMOS gate array integrated circuits, the level fluctuation of each internal power supply voltage is suppressed, and the power supply noise accompanying the fluctuation of the operating current is suppressed.
The operation of the CMOS gate array integrated circuit can be stabilized.

As shown in the above embodiment, the present invention is
The following effects can be obtained by applying the present invention to a semiconductor integrated circuit device such as an OS gate array integrated circuit. (1) The power supply voltage of a Bi / CMOS gate array integrated circuit or the like is unified and step-down is performed. By providing a plurality of circuits corresponding to a substantial power distribution point, that is, each cell row, and forming each circuit in the vicinity of the corresponding cell row and below the power supply voltage supply main line and the ground potential supply main line, Bi-CMOS The advantage is that a plurality of step-down circuits can be provided without reducing the degree of integration of the gate array integrated circuit and the like.

(2) According to the above item (1), an effect is obtained that the level fluctuation of the internal power supply voltage formed by the step-down circuit can be suppressed, and the power supply noise accompanying the fluctuation of the operating current can be suppressed.

(3) In the above items (1) and (2), the reference potential generating circuit for forming the reference potential is provided in common to all the step-down circuits, and the reference potential supply line for transmitting the reference potential is provided by the power supply voltage supply main line. In addition, by forming the internal power supply voltage between the ground potential supply main lines and in the same layer, the level of the internal power supply voltage formed by the step-down circuit can be unified and stabilized.

(4) According to the above items (1) to (3), the operation can be stabilized and the reliability thereof can be improved while promoting the high integration of the Bi.CMOS gate array integrated circuit and the like. can get.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in FIG. 1, the number and combination of macro cells and logic blocks mounted on a Bi-CMOS gate array integrated circuit are arbitrary. Further, the arrangement method and the direction of the power supply voltage supply main line and the ground potential supply main line including the power supply voltage supply bus and the ground potential supply bus are not limited by this embodiment.
Another reference potential generating circuit VRG may be provided, for example, on the lower side of the peripheral region PZ. In FIG. 2 to FIG. 4, the step-down circuits VD and VD1 and VD2 may be provided on only one side of the corresponding cell row. Further, these step-down circuits may be arranged below the power supply voltage supply bus SBV and the ground potential supply bus SBG, or may correspond to macro cells such as the arithmetic logic unit ALU and the random access memory RAM as required. It may be provided. The configuration and arrangement method of each logic block and each cell column are arbitrary. In FIG. 5, various embodiments can be considered for the specific circuit configuration of the step-down circuit VD, and the layout method of the element-to-element coupling wiring is also arbitrary. In FIG. 6, the metal wiring layer is not required to be formed of aluminum or an alloy thereof. The number of aluminum wiring layers is arbitrary, and the use of each aluminum wiring layer is also arbitrary.

In the above description, the case where the invention made by the present inventor is applied to a Bi-CMOS gate array integrated circuit, which is the field of application as the background, has been described. However, the present invention is not limited thereto. The present invention can also be applied to a dedicated logic integrated circuit device or the like having a basic configuration of a Bi / CMOS gate array integrated circuit or a Bi / CMOS composite circuit having only the same. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor integrated circuit device including at least a voltage conversion circuit for forming an internal power supply voltage.

[Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the power supply voltage of a Bi-CMOS gate array integrated circuit or the like is unified, and a plurality of step-down circuits are provided corresponding to a substantial power distribution point, that is, a cell row. It is formed below the trunk line and the ground potential supply trunk line. In addition, a reference potential generating circuit for forming a reference potential is provided commonly to all the step-down circuits, and a reference potential supply line for transmitting the reference potential is formed between the power supply voltage supply main line and the ground potential supply main line. Thus, a plurality of step-down circuits can be provided in a Bi-CMOS gate array integrated circuit or the like without lowering the degree of integration, and the level of the internal power supply voltage formed thereby can be unified and stabilized. As a result, Bi
-Stability of operation can be achieved and reliability can be improved while promoting high integration of CMOS gate array integrated circuits and the like.

[Brief description of the drawings]

FIG. 1 is a substrate layout diagram showing one embodiment of a Bi-CMOS gate array integrated circuit to which the present invention is applied. FIG. 2 is a first view of a first embodiment included in the Bi-CMOS gate array integrated circuit of FIG. FIG. 3 is a layout diagram showing one embodiment of a logic block, FIG. 3 is a layout diagram showing one embodiment of a second logic block included in the Bi-CMOS gate array integrated circuit of FIG. 1, and FIG. FIG. 1 is a layout diagram showing an embodiment of a third logic block included in the Bi-CMOS gate array integrated circuit of FIG. 1, and FIG. 5 is an embodiment of a step-down circuit included in the logic blocks of FIGS. FIG. 6 is a sectional view showing an embodiment of the step-down circuit of FIG. SUB ... Semiconductor substrate, IZ ... Substrate internal area, PZ ... Substrate peripheral area, VCC ... Pad for power supply voltage, GND ... Pad for ground potential supply, PAD ... Other pads, SBV ... Power supply voltage Supply bus, SBG: Ground potential supply bus, SV: Power supply voltage supply trunk line, SG: Ground potential supply trunk line, SR: Reference potential supply line, IO1, IO2: Input / output buffer, VRG: Reference potential generation Circuit, ALU… Arithmetic logic unit, MULT…
... Multiplication circuit, REG ... Register file, ROM ... Read only memory, RAM1 to RAM3 ... Random access memory, LB1 to LB3 ... Logic block. VD: Step-down circuit, CG1 to CG10: Cell column, CU: CMOS unit cell, CBU: Bipolar unit cell, SCV: Power supply voltage supply line, SCD, SCS ... Internal power supply voltage supply line, SCG ... Ground potential supply line. Q1-Q3 ... P-channel MOSFET, Q11-Q13 ... N-channel MOSFET, C1 ... Capacitor.

Claims (5)

(57) [Claims] 1. A power supply voltage supply trunk connected to an external terminal to which a power supply voltage is supplied and having a wide wiring width for transmitting the power supply voltage, and an external terminal to which a ground potential of a circuit is supplied. A ground potential supply trunk line having a wide wiring width for transmitting the ground potential of the circuit, and being arranged in parallel with the power supply voltage supply trunk line; branching from the power supply supply trunk line and the ground potential supply trunk line, The internal power supply line and the internal ground potential supply line, each of which transmits the stepped-down internal voltage and the ground potential, and has a wiring width narrower than the power supply voltage supply main line and the ground potential supply main line. A logic block connected to a power supply line and an internal ground potential supply line and having a desired circuit function; and a power supply voltage supply trunk line, a ground potential supply trunk line, and the internal power supply line. A branch portion between the voltage supply line and the internal ground potential supply line, which is constituted by a wiring layer and a semiconductor region below the power supply voltage supply main line and the ground potential supply main line, and reduces the power supply voltage to reduce the internal voltage. A step-down circuit formed and transmitted to the internal power supply voltage supply line. 2. The system according to claim 1, further comprising a reference voltage generation circuit, wherein the reference voltage generated by said reference voltage generation circuit is supplied along a reference voltage supply trunk line and a ground potential supply trunk line. The semiconductor integrated circuit device is transmitted to the step-down circuit via a line, and the step-down circuit forms a step-down voltage corresponding to the reference voltage. 3. The system according to claim 2, wherein the reference voltage supply line is a part except for a part extending from the reference voltage generation circuit to the power supply voltage supply trunk line and the ground potential supply trunk line.
A semiconductor integrated circuit device which is arranged so as to be sandwiched between the power supply voltage supply main line and the ground potential supply main line. 4. The power supply voltage supply main line and the ground potential supply main line are formed by an uppermost wiring layer, and a wiring layer for forming the step-down circuit is lower than the uppermost layer. A semiconductor integrated circuit device formed of a wiring layer. 5. The internal power supply according to claim 1, wherein the logic block comprises a plurality of cell columns, the power supply voltage supply trunk line and the ground potential supply trunk line extend along both ends of the cell column. A semiconductor integrated circuit device, wherein the line and the internal ground potential supply line are extended along the cell column, and the step-down circuit is arranged on both sides of the cell column.