JPH03188651A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the integration degree of a bipolar CMOS gate array IC, stabilize operation, and improve reliability, by separately arranging a plurality of voltage converting circuits in the inner region of a semiconductor substrate. CONSTITUTION:On a semiconductor substrate SUB, the following are arranged as microcells; an arithmetic logic operation unit ALU, a multiplying circuit MULT, a register file REG, one ROM, three RAMs 1-3, and three logic blocks LB1-3. These microcells constitute a digital device like a microprocessor together with I/O buffers, I02. On the periphery, a source voltage supply bus SBV and an earth potential supplying bus SBG are arranged as shown in the figure. The bus SBV is coupled with a source voltage supply pad VCC, on the upper side of the substrate SUB. The bus SBG is coupled with an earth potential supply pad GND on the lower side of the substrate SUB. In this manner, a power supply voltage VCC is applied to the pad VCC, and an earth potential is applied to the pad GND.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor integrated circuit devices, and is particularly effective when applied to, for example, bipolar CMO3 (hereinafter abbreviated as Bi-0MO8) gate array integrated circuits. It's about technology.

[Prior art] B equipped with a logic block including a plurality of cell strings consisting of a CMO3 (complementary MO3) circuit or a Bi-CMO8 circuit, etc.
1- There is a CMOS gate array integrated circuit.

In these B1-CMOS gate array integrated circuits,
With the progress of high integration and miniaturization technology, a decrease in the withstand voltage of circuit elements has become a problem, and on the other hand, the speed of devices approaching their physical limits can be increased by optimizing the power supply voltage according to their characteristics. There have been proposals to do so. In this case, it is essential to unify the power supply voltage in order to maintain compatibility with conventional products, and for this purpose, for example, the +5V power supply voltage is converted to +3.3V internal power supply voltage, and the low voltage internal circuit A step-down circuit is provided to supply the voltage.

For B1-CMOS gate array integrated circuits with step-down circuits, see, for example, "I.
Nis Nis Cii Cii (I 5sCC:Inter
national 5olid-3tate C1
Digest of Technical Babers
Technical Papers) 5ESS
ION 13 J, pages 176 to 177.

[Problem to be solved by the invention]

In the conventional B1-CMOS gate array integrated circuit as described above, a step-down circuit is provided as a common circuit, for example, in a peripheral area of a semiconductor substrate.As is well-known, a built-in step-down circuit is The output impedance is large, which causes power supply noise when internal circuits operate simultaneously, making circuit operation unstable. In order to deal with this, if an attempt is made to reduce the output impedance of the step-down circuit or to distribute the step-down circuit in the internal area of the semiconductor substrate, the required layout area of the step-down circuit increases significantly, making it difficult to use as a gate array integrated circuit. The degree of integration decreases. Further, when attempting to directly supply a plurality of power supply voltages from the outside, the degree of integration as a gate array integrated circuit is reduced due to the routing of power supply voltage supply lines.

An object of the present invention is to provide a B1-CMOS gate array integrated circuit, etc., in which step-down circuits and the like are arranged in a distributed manner without reducing the degree of integration.

Another object of the present invention is to stabilize the operation of a Bi-CMOS gate array integrated circuit and increase its reliability by suppressing level fluctuations in an internal power supply voltage formed by a step-down circuit and the like.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

(Means for Solving the Problems) A brief overview of typical inventions disclosed in this application is as follows.

That is, the power supply voltage supplied from the outside to the B1-CMOS gate array integrated circuit, etc. is unified, and a plurality of step-down circuits are provided corresponding to the actual power distribution points, that is, each cell column, and each step-down circuit is connected to the corresponding cell. It is formed close to the column and below the power supply voltage supply main line and the ground potential supply main line. In addition, a reference potential generation circuit that forms the reference potential necessary for the step-down circuit is provided in common for all step-down circuits, and a reference potential supply line that transmits the reference potential is connected between the power supply voltage supply main line and the ground potential supply main line. Form.

[For production]

According to the above means, it is possible to provide a plurality of step-down circuits in a B1-CMOS gate array integrated circuit, etc. without reducing the degree of integration, and to unify the level of the internal power supply voltage. Levels can be stabilized. As a result, it is possible to promote higher integration of Bi.CMOS gate array integrated circuits and the like, stabilize the operation, and improve the reliability.

〔Example〕

FIG. 1 shows a substrate layout diagram of an embodiment of a Bi-cMOS gate array integrated circuit to which the present invention is applied. In addition, in Figures 2 to 4, B1-C in Figure 1 is shown.
A layout diagram of one embodiment of logic blocks LBI to LB3 of a MOS gate array integrated circuit is shown, respectively.

Furthermore, FIG. 5 shows a circuit diagram of an embodiment of the step-down circuit VD included in the logic block LBI of FIG.
The figure shows a cross-sectional view of one embodiment of the step-down circuit VD of FIG. Based on these figures, B1- of this example
An overview of the configuration and operation of a CMOS gate array integrated circuit as well as its characteristics will be described. Note that each circuit element in FIG. 5 and the circuit elements constituting each block in FIGS. 1 to 4 are not particularly limited by known semiconductor integrated circuit manufacturing techniques, but may be made of single crystal silicon such as single crystal silicon. is formed on a semiconductor substrate. Further, in FIG. 5, the MOSFET whose channel (bank gate) portion is marked with an arrow is a P-channel type, and is shown to be distinguished from the N-channel MO3FET whose channel (bank gate) portion is not marked with an arrow.

In FIG. 1, the B1-CMOS gate array integrated circuit of this embodiment includes, but is not limited to, a semiconductor substrate SU
Arithmetic and logic operation Unison ALU formed as a macro cell on B, multiplication circuit MULT, and register file RE
G, and one read-only memory ROM and three
random access memories RAMI to RAM3.

The Bt-CMOS gate array integrated circuit further includes three logic blocks L, B1 to LB3.

These logic blocks each include a predetermined number of cell columns, and each cell column includes a large number of standard unit cells having a predetermined circuit configuration, as will be described later.
Although not particularly limited, the LB3 constitutes one digital device such as a microprocessor together with the arithmetic and logic operation unit ALU, the multiplication circuit MULT, etc., and the input/output cover sofa IOI and 102, which will be described later, etc., although not particularly limited thereto.

In this embodiment, a power supply voltage supply bus SBV and a ground potential supply bus SBG are arranged in an eye shape around the plurality of macro cells and logic blocks, although this is not particularly limited. The region surrounded by the power supply voltage supply bus and the ground potential supply bus is a so-called internal region (Z) of the semiconductor substrate, and the outside thereof is a peripheral region PZ.

Internal area ■Z is a relatively wide power supply voltage supply bus SB
By being surrounded by V and ground potential supply bus SBG,
Provides electrical protection area.

Although not particularly limited, the power supply voltage supply bus SBV has a power supply voltage supply pad VC on the upper side of the semiconductor substrate SUB.
The ground potential supply bus SBG is coupled to the ground potential supply pad GND at its lower side. A power supply voltage VCC is supplied to the power supply voltage supply pad VCC from an external power supply device through a predetermined external terminal (not shown) of the puff cage.
cc is supplied, and the ground potential supply band GND is similarly coupled to a ground potential point via a predetermined external terminal not shown. Here, the power supply voltage Vcc is a positive power supply voltage such as +S or OV, although it is not particularly limited. In other words, although the Bk-CMOS gate array integrated circuit of this embodiment requires a plurality of internal power supply voltages, as will be described later, its operating power supply voltage is the power supply voltage Vc.
It is unified only to c.

The power supply voltage supply point and ground potential supply point of each macro cell and logic block are connected to the corresponding power supply voltage supply main line S.
It is coupled to a nearby point of the power supply voltage supply bus SB■ via V, and to a nearby point of the ground potential supply bus SBG via a corresponding ground potential supply main line SG. In this embodiment, the semiconductor substrate sUB on which the B1-CMOS gate array integrated circuit is formed includes 3Wi metal wiring layers ALI to ALI made of aluminum or its alloy, although not particularly limited.
L3 is prepared, and the above-mentioned power supply voltage supply bus SB■, ground potential supply bus SBG, and tIi source voltage main line SV
The supply main lines such as the ground potential supply main line SG and the like are formed of the uppermost aluminum wiring layer AL3, except for the intersection portions.

The B 1-CMOS gate array integrated circuit of this embodiment further includes, although not particularly limited to, two exposed cover sofas 101 and 102 formed in the peripheral region PZ of the semiconductor substrate SUB and a reference potential generation circuit VRG. Among these, the input/output covers and the fibers 101 and 102 are constituted by a plurality of standard cells dedicated to input or output, although not particularly limited, and act as an interface circuit with an external device. On the outside of the input and output cover sofas 101 and 102,
A plurality of pads PAD are provided for data input/output and the like.

On the other hand, the reference potential generation circuit VRG is formed as one macrocell, although not particularly limited, and is formed at the power supply voltage Vc.
A predetermined reference potential Vr is formed based on c. This reference potential Vr is applied to logic blocks LBI to LB3 via a reference potential supply line SR arranged between a power supply voltage supply bus SBV and a ground potential supply bus SBG or between a power supply voltage supply main line SV and a ground potential supply main line SG. Supplied. As a result, the reference potential supply line SR is connected to the power supply voltage supply bus SBV and the ground potential supply bus SBG or the power supply voltage supply main line S
The level of the reference potential Vr is stabilized by the shielding effect of the V and ground potential supply main line SG.

Logic block LBI includes, but is not particularly limited to, 10 cell columns CG1 to CGIO, as illustrated in FIG. The withstand voltage of each unit cell, including
The internal power supply voltage Vcd, which has a relatively small absolute value, is used as the operating power supply. Therefore, the B1-CMOS of this example
In the gate array integrated circuit, although not particularly limited, the power supply voltage V
Two step-down circuits ii$VD (voltage conversion circuits) are provided, each forming an internal power supply voltage Vcd based on cc.

Here, each of the step-down circuits VD has a basic configuration of a pair of differential N-channel MO3FETs QI1 and Q12, as shown in FIG. 5, although this is not particularly limited. A P-channel MO3FET is connected between the drains of MOSFETs Q11 and QL2 and the power supply voltage Vcc.
QI and Q2 are provided respectively. MOSFETQ2
The gates of are commonly coupled to their drains and further connected to the MO
Coupled to the gate of 3FETQI. This allows M.O.
SFETQI and Q2 are in current mirror configuration and MO
Acts as an active load for 3FET QI 1 and Q12.

Although not particularly limited, between the commonly coupled sources of MO3FETQI 1 and Q12 and the ground potential Vss,
An N-channel MOSFET Q13 is provided. This M
The O3FET QI 3 is always turned on by having its gate coupled to the power supply voltage Vcc, thereby acting as a current source for supplying a predetermined operating current to the differential MO3FETs QII and Q12.

A reference potential Vr is supplied to the gate of the MO3FET QI l from the reference potential generation circuit VRG via a reference potential supply line SR. This reference potential ■r is set to a relatively stable level such as +3.3 V, although it is not particularly limited.

Meanwhile, the commonly coupled drains of MO3FETs QI and Qll are further coupled to the gate of P-channel MO3FET Q3. The source of this MO3FETQ3 is coupled to the power supply voltage Vcc, and its drain is connected to the MO5FETQ3.
It is coupled to the gate of FET QI 2 and also to the internal mW pressure supply point ■cd. A power supply smoothing capacitor C1 is provided between the internal power supply voltage supply point Vcd and the ground potential Vss. This allows MOS FET
Q3 substantially applies internal power supply voltage Vcd to the corresponding cell column.
It acts as a current supply ~105FET for supplying , and acts as a voltage control MO3FET that controls the level of internal power supply voltage Vcd by changing its gate voltage.

From these things, differential MO3FETQI 1 and Q1
2 is a MOS when the power supply voltage Vcc is supplied.
It functions as a differential amplifier circuit with FETQ1 and Q2 as active loads. At this time, the differential amplifier circuit compares the level of the internal power supply heavy voltage Vcd supplied to its non-inverting input terminal, that is, the gate of MO3FET QI 2, with the reference potential Vr, supplied to its inverting input terminal, that is, the gate of MO3FET QI 1. , the level difference is enlarged, and the non-inverting output terminals, that is, MO3FETQI and Ql
It is transmitted to the commonly coupled drain of MO3FETQ3. As a result, the level of the internal power supply voltage Vcd is controlled, and the reference potential ■", that is, +3.3
It is converged to v.

That is, when the level of internal power supply voltage Vcd rises and becomes higher than reference potential Vr, the conductance of MO3FETQ12 increases. For this reason, MO3FETQI
And the gate voltage of Q2 becomes small, MO3FETQI
conductance increases. Therefore, MO3F
The gate pressure of ETQ3 increases and its conductance decreases, so that the level of internal power supply voltage Vcd is lowered as a result. On the other hand, the level of internal @[heavy pressure Vcd decreases and becomes lower than the reference potential Vr (when MO3FETQ
12 conductance becomes small.

Therefore, the gate voltages of MO5FETQI and Q2 become high, and the conductance of MO3FETQI becomes small. Therefore, the gate pressure of MO3FETQ3 becomes low and its conductance becomes large, so that the level of internal power supply voltage Vcd becomes high as a result. This results in
The level of internal power supply voltage Vcd is converged to the base f$ potential Vr, that is, +3.3cm, and is stabilized.

In FIG. 2, two step-down circuits VD provided corresponding to each cell column are connected to a power supply voltage supply main line SV and a ground potential supply main line S that vertically pass through the WI end of the logic block LBI.
It is formed in the lower layer of G. That is, this B1-CMOS
As mentioned above, the semiconductor substrate SUB on which the gate array integrated circuit is formed has three layers of aluminum wiring WIALL.
~ AL3 is needed! The pressure supply main line SV and the ground potential supply main line SG in the X direction '1jLs' are formed in parallel using an aluminum wiring layer A L3, and in the Y direction are formed in parallel using an aluminum wiring layer AL2. . Also,
These power supply voltage supply main line SV and ground potential supply main line S
A reference potential supply line SR for transmitting the reference potential Vr is formed between the reference potential Vr and the reference potential Vr. In this embodiment, each circuit element of the step-down circuit VD is as illustrated in FIG.
It is constituted by a diffusion layer, a gate layer G, etc., which are formed directly under the power supply voltage supply main line SV and the ground potential supply main line SG, which are formed using the aluminum wiring layer AL2, that is, in the element formation layer SH of the semiconductor substrate SOB. In addition, the aluminum wiring JiiAL1 above it has, for example, 0 as shown in FIG.
Inter-element coupling wiring with marks is formed. The internal power supply voltage Vcd and ground potential Vss formed by the step-down circuit VD are supplied to the plurality of cells forming each cell column via the internal power supply voltage supply line SCD and the ground potential supply line SCG formed by the aluminum wiring layer ALL. are supplied to each unit cell CU.

That is, in the B1-CMOS gate array integrated circuit of this embodiment, the configuration of the step-down circuit VD is relatively simple, and its inter-element coupling wiring is realized by only one aluminum wiring layer ALL. For this reason, the conventional B1-CMO
To place this in the layer below the power supply voltage supply main line SV and the ground potential supply main line SG, which have been considered ineffective areas in S gate array integrated circuits, etc., without using the effective area of the B i -CMOS gate array integrated circuit. I can do it. As described above, each step-down circuit VD is provided corresponding to a substantial power distribution point of the power supply voltage supply main line SV and the ground potential supply main line SC, and is arranged close to the corresponding cell column. However, in the B1-CMOS gate array integrated circuit of this embodiment, the step-down circuit VD with a relatively large output impedance can be integrated without reducing its degree of integration.
are provided adjacent to and corresponding to each cell column. This suppresses power supply noise caused by fluctuations in operating current.
The operation of the B1-CMOS gate array integrated circuit is stabilized.

Next, the logic block LB2 includes, although not particularly limited to, six cell columns CG1 to CG6, as shown in FIG. Unit cells CU and CBU including a CU and a large number of unit cells CBU formed above and below these unit cells CU and made of bipolar transistors are functionally connected via inter-element coupling wiring (not shown), although this is not particularly limited. is coupled to constitute a Bi-0MO3 type logic gate circuit.

Although the logical block LB2 is not particularly limited, furthermore,
A plurality of step-down circuits VD are provided, two of which correspond to each cell column. Although not particularly limited, these step-down circuits have the same circuit configuration as the step-down circuit VD included in the logic block LBl, and form the internal power supply voltage Vcd based on the power supply voltage Vcc. Further, each step-down circuit VD is arranged close to the actual power distribution point of the power supply voltage supply main line SV and the ground potential supply main line SG, which are arranged vertically penetrating both sides of the logic block LB2, and Formed below the main line. As a result, the same effects as the logic block LBI described above can be obtained in terms of higher integration and stable operation of the Bi-CMOS gate array integrated circuit.

By the way, the unit cell CBU provided in the logic block LB2 in the form of a non-polar circuit is not particularly limited;
As its operating power supply, +5. OV power supply voltage Vcc
Requires. Therefore, the B1-CMOS of this example
In the gate array integrated circuit, another power supply voltage supply uASC is provided between the substantial input node of the step-down circuit VD, that is, the substantial power distribution point of the power supply voltage supply main line SV and the power supply voltage supply point of each cell column. is provided, and a power supply voltage Vcc is supplied to each unit cell CBU via this. In other words, although this B1-CMOS gate array integrated circuit requires a plurality of internal power supply voltages, only L types of power supply voltage supply main lines are routed within the semiconductor substrate SUB, and each cell By arranging the branch node of the power supply voltage Vcc for the column and the output node of the step-down circuit VD close to each other, the level difference between the power supply voltages is reduced. As a result, the integration of the B1-CMOS gate array integrated circuit is further promoted, and its operation is further stabilized.

On the other hand, the logic block LB3 includes five cell columns CG1 to CG5, as shown in FIG. 4, although this is not particularly limited. Each cell column consists of a large number of unit cells C consisting of 0MO3.
The unit cells CU and CBU, which include a unit cell U and a large number of unit cells CBU formed above and below these unit cells CU and made of bipolar transistors, are functionally coupled via inter-element coupling wiring (not shown). i-0MO3
Construct a logical gate circuit of the form.

In this logic program LB3, cell columns CG1 to CG
The unit cell CBU formed below the unit cell CU No. 5 requires an internal power supply voltage Vcs of, for example, +2.5cm, although it is not particularly limited. Therefore, logical block LB3
Furthermore, a plurality of step-down circuits VDI, two of which are provided corresponding to each cell column, form an internal power supply voltage Vcd based on the power supply voltage Vcc, and two step-down circuits VDI, which are similarly provided corresponding to each cell column. A plurality of step-down circuits VD2 are provided to form the internal power supply voltage Vcs based on the power supply voltage Vcc. Among these, the step-down circuit VDI has the same circuit configuration as the step-down circuit VD included in the logic block LBI, although it is not particularly limited, and the step-down circuit VD2 basically has a circuit configuration that follows the step-down circuit VD. Ru. The step-down circuits VDI and VD2 are arranged close to the actual power distribution points of the power supply voltage supply main line SV and the ground potential supply main line SG, which are arranged vertically penetrating both sides of the logic block LB3, and are arranged in the lower layer thereof. It is formed. The internal power supply voltage Vcs formed by the step-down circuit VD2 is supplied to the plurality of unit cells CBU constituting the corresponding cell column via the internal power supply voltage supply line SCS. As a result, the logic block LB3 is suitable for high integration and stable operation of the BiCMOS gate array integrated circuit.
It is possible to obtain the same effect as I, and also to obtain the same effect as the logic block LB2 in terms of unifying the power supply voltage.

As described above, the B1-CMOS gate array integrated circuit of this embodiment includes a logic block LBI including a plurality of cell columns in addition to macro cells such as an arithmetic logic unit ALU, a multiplication circuit MULT, and a random access memory RAM.
~Equipped with LB3.

A part of the cell columns forming these logic blocks is formed by highly miniaturized 0M03 circuits, and uses an internal power supply voltage Vcd having a small absolute value as an operating power supply. Further, a part of the circuit is constituted by a B i -0M03 circuit, and further requires a power supply voltage Vcc or an internal power supply voltage Vcs. The source voltage supplied externally to the B1-CMOS gate array integrated circuit in this embodiment is the same as that of the conventional B1-CMOS gate array integrated circuit.
In order to maintain compatibility with the S-gate array integrated circuit, the power supply voltage Vcc is unified, and a step-down circuit VD or VDI and VD2 is used to form the internal power supply voltages Vcd and Vcs based on this power supply voltage Vcc. Built-in. In this embodiment, a plurality of step-down circuits are provided corresponding to the actual power distribution points of the power supply voltage supply main line and the ground potential supply main line, that is, corresponding to each cell column, and are close to the corresponding power distribution point and supply the power supply voltage. It is formed below the aluminum wiring layer AL2 in which the main line and the ground potential supply main line are formed.

Further, the reference potential Vr necessary for each step-down circuit is formed by a reference potential ordering circuit VRG provided in common to all step-down circuits, and is arranged to be shielded between the power supply voltage supply main line and the ground potential supply main line. Reference potential supply line SR
is transmitted to each step-down circuit via. As a result, in the Bi CMOS gate array integrated circuit of this embodiment, a plurality of step-down circuits are provided without causing a decrease in the degree of integration, and these step-down circuits are connected to the main power supply voltage supply main line and the ground potential supply main line. can be located close to a power distribution point. As a result, while promoting higher integration of B1-CMOS gate array integrated circuits, it is possible to suppress level fluctuations of each internal power supply voltage, further suppress power supply noise due to fluctuations in operating current, and improve B+-CMOS gate array integrated circuits. This makes it possible to stabilize the operation of the circuit.

As shown in the above embodiment, this invention can be applied to B1-C
By being applicable to semiconductor integrated circuit devices such as MOS gate array integrated circuits, the following effects can be obtained. That is, the power supply voltage of the fllB t -CMOS gate array integrated circuit, etc. is unified, and a plurality of step-down circuits are provided corresponding to the actual power distribution points, that is, each cell column, and each step-down circuit is provided close to the corresponding cell column. In addition, by forming it in a layer below the power supply voltage supply main line and the ground potential supply main line, it is possible to obtain the effect that multiple step-down circuits can be provided without reducing the degree of integration of the B1-CMOS gate array integrated circuit, etc. .

(2) According to the above (1), is the internal type formed by the step-down circuit? The effect of suppressing level fluctuations in the Ig voltage and suppressing power supply noise accompanying fluctuations in operating current can be obtained.

(3) In the above items +11 and (2), the reference 1 generation circuit that forms the reference potential is provided in common to all the step-down circuits, and the reference potential supply line that transmits the reference potential is set to ? By forming the voltage between the source voltage supply main line and the ground potential supply main line in the same layer, it is possible to unify and stabilize the level of the internal power supply voltage formed by the step-down circuit.

(41 Above (paragraphs 11 to 31, B i -CM
While promoting high integration of OS gate array integrated circuits,
This has the effect of stabilizing the operation and increasing its reliability.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in FIG. 1, the number and combination of macro cells and logic blocks mounted on the B1 CMOS gate array sg1 circuit are arbitrary. Further, the arrangement method and direction of the power supply voltage supply main line and the ground potential supply main line including the power supply voltage supply bus and the ground potential supply bus are not restricted by this embodiment. Another (circle) may be provided on the lower side of PZ. In FIGS. The step-down circuit is connected to the power supply voltage supply bus SBV
and the ground potential supply bus SBG, or may be provided corresponding to macro cells such as the arithmetic and logic unit unit L-ALU and the random access memory RAM, if necessary. The configuration and arrangement method of each logic block and each cell column is arbitrary. In FIG. 5, various embodiments can be considered for the specific circuit configuration of the step-down circuit VD, and the layout method of the inter-element coupling wiring is also arbitrary.

! In FIG. 46, the metal wiring layer is not required to be formed of aluminum or its alloy. Further, the number of aluminum wiring layers is arbitrary, and the use of each aluminum wiring layer is also arbitrary.

In the above explanation, the invention made by the present inventor was mainly applied to Bt-CMOS gate array integrated circuits, which is the background field of application, but the invention is not limited thereto. B1-CMOS gate array 9 product circuit equipped with only cells and B
It can also be applied to a dedicated logic integrated circuit device etc. whose basic configuration is an i-CMO3 composite circuit. The present invention can be widely applied to semiconductor integrated circuit devices that include a built-in voltage conversion circuit for forming at least an internal power supply voltage.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, the power supply voltage of the B1-CMOS gate array integrated circuit, etc. is unified, and a plurality of step-down circuits are provided corresponding to the actual power distribution points, that is, cell rows, and the power supply voltage is supplied close to the corresponding cell row. Formed below the main line and ground potential supply main line. Further, a reference potential generation circuit for generating a reference potential is provided in common to all the step-down circuits, and a reference potential supply line for transmitting the reference potential is formed between a power supply voltage supply main line and a ground potential supply main line. As a result, a plurality of step-down circuits can be provided in a B1-CMOS gate array integrated circuit, etc., and the level of the internal power supply voltage formed thereby can be unified and stabilized, without causing a decrease in packaging efficiency. As a result, it is possible to promote high integration of B1-CMOS gate array integrated circuits and the like, stabilize the operation, and improve the reliability thereof.

[Brief explanation of drawings]

FIG. 1 is a board layout diagram showing an embodiment of a 131-CMOS gate array integrated circuit to which the present invention is applied. FIG. FIG. 3 is a layout diagram showing an embodiment of the logic block of 'iS2 included in the B1-CMOS gate array integrated circuit of FIG. 1; FIG. B1-A layout diagram showing an embodiment of the third logic block included in the CMOS gate array integrated circuit in FIG. 1; A circuit diagram showing an embodiment, the sixth circuit is a sectional view showing an embodiment of a step-down circuit in the fifth section. 5LJB...Semiconductor substrate, 1z...Substrate internal area,
pz...substrate peripheral area, VCC...pad for supplying power voltage, GND...pad for supplying ground potential, PAD...
...Other bands, SBV...Power supply voltage I1 (supply bus, SBG...Ground potential supply bus, SV...Power supply voltage supply main line, SG...Ground potential supply main line, SR...
Reference potential supply line, 101, 102...input/output bumper, VRG...reference potential generation circuit, A L L+...
Arithmetic logic unit, MULT...Multiplication circuit, RE
G...L nozzle file, ROM...read only memory, RAMI~RAM3...random access memory, LBI~LB3...logic block. VD...Door pressure circuit, C, C, I-CGIO...Cell column, C[, J...('', MOSφ cell, CB
U... Bipolar unit cell, S CV... Power supply voltage supply line, SCD, SC3... Internal power supply voltage supply line, S
CG...Ground potential supply line. Q1~Q3...P channel MOS FET. Qll-Q13...N-channel MO3FET. CI...Capacitor.

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device comprising a plurality of voltage conversion circuits distributed in an internal region of a semiconductor substrate. 2. The voltage conversion circuit is a step-down circuit for forming, based on a predetermined power supply voltage, an internal power supply voltage whose absolute value is smaller than the power supply voltage. semiconductor integrated circuit devices. 3. The semiconductor integrated circuit device includes a power supply voltage supply trunk line and a ground potential supply trunk line for transmitting the power supply voltage, and the step-down circuit is configured to substantially connect the power supply voltage supply trunk line and the ground potential supply trunk line. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is provided corresponding to a power distribution point. 4. The semiconductor substrate on which the semiconductor integrated circuit device is formed includes a plurality of metal wiring layers, and the step-down circuit is formed in a layer below the power supply voltage supply main line and the ground potential supply main line. A semiconductor integrated circuit device according to claim 1, 2, or 3. 5. The potential of the internal power supply voltage is set according to a predetermined reference potential, and the reference potential generation circuit for forming the reference potential is provided in common to a plurality of the step-down circuits. Claims 1 and 2
4. A semiconductor integrated circuit device according to item 3, item 4, or item 4. 6. The power supply main line and the ground potential supply main line are formed in parallel to the metal wiring layer of the same layer, and the reference potential supply line that transmits the reference potential is connected to the power supply voltage supply main line and the ground potential supply line. Claims 1, 2, 3, and 4 are formed between potential supply main lines.
5. The semiconductor integrated circuit device according to item 5. 7. The internal circuit further receives the power supply voltage, and a power supply voltage supply line for transmitting the power supply voltage to the internal circuit is branched from a substantial input node of the corresponding step-down circuit. Claims 1, 2, 3, 4, 5, or 6 are characterized in that:
The semiconductor integrated circuit device described in . 8. The internal circuit further receives another internal power supply voltage whose potential is different from the internal power supply voltage,
Another voltage generation circuit that generates the other internal power supply voltage based on the power supply voltage is formed in the vicinity of the corresponding internal circuit and below the power supply main line and the ground potential supply main line. A semiconductor integrated circuit device according to claim 1, 2, 3, 4, 5, or 6. 9. The semiconductor integrated circuit device is a bipolar CMOS gate array integrated circuit including a logic block including a plurality of cell columns, and the power distribution point is provided corresponding to the cell column. Claim 1
A semiconductor integrated circuit device according to item 1, 2, 3, 4, 5, 6, 7, or 8.