JPH03272166A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable an excess circuit to be effectively employed so as to improved a semiconductor integrated circuit in degree of integration by a method wherein output circuit forming transistors which become excess when an input- output buffer forming region is used as an input circuit are used to constitute a power supply voltage conversion circuit. CONSTITUTION:An input-output unit circuit 15 can be used as various kinds of circuit such as an input circuit, an output circuit, or an input-output circuit, and when the circuit 15 is used as an input circuit, transistors used for an output circuit become excess. A supply voltage conversion circuit 17 is constituted taking advantage of the excess transistors concerned, the circuit 15 is used as both an input circuit 17 and a circuit 18, and the circuit 15 not used for an input-output circuit is separately used as a supply voltage conversion circuit 19. As transistors of large size used in an output circuit are used in the circuits 17 and 19, a semiconductor device of this design is large in power supply capacity. By this setup, a semiconductor integrated circuit of this design can be improved in degree of integration taking advantage of an excess circuit without providing a dedicated power supply circuit.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit having a built-in power supply voltage conversion circuit for converting an external power supply voltage to an internal power supply voltage that is compatible with an internal circuit. The present invention relates to semiconductor integrated circuits such as gate arrays or standard cells designed based on or reflecting the same, and relates to techniques that are effective when applied to, for example, microcomputers.

[Conventional technology]

Gate arrays and standard cells are typical examples of semiconductor integrated circuits that are designed and manufactured according to customer specifications and logic circuits. These semiconductor integrated circuits include an internal circuit that performs complex functional operations and data storage, and a covered circuit that interfaces with the outside surrounding the internal circuit. In these input/output buffer circuits, various input circuits,
Generally, it is possible to select an output circuit or an input/output circuit.

Now, with the evolution of processes and the miniaturization of devices, devices are no longer able to withstand voltage with a single power supply voltage such as the conventional 5-inch voltage. However, for users who use various semiconductor integrated circuits mounted on the same board, it is desirable to avoid supplying multiple types of power supply voltages. Therefore, it is common to configure a power supply voltage conversion circuit within a semiconductor integrated circuit to lower the internal power supply voltage to, for example, 3V while maintaining the external power supply voltage at 5V.

An example of a gate array incorporating this power supply voltage conversion circuit is THPM13.1 (PP
176-177) (A BiCMO5Ch
anneless Masterslice 0n-
Chip V.

], stage Converter). In this gate array, a power supply voltage conversion circuit is configured inside the input/output buffer circuit and surrounds the internal circuit.

[Problem to be solved by the invention]

In the above conventional technology, the power supply voltage conversion circuit is configured in a dedicated area independent of the internal circuits and input/output buffer circuits.
Compared to semiconductor integrated circuits that do not require a power supply voltage conversion circuit, the degree of integration is lower. In particular, in semiconductor integrated circuits that operate at high speed, the current supply capacity of the power supply voltage conversion circuit must be increased, so a large number of power supply voltage conversion circuits are required, and the area dedicated to such conversion circuits is relatively large from the beginning. This will take up a lot of space and significantly reduce the degree of integration3.

An object of the present invention is to provide a semiconductor integrated circuit that can configure a power supply voltage conversion circuit without reducing the degree of integration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a semiconductor integrated circuit in which an input/output buffer forming area connected to the outside is arranged at the peripheral edge of a semiconductor substrate, and necessary circuits are formed in the inner area, various input circuits, Transistors for configuring an output circuit or an input/output circuit are independently included. Therefore, when the input/output buffer forming area is used as an input circuit, large transistors for configuring the output circuit are left unused. The present invention constructs a power source voltage conversion circuit using these unused transistors for configuring an output circuit.

In order to improve the current supply capability from the power supply voltage conversion circuit, it is preferable to utilize as many unused output circuit configuration transistors as possible in the power supply voltage conversion circuit. For example, in a logic LSI such as a microcomputer, external terminals 174 to
About 378 are used as input terminals. According to this, the unused output circuit configuration transistors will occupy more than 4/4 to 3/8 of the total in the input/output cover sofa formation area,
As much as possible, all of it can be used for the power supply voltage conversion circuit.

The location where the power supply voltage conversion circuit is formed in the input/output buffer formation area is determined by the layerer 1 to state of the various circuits formed in the area. Therefore, in order to be able to configure a power supply voltage conversion circuit no matter where the unused output circuit is located, it is necessary to It is preferable that the internal power supply main line to be coupled be routed along the input/output buffer forming area.

In addition, when the conversion level of the power supply voltage by the power supply voltage generation circuit is determined by the reference voltage, the reference voltage generation circuit and the input/output buffer forming area for transmitting the reference voltage generated by the reference voltage generation circuit are provided. It is preferable to provide a reference voltage wiring line along the line.

[For production]

According to the above-mentioned means, a power supply voltage conversion circuit having the required current supply capability is constructed by reusing unused output circuit configuration transistors in the input/output buffer formation region. This works so that there is no need to reserve a transistor area dedicated to the power supply voltage conversion circuit in advance in the standard cell or gate array, and it is therefore possible to configure the power supply voltage conversion circuit without reducing the degree of integration. .

〔Example〕

FIG. 1 shows an embodiment of a semiconductor integrated circuit according to the present invention.

The semiconductor integrated circuit shown in the figure is a microcomputer formed by a standard cell method or a gate array method, although it is not particularly limited, and is formed on a semiconductor substrate such as silicon.

The internal circuit forming area 3 located in the center of the semiconductor substrate has random logic 4 to
6, register file 7, arithmetic logic unit 8, multiplier 9
, ROM (read-only memory) 10, and R
AM (random access memory) 11 to 3 are configured.

The area around the internal circuit forming area 3 is an input/output buffer forming area 2, in which a large number of input/output unit circuits 15 that can selectively configure an input circuit, an output circuit, or an input/output circuit are arranged, and each input/output A large number of pads 6 such as bonding pads or metal bump electrodes are provided corresponding to the unit circuits 15.

Here, in the semiconductor integrated circuit of this embodiment, the operating voltage of each circuit block in the internal circuit formation region 3 is, for example, 3V. At this time, in order to operate by receiving an external power supply voltage of, for example, 5V, a configuration is required to internally step down the external power supply voltage to 3V and supply it to each circuit block in internal circuit formation area 7-3. become.

Conventionally, a dedicated transistor area for a power supply voltage conversion circuit was provided between the internal circuit forming area 3 and the input/output buffer forming area 2, but in this embodiment, an unused transistor area is provided in the input/output unit circuit 15. A power supply voltage conversion circuit is configured using transistors for configuring an output circuit.

Next, a specific method of configuring the power supply voltage conversion circuit will be explained.

The input/output unit circuit 15 can be used as various input circuits, output circuits, or input/output circuits according to the user's specifications, but when used as an input circuit, the transistors for the output circuit become redundant. Some of them include large-sized transistors. Therefore, the power supply voltage conversion circuit 17 is constructed using the surplus transistors, and the input/output unit circuit 15 is connected to the input circuit 8 and the power supply voltage conversion circuit 17.
used as Further, the input/output unit circuit 15 which is not used for input/output is used alone as a power supply voltage conversion circuit 19. The power supply voltage conversion circuit 17.19 is a large-sized transistor for the output circuit.
Each transistor has a relatively large power supply capacity, and a large number of unused output circuit configuration transistors can be used to configure a large number of power supply voltage conversion circuits, so it has sufficient current supply capacity to satisfy the requirements for high-speed operation. can be obtained.

In the upper layer of the input/output buffer formation area 2, there is an external power supply wiring 20 to which an external power supply voltage such as 5.
．． An internal power supply main line 21 to which an internal power supply voltage such as 3V is supplied from the power supply voltage conversion circuit is circulated. The power supply voltage conversion circuit 17 formed in the input/output unit circuit 15 that is not used as an output circuit is coupled to the external power supply wiring 20, and the input circuit 18 included in the unit circuit 15 is coupled to the corresponding pad 16. . On the other hand, the power supply voltage conversion circuit 9 included in the input/output unit circuit 15 which is not used as an input/output circuit is coupled to the external power supply wiring 20 and to the corresponding pad 6. The power supply output terminal of the power supply voltage conversion circuit 1-7.18 is coupled to the internal power supply main line 21-. The internal power supply voltage supplied to the internal power main line 21 is supplied to various internal circuits via the internal power supply branch line 22. In FIG. 1, the external power supply wiring 20 is shown as a - line wiring, but it may be provided for an input circuit and an output circuit, respectively. Also,
In FIG. 1, a power supply wiring for a low-level voltage such as a ground potential is omitted, but in reality, a power supply wiring coupled to a specific pad exists.

The circuit configuration of the power supply voltage conversion circuits 17 and 19 is determined depending on the number and types of transistors included in the input/output unit circuit 15. For example, when adopting a circuit configuration in which the level of the internal power supply voltage with respect to the external power supply voltage is determined using the base voltage, the reference voltage generation circuit can be constructed by each input/output unit circuit 15. For example, 1 to 8 Bi-CMO circuits can be configured in the input/output unit circuit 15.
If a transistor is included, a bandgap reference voltage generation circuit using bipolar transistors can be employed. Furthermore, in the case of an MO8 type semiconductor integrated circuit, a reference voltage can be generated using the difference in threshold voltage between a pair of MOSFETs. At this time, the threshold voltage of the MOSFET varies depending on the manufacturing conditions, so in order to obtain a highly accurate reference voltage, a pair of MOS
Consideration must be given to making the load resistance of the FET adjustable by laser trimming or the like.

In this embodiment, a large number of power supply voltage conversion circuits 17 and 19 share the reference voltage generation circuit 24. That is, the reference voltage generation circuit 24 is configured at the corner of the input/output buffer formation area 2, and the reference voltage generated by the circuit is transmitted through the reference voltage wiring 25 which is routed around the -L layer of the input/output buffer formation area 2. The voltage is supplied to the respective power supply voltage conversion circuits 17 and 19 via the power supply voltage conversion circuits 17 and 19.

FIG. 2 shows the CM and O8 configured in the input/output unit circuit 15.
An example output circuit of the type is shown.

In the same figure, P-channel type MO8FETQI and N-channel type MO8FETQ2 are relatively large transistors that constitute the final 11 2 stage of output, and the Nant gate NAN that constitutes the flip-flop circuit.
D3-. NOR gates N0R1- and N0R2, which constitute the NAND2 and flip-flop circuits, convert the input logic level of Ov~3■ to OV~5■, and MO8FET
This is a logic gate for driving QI and O2. An external power supply voltage such as 5V is supplied to these transistors and logic gates. In addition, inverters INVI to INV
3 operates with an internal power supply voltage such as 3■, and the gate N
ANDI, NAND2. Controls N0RI and N0R2.

In this output circuit, when the enable signal EN is set to high level, both MO8FETQI.

O2 is cut off into a high output impedance state.

When the enable signal EN is set to low level, the output circuit performs an output operation according to the level of the data Din. That is, when the data Din is set to a high level, the flip-flop constituted by the NAND gates NANDi and NAND2 outputs a low level, and the NAND gate hN
When the flip-flop constituted by OR1 and N○R2 outputs a low level, the output circuit outputs data l) out having a logic level such as 5■. On the other hand, when the data Djn is set to low level, the flip-flop composed of NAND gates NANDI and NAND2 outputs high level, and the flip-flop composed of NOR gates N0RI and N0R2 outputs high level. , the output circuit outputs data I) with a logic level such as Ov.
Output. Note that Vcc is an external power supply voltage such as 5V.

FIG. 3 shows an example of a power supply voltage conversion circuit constructed using the transistors for configuring the output circuit shown in FIG. 2. In FIG.

The MO8FETQI is used as a drive MO8FET for supplying a power supply voltage, and the M○5FETQ2 is used as an oscillation prevention capacitor. In addition, MO8
The ground potential of the circuit is applied to the drain and source electrodes of the FETQ2, and the gate electrode of the MO8FETQ2 is coupled to the drain electrode of the MO8FETQI, and the coupled node serves as an output terminal for the internal power supply voltage Vint. The driving MO8FETQI is a pair of P-channel type MO8FETQ3. A current mirror load consisting of Q4 and a pair of N-channel MO8FETs Q5. Q
6 and N-channel power switch MO8FETQ7
It is controlled by a circuit consisting of Input MO8F
A reference voltage V r e f such as 3V generated by the reference voltage generation circuit 24 is applied to the gate electrodes of the ETQ5 and the power switch MO8FETQ7. the other input M
MO8FETQI and M are connected to the gate electrode of O8FETQ6.
A coupling node of O8FETQ2 is connected. The driving MO8FETQ is controlled by the voltage of the common drain electrode of the MO8FETQ3 and Q5. This circuit refers to the reference voltage Vref to drive MO8FETQI.
to control the internal power supply voltage Vint to the reference voltage V r e
The voltage is controlled to be equal to f. In addition, MO8FETQ3~
Q7 is the gate NANDI, NAND2 . N0RI,
N.

It is formed by a transistor forming R2.

Here, an example of transistor size is MO
8FETQI, Q2 is W (channel width) = 600μm
, MO8FETQ3-Q7 has W=about 50 μm, and transistors included in the internal circuit formation region 3 have W=15 to 20 μm.
It is about μm. Further, as an example of how the pads 16 are used in the entire LSI, the power supply terminals are about 115 of the total, and the input circuits are about 1/4 to 3/8 of the total. Therefore, at this time, the number of power supply voltage conversion circuits 17 and 19 constituted by unused output circuit configuration transistors is:
14/40 to 19/40 for all input/output unit circuits
(assuming a field in which half of the power supply terminals are assigned to GND), and sufficient current supply capacity is obtained.

According to the above embodiment, there are the following effects.

(1) Unused output circuits 15- in the input/output buffer formation area 2. Since the power supply voltage conversion circuits 17 and 19 with the required current supply capacity are constructed using the transistors for configuring the There is no need to reserve a transistor area exclusively for the power supply voltage conversion circuit in advance.

(2) Conventionally, when a specific pad 16 was used as a power supply terminal, the input/output unit circuit 15 corresponding to the pad was considered unused. It is possible to effectively utilize the output buffer forming area.

(3) All the unused output circuit configuration transistors in the input/output buffer formation area 2 can be allocated to the power supply voltage conversion circuits 17 and 19, so a large power supply current supply capacity can be easily obtained and high-speed operation can be achieved. We can fully meet your demands.

(4) From the above-mentioned effects, it is possible to configure a power supply voltage conversion circuit with the required current supply capability without reducing the degree of integration.

(5) By making the internal mold 16-source main line 21 and external power supply wiring 20 go around the upper layer of the input/output buffer formation area 2, the power supply voltage conversion circuit can be placed at any position in the input/output buffer formation area 2. 17.19 can be configured.

(6) When a circuit configuration in which the level of the internal power supply voltage with respect to the external power supply voltage is determined using a reference voltage is adopted for the power supply voltage conversion circuit 17.19, the reference voltage generation circuit 24 is 19, and the reference voltage generated thereby is applied to the input/output buffer forming area 2.
By supplying the power to each power supply voltage conversion circuit 17 and 19 via the reference voltage wiring 25 that is routed in the upper layer,
It is possible to reduce the number of circuits such as resistor string circuits for adjusting fluctuations in the reference voltage due to variations in element characteristics due to manufacturing conditions, and contributes to shortening the adjustment work time.

Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, the types of circuit blocks configured in the internal circuit formation area are not limited to the above embodiments. Further, the specific circuit configuration of the power supply voltage conversion circuit is not limited to the above embodiment, and can be changed as appropriate depending on the type of transistor included in the input/output buffer formation region. For example, not only the CMO8 circuit, but also a Bj-CMO8 circuit, an NMO8 circuit, a bipolar circuit, etc. can be changed as appropriate. Further, it goes without saying that the configuration of the output circuit is not limited to the above embodiment.

The above explanation has mainly been about the case where the invention developed by the present invention is applied to semiconductor integrated circuits such as microcomputers, which is the background field of application. It can be widely applied to various semiconductor integrated circuits such as peripheral circuits and peripheral circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, the unused output circuit configuration transistors in the crowded cover sofa formation area are used to configure the power supply voltage conversion circuit with the required current supply capacity, so the transistor area dedicated to the power supply voltage conversion circuit in the standard cell or gate array is used. There is no need to secure this in advance, and this has the effect that the power supply voltage conversion circuit can be configured with the required current supply capability without reducing the degree of integration.

By placing the internal power supply main line and the external power supply wiring around the upper layer of the cover sofa formation area, a power supply voltage conversion circuit can be configured at any position in the input/output buffer circuit formation area.

When a power supply voltage conversion circuit employs a circuit configuration that uses a reference voltage to determine the level of the internal power supply voltage relative to the external power supply voltage, the reference voltage generation circuit is shared by a large number of power supply voltage conversion circuits, and the level of the internal power supply voltage generated by this is By supplying the reference voltage to each power supply voltage conversion circuit through the reference voltage wiring routed in the upper layer of the input/output buffer formation area, the reference voltage can fluctuate due to variations in device characteristics due to manufacturing conditions. It is possible to reduce the number of circuits for adjusting the
This contributes to shortening the adjustment work time.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of an example of an output circuit configured in an input/output buffer formation area, and FIG. 3 is a circuit diagram of an example of an output circuit configured in an input/output buffer formation area. FIG. 2 is a circuit diagram of an example of a power supply voltage conversion circuit. 1-... Semiconductor substrate, 2... Input/output buffer formation area, 3... Internal circuit formation area, 15... Input/output unit circuit, 16... Pad, 1-7... Power supply voltage conversion Circuit, 18... Input circuit, Engineering 9... Power supply voltage conversion circuit, 2
0...Wiring for external power supply, 21...Main line for internal power supply,
24... Reference voltage generation circuit, 25... Reference voltage wiring. ←〉 Jin〉

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit in which an input/output buffer formation area connected to the outside is arranged at a peripheral portion of a semiconductor substrate, and a necessary circuit is configured in an inner area of the input/output buffer formation area, wherein the input/output buffer A semiconductor integrated circuit that includes a power supply voltage conversion circuit formed by a part of transistors in a forming region, and the power supply voltage conversion circuit steps down an external power supply voltage and supplies it to an internal region. 2. The power supply voltage conversion circuit is formed in the input/output buffer formation region by a plurality of transistors for configuring an output buffer circuit that are not used as an output buffer circuit, and transistors for configuring an input/output buffer circuit that are not used as an input/output buffer circuit. 2. The semiconductor integrated circuit according to claim 1. 3. An external power supply line coupled to an external power supply terminal and an internal power supply trunk line coupled to an internal power supply branch line in the internal area are wired along the input/output buffer forming area, or 2. The semiconductor integrated circuit according to 2. 4. The power supply voltage conversion circuit includes a reference voltage generation circuit and a reference voltage wiring line arranged along the input/output buffer formation area to transmit the reference voltage generated by the reference voltage generation circuit. 4. The semiconductor integrated circuit according to claim 3, wherein the conversion level of the power supply voltage is determined according to the level of the reference voltage supplied from the reference voltage wiring.