JP2000174139A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable performing d-c test with less wirings, using a MOSFET having a low threshold voltage by switching a switch circuit according to a control signal and also serving it for a back vias voltage. SOLUTION: A switch circuit is switched by control signals PDP, PDN, and a p- and n-channel MOSFETs constituting a logic circuit are formed on a well region or a substrate to which a voltage corresponding to an operating voltage of the logic circuit is fed in the usual operation. In a d-c test mode or standby mode, a back bias voltage is fed to the well region of the logic circuit or the substrate so as to make the threshold voltage high, i.e., a voltage higher than the power voltage is fed to a p-channel MOSFET and a negative voltage lower than the ground potential of the circuit is fed to an n-channel MOSFET. Thus, it is possible to operate a CMOS circuit in two modes, effectively using wiring channels.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and mainly to a MOSFET having a low threshold voltage.
CMO using (insulated gate field effect transistor)
The present invention relates to a technology effective for use in an S (complementary MOS) gate array or the like.

[0002]

2. Description of the Related Art In order to achieve both high speed and low power consumption of a semiconductor integrated circuit device, a variable threshold MOSF is used.
The threshold voltage of a MOSFET operated at high speed using ET is low, and the threshold voltage of a MOSFET not required to operate at high speed is increased. To control such different threshold voltages, a dedicated circuit for controlling the well potential is provided with a control circuit for setting a bias voltage applied to the well region in which the MOSFET is formed, in addition to the base region of the gate array. There is something. Regarding such a gate array, CICC (CICC),
1996, pages 53-56.

[0003]

In a CMOS gate array, there is a tendency to lower the threshold voltage for miniaturization and higher speed. When the MOSFET is lowered in threshold voltage as described above, the DC current flowing between the power supply voltage and the ground potential of the circuit increases even in the CMOS circuit, and a DC test during standby in which the logic circuit does not operate at all is performed. There is a problem that it becomes impossible. That is, the leak current of the MOSFET increases due to the lower threshold voltage,
Since the variation is relatively large, it is impossible to determine the presence or absence of a leak current due to insulation failure between the power supply voltage and the ground potential of the circuit. Therefore, it is conceivable to supply a back bias voltage that does not cause a leak current to flow through a MOSFET during a DC test by using the above-described bias voltage control technique. However, this requires a power supply line for supplying a back bias voltage in addition to the normal operation voltage, and a control signal for switching the voltage between the normal operation and the test operation. There is a problem that the number of provided power supply lines and signal lines is increased.

It is an object of the present invention to provide a low threshold voltage MO.
An object of the present invention is to provide a semiconductor integrated circuit device having a CMOS configuration that enables a DC test with a small number of wirings while using an SFET. Another object of the present invention is to provide a low threshold voltage M
It is an object of the present invention to provide a semiconductor integrated circuit device having a CMOS configuration that achieves low power consumption during standby using a small number of wires while using an OSFET. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, P-channel type MOSFE
A CMOS logic circuit comprising a T and an N-channel MOSFET, and an operating voltage supplied to a source of one MOSFET of the CMOS logic circuit with respect to a substrate or a well region where the P-channel MOSFET or the N-channel MOSFET is formed. Alternatively, a switch circuit for selectively switching and supplying a back bias voltage to the first MOSFET constituting the CMOS logic circuit is provided, and when the switching control signal is set to one level corresponding to the back bias voltage, the voltage is applied to the first MOSFET. And supplying the operating voltage to the substrate or well region when the switching control signal is set to the other level corresponding to the ground potential of the circuit.

[0006]

FIG. 1 is a schematic block diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention. Each circuit block shown in the figure is formed on one semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique.

[0007] An input / output circuit I / I
O is provided, and a logic cell is provided in the internal circuit region. The internal circuit area is a spread gate area, and the circuit function of the logic circuit is realized by the connection design. A plurality of cells constituting a switch circuit according to the present invention are dispersed in an internal circuit using unused cells in the spread gate region.

This switch circuit (cell) is controlled by a control signal P
A voltage corresponding to the operating voltage of the logic circuit is supplied to the well region or substrate in which the P-channel MOSFET and the N-channel MOSFET forming the logic circuit are switched by the DP and the PDN, respectively. In the DC test mode or the standby mode, a back bias voltage for increasing the threshold voltage with respect to the well region or the substrate of the logic circuit, that is, a voltage higher than the power supply voltage for a P-channel MOSFET is supplied; In an N-channel MOSFET, a negative voltage lower than the ground potential of the circuit is supplied.

It is characterized in that the control signals PDP and PDN also serve as the back bias voltage together with the switching control of the switch circuit. That is, the control signal P
For a P-channel type MOSFET, when the voltage is set to a voltage higher than the power supply voltage VDD in order to increase the threshold voltage of the P-channel MOSFET and substantially prevent a leak current from flowing, the DP is set to the above-described voltage. Supply to the well region or substrate, when it is brought to a potential such as the ground potential of the circuit,
The power supply voltage VDD is supplied to the well region or the substrate. The control signal PDN is an N-channel type MOSFE
T is set to a negative voltage equal to or lower than the ground potential VSS of the circuit in order to increase the threshold voltage and substantially prevent leakage current from flowing. And when it is set to a high level such as the power supply voltage VDD, the ground potential VSS
Is supplied to the well region or the substrate.

Thus, only the power supply voltage line for supplying the original operating voltage and the circuit ground line and one signal line each serving as the control signal and the back bias voltage are added to the switch circuit. Just do it. As a result, it is possible to reduce the power consumption in a standby state in which no operation is performed, as described later, while enabling the DC test while effectively utilizing the wiring channels formed in the gate array.

FIG. 2 is a circuit diagram showing one embodiment of the above switch circuit. In this embodiment, although not particularly limited, the P-channel type MOSFET includes a P + type source S and a drain D formed in an N type well region NWELL, and a thin gate on a surface of a semiconductor region sandwiching the source S and the drain D. A gate electrode G formed via an insulating film. The above P-channel type MOSFE
The well region NWELL where the T is formed is a P-type substrate PS
UB is formed. The switch circuit includes a well region NWELL in which the P-channel MOSFET is formed.
Is performed.

A power supply voltage VDD and a circuit ground potential VSS are applied to the CMOS logic circuit as operating voltages.
A power supply voltage VDD is supplied to a source S of the P-channel MOSFET exemplarily shown in FIG. In the semiconductor integrated circuit device of this embodiment, in addition to the power supply line VDD for supplying the operating voltage and the circuit ground line VSS, the power supply line for the back bias voltage and the switching control line are also provided for the spread gate region. Wiring is provided. FIG. 1 shows only a switch circuit that supplies a back bias voltage to the P-channel MOSFET as described above in the CMOS logic circuit.

In the N-type well region NWELL in which the P-channel MOSFET is formed, a P-channel switch MOSFET Q1 and an N-channel MOSFET are provided.
A control signal PDP also serving as the back bias voltage is supplied via a first CMOS switch made of TQ2,
P-channel MOSFET Q3 and N-channel MO
The operating voltage VDD is supplied via a second CMOS switch including the SFET Q4.

In order to selectively switch between the first and second CMOS switches, a gate of a P-channel MOSFET Q1 constituting the first CMOS switch and an N-channel MOSFET constituting a second CMOS switch are provided.
A CM receiving the control signal PDP is provided in the gate of TQ4.
The output signal of the OS inverter circuit IV1 is supplied. N-channel type MOS constituting the first CMOS switch
The CM receiving the output signal of the CMOS inverter circuit IV1 is connected to the gate of the FET Q2 and the gate of the P-channel MOSFET Q3 forming the second CMOS switch.
The output signal of the OS inverter circuit IV2 is supplied.

Control signal (or power down signal) PDP
Is low level VT such as the ground potential of the circuit,
The output signal of the CMOS inverter circuit IV1 is the power supply voltage V
The CMOS inverter circuit I is set to a high level such as DD.
The output signal of V2 is set to a low level such as the ground potential of the circuit. Therefore, the P which constitutes the second CMOS switch
Channel type MOSFET Q3 and N channel type MOS
The FET Q4 is turned on, and the well region NWE is turned on.
LL is supplied with the operating voltage VDD. That is, during the normal operation, the control signal PDP is set to the low level, and the P-channel type MO constituting the CMOS circuit is set.
The SFET operates at a high speed with a low threshold voltage.

When the control signal PDP is at a high level (VP
In the case of P), the CMOS inverter circuit IV1 is set to low level, and the CMOS inverter circuit IV2 is set to high level. Therefore, the P-channel MOSFET Q1 and the N-channel MO constituting the first CMOS switch
The SFET Q2 is turned on, and the well region NWE is
LL is supplied with the high level of the control signal PDP also serving as the back bias voltage VPP. That is, the power supply voltage V
A P-channel type MO supplied with a power supply voltage VDD by a control signal PDP which is set to a higher potential VPP than DD.
The potential of the well region NWELL is set to a high voltage such as VPP with respect to the source S of the SFET, and a back bias voltage is supplied to the P-channel MOSFET.

Therefore, when the power supply voltage VDD is supplied to the gate G and the leakage current flowing between the power supply voltage VDD and the ground potential VSS of the circuit is measured in the off state, or the semiconductor integrated circuit device does not operate at all. When the gate voltage is at a high level such as VDD in a standby state where the operation is not performed, the control signal PDP is set to a high level, and the P-channel MOSFET constituting the CMOS circuit is set to a high threshold voltage to configure a CMOS circuit. The leakage current flowing through the off-state P-channel MOSFET and the on-state N-channel MOSFET is suppressed to a small current that can be regarded as zero. This makes it possible to determine a DC failure due to insulation failure or the like, and to make use of the low power consumption of the CMOS circuit in the standby mode.

FIG. 3 is a circuit diagram showing one embodiment of the above switch circuit. In this embodiment, although not particularly limited, the N-channel MOSFET is a P-type substrate PS
It is composed of an N + type source S and drain D formed by UB, and a gate electrode G formed on a surface of a semiconductor region sandwiching the source S and drain D via a thin gate insulating film. The switch circuit of this embodiment performs a voltage switching operation for the substrate PSUB on which the N-channel MOSFET is formed.

An N-channel type M shown as an example in FIG.
The source S of the OSFET is supplied with the ground potential VSS of the circuit. The control signal PDN also serving as the back bias voltage is supplied to the P-type substrate PSUB on which the N-channel MOSFET is formed via a third CMOS switch including a P-channel switch MOSFET Q5 and an N-channel MOSFET Q6. , P-channel MOSFET Q7 and N-channel MOSFET
The ground potential VSS is supplied through a fourth CMOS switch including Q8.

In order to selectively switch between the third and fourth CMOS switches, a gate of a P-channel MOSFET Q7 forming a fourth CMOS switch and an N-channel MOSFET forming a third CMOS switch are provided.
A CM receiving the control signal PDN is provided in the gate of TQ6.
The output signal of the OS inverter circuit IV3 is supplied. N-channel type MOS constituting the fourth CMOS switch
The CM receiving the output signal of the CMOS inverter circuit IV3 is connected to the gate of the FET Q8 and the gate of the P-channel MOSFET Q5 constituting the third CMOS switch.
An output signal of the OS inverter circuit IV4 is supplied.

When the control signal PDN is at a high level such as the power supply voltage VDD, the CMOS inverter circuit IV3
Is output to a low level such as the ground potential of the circuit,
The output signal of MOS inverter circuit IV4 is at power supply voltage VD
It is set to a high level like D. Therefore, the fourth CMO
P-channel MOSFET Q7 constituting S switch
Then, the N-channel MOSFET Q8 is turned on, and the substrate PSUB is supplied with the ground potential VSS as an operating voltage. In this way, during normal operation, the control signal PDN is set to the high level, and the N-channel MOSFET constituting the CMOS circuit operates at high speed with a low threshold voltage.

When the control signal PDN is at a low level (VB
In the case of B), the CMOS inverter circuit IV1 is set to the high level, and the CMOS inverter circuit IV2 is set to the low level. Therefore, the P-channel MOSFET Q5 and the N-channel MO constituting the third CMOS switch
The SFET Q6 is turned on, and the control signal PDN also serving as the back bias voltage VBB is supplied to the substrate PSUB.
Are supplied. That is, the potential of the substrate PSUB is set to VBB with respect to the source S of the N-channel MOSFET to which the ground potential VSS of the circuit is supplied by the control signal PDN which is set to the potential VBB lower than the ground potential VSS as the operating voltage. To a low negative voltage like
A back bias voltage is supplied to the N-channel MOSFET.

Therefore, the gate G is connected to the ground potential VSS of the circuit.
Is supplied, when a leak current flowing between the power supply voltage VDD and the ground potential VSS of the circuit is measured, or in a standby state where the semiconductor integrated circuit device does not perform any operation, the gate voltage becomes like VSS. When the control signal PDN is at the low level, the control signal PDN is set to the low level corresponding to the negative potential.
On-state P-channel type MOSFE constituting an S circuit
The leakage current flowing through T and the off-state N-channel MOSFET is suppressed to a small current that can be regarded as zero. This makes it possible to determine a DC failure due to insulation failure, etc.
The low power consumption of the S circuit can be utilized.

In this embodiment, as described above, the above-mentioned switch circuit is constructed by using the unused cell area of the CMOS gate array. In general, a CMOS gate array uses only about half of the spread gates, so that an area where the switch circuit is provided can be easily obtained.
Then, a switch circuit is arranged using a part of the unused cell area, and a control signal line also serving as the back bias voltage is added to the switch circuit. CMOS in mote
Low power consumption of the circuit can be realized.

FIG. 4 is a circuit diagram showing another embodiment of the above switch circuit. In this embodiment, a switch for selectively supplying the operating voltage VDD and the back bias voltage VPP to a well region or a substrate in which a P-channel MOSFET is formed is a P-channel MOSFET.
The P-channel MOSFET Q3 is directly connected to a control signal PD.
Supply P. With this configuration, the number of elements can be reduced by half. That is, P-channel MOSFET
This is because VDD or a higher voltage VPP is supplied to the well region or the substrate where is formed, so that the above-described voltages can be supplied without level loss by using a P-channel MOSFET. The above configuration can also be applied to the embodiment of FIG. MOSFET for supplying circuit ground potential VSS or negative voltage VBB
For example, an N-channel MOSFET is used.

FIG. 5 is a block diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention. Each circuit block in the figure is drawn according to a geometrical arrangement on an actual semiconductor substrate. Each circuit block in the figure is formed on a semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique.

In the figure, 9 is a semiconductor chip,
10 is an internal circuit, and 11 is an internal voltage generation circuit VBB
G, VPPG, and is composed of an on-chip RAM composed of 12 and 13 and other logic circuit units.
The internal voltage generation circuits VBBG and VBBG include an oscillation circuit, and use a charge pump circuit to increase the boosted voltage VPP higher than the power supply voltage VDD and the negative voltage lower than the ground potential VSS of the circuit based on the power supply voltage VDD. VB
B is generated.

For example, when the power supply voltage VDD supplied from the external terminal is 3.3 V, the internal voltage supplied to the internal circuit operates at a step-down voltage such as 2.5 V formed by stepping down the power supply voltage VDD. When this is done, the internal voltage generation circuit VPPG is replaced with an internal step-down voltage generation circuit. Then, the back bias voltage VPP may use the external power supply voltage VDD as it is.

Although not particularly limited, the above-mentioned on-chip RA
M12 and M13 are configured by RAM macros. The area other than the RAM block in the area where the internal circuit 10 is formed is a spread gate area, and the respective functions are realized by the connection design. The MOSFETs are spread all over like the enlarged pattern 16 in this area. The switch circuit and the internal voltage generation circuit are formed by using elements not used as an internal circuit. A bonding pad 15 is provided around the semiconductor chip 9, and an input / output circuit unit 14 is provided between the bonding pad 15 and the internal circuit 10.
In the logic circuit portion, a circuit for realizing a function corresponding to each application is formed. When the voltage of the internal circuit is reduced, the input / output circuit section 14 is provided with a level conversion circuit for converting a signal level based on the reduced voltage to a level corresponding to the power supply voltage VDD.

When the internal voltage generating circuit is incorporated as described above, not only does a special power supply become unnecessary at the time of a test, but also no operation is performed when the internal power supply circuit is mounted on the system. The low power consumption mode can be set when there is no standby state.

As described above, the P-channel MOSFET and the N-channel MOSFET constituting the CMOS logic circuit
It is most desirable to supply a back bias voltage to each of the ETs during the DC test operation and the standby mode as described above in order to reduce the leak current. However, in a DC test, in a CMOS inverter circuit or a logic circuit connected to another stage, one is turned on and the other is turned off in response to an input signal. Each time, the N-channel MOSFET and the P-channel MOSFET are turned off. Therefore, for example, a P-channel MOSFET
A switch circuit may be added only to a well or a substrate in which is formed to supply the back bias voltage. In this case, it is possible to reduce half of the leak current due to the low threshold voltage that flows through the P-channel MOSFET, that is, half of the entire leak current.

The reason for reducing the leak current is that it is impossible to determine the presence or absence of a DC current due to the insulation failure between the power supply voltage and the ground potential of the circuit due to the variation. If the DC current due to insulation failure can be determined, the above P-channel type MO
The back bias voltage may be supplied only to the SFET or the N-channel MOSFET. The reduction in power consumption in the standby state can be expected to have a sufficient effect by halving the leak current.

The operation and effect obtained from the above embodiment are as follows. (1) A CMOS logic circuit composed of a P-channel MOSFET and an N-channel MOSFET, and the P-channel MOSFET or the N-channel MOSFET described above.
CMOS for the substrate or well region where
The operating voltage supplied to the source of one MOSFET of the logic circuit or the first MOS constituting the CMOS logic circuit
A switch circuit for selectively switching and supplying a back bias voltage to the FET is provided, and when the switching control signal is set to one level corresponding to the back bias voltage, the voltage is supplied to the substrate or the well region, By supplying the operating voltage to the substrate or the well region when the switching control signal is set to the other level corresponding to the ground potential of the circuit, the CMOS circuit operates in two modes while effectively using the wiring channel. The effect is obtained.

(2) The switching control signal is set to one level corresponding to the back bias voltage in a DC test mode of the semiconductor integrated circuit device or in a standby mode in which the semiconductor integrated circuit device does not operate. When the integrated circuit device performs a normal operation, the level is set to the other level corresponding to the ground potential of the circuit.
The effect that power consumption of the OS circuit can be reduced can be obtained.

(3) When applied to a CMOS gate array,
M constituting the first switch circuit and the second switch circuit
The use of an unused OSFET as a base makes it possible to achieve high integration and secure general versatility as a gate array.

(4) By forming the back bias voltage using a built-in charge pump circuit, the effect of reducing the load on the external power supply and improving the usability can be obtained.

The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, CM
The OS circuit may be a combination of circuit blocks in which each functional block is prepared in advance, such as a standard cell or a one-chip microcomputer, in addition to the gate array as described above. INDUSTRIAL APPLICABILITY The present invention can be widely used for a CMOS semiconductor integrated circuit device using a low threshold voltage MOSFET.

[0038]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, P-channel type MOSFE
A CMOS logic circuit comprising a T and an N-channel MOSFET, and an operating voltage supplied to a source of one MOSFET of the CMOS logic circuit with respect to a substrate or a well region where the P-channel MOSFET or the N-channel MOSFET is formed. Alternatively, a switch circuit for selectively switching and supplying a back bias voltage to the first MOSFET constituting the CMOS logic circuit is provided, and when the switching control signal is set to one level corresponding to the back bias voltage, the voltage is applied to the first MOSFET. By supplying the operating voltage to the substrate or the well region when the switching control signal is set to the other level corresponding to the ground potential of the circuit, the wiring channel is enabled. DC failure due to insulation failure, etc. It can reduce the power consumption of the CMOS circuit in Imoto.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a circuit diagram showing one embodiment of a switch circuit provided in the semiconductor integrated circuit device of FIG. 1;

FIG. 3 is a circuit diagram showing one embodiment of a switch circuit provided in the semiconductor integrated circuit device of FIG. 1;

FIG. 4 is a circuit diagram showing a modification of the switch circuit shown in FIG. 2;

FIG. 5 is a block diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention.

[Explanation of symbols]

Q1-Q8: MOSFET, IV1-IV4: CMOS
Inverter circuit, PWELL ... P-type well region, PSU
B: P-type substrate, 9: semiconductor chip, 10: internal circuit, 1
DESCRIPTION OF SYMBOLS 1 ... Internal voltage generation circuit, 12-13 ... RAM macro cell (on-chip RAM), 14 ... Input / output circuit, 15 ... Bonding pad, 16 ... Internal circuit (enlarged pattern).

Claims (4)

[Claims] 1. A first MOSFET of a second conductivity type formed in a substrate or well region of a first conductivity type, and a second MOSFET of a first conductivity type formed in a substrate or well region of a second conductivity type.
A CMOS logic circuit configured by combining an SFET and the CM for the substrate or well region of the first conductivity type;
A switch circuit for selectively switching and supplying a back bias voltage to one operating voltage supplied to the source of the first MOSFET of the OS logic circuit or to the first MOSFET constituting the CMOS logic circuit; When the control signal is set to one level corresponding to the back bias voltage, the voltage is supplied to the substrate or well region of the first conductivity type,
A semiconductor integrated circuit device for supplying the operating voltage to the first conductivity type substrate or well region when the switching control signal is set to the other level corresponding to the ground potential of the circuit. 2. The switch control signal according to claim 1, wherein the switching control signal has one level corresponding to the back bias voltage in a DC test mode of the semiconductor integrated circuit device or in a standby mode in which the semiconductor integrated circuit device does not operate. Wherein the semiconductor integrated circuit device is set to the other level corresponding to the ground potential of the circuit when the semiconductor integrated circuit device performs a normal operation. 3. The CMOS logic circuit according to claim 1, wherein the CMOS logic circuit is configured by the gate array, and the switch circuit is configured by an unused MOSFET built in the gate array. A semiconductor integrated circuit device. 4. The switch circuit according to claim 1, wherein the switch circuit includes a first switch circuit corresponding to a substrate or a well region of a first conductivity type on which the first MOSFET is formed. The second where the 2MOSFET is formed
A second switch circuit corresponding to a conductive type substrate or a well region, wherein the switching control signal includes the first switch circuit and the second switch circuit;
A semiconductor integrated circuit device having a voltage level corresponding to a back bias voltage provided by a switch circuit.