JP4428514B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and is effectively used for, for example, a system LSI (Large Scale Integrated Circuit) in which a plurality of functional modules are divided into circuit blocks and a power supply voltage is supplied to each independently. Technology.

The existence of Japanese Patent Application Laid-Open No. 2003-218682, in which a plurality of functional modules are incorporated in a semiconductor integrated circuit, and Japanese Patent Application Laid-Open No. 11-008306, in which a ring-shaped power source is connected by a macro cell based on a survey of known examples after the present invention has been made. Was reported. However, these patent documents do not describe any technical problems to be solved by the present invention as will be described later.
JP 2003-218682 A JP-A-11-008306

  In a CMOS circuit formed by combining a P-channel MOSFET and an N-channel MOSFET, one of the MOSFETs is turned off when the input signal does not change, so that no DC current flows theoretically, resulting in low power consumption. It has the characteristics. However, as device miniaturization progresses, the leakage current flowing through the MOSFET in the off state cannot be ignored. In particular, since a large number of elements are formed in a large-scale integrated circuit, a large leak current flows when viewed as a semiconductor integrated circuit device.

  In view of this, a block was divided for each functional module in the LSI, and a power supply system suitable for each function was studied. In a circuit that does not affect the circuit operation when the power is turned on again, such as ROM, if the power supply voltage is cut off in the standby mode as described in Patent Document 1, the leakage current is also reduced. Eliminating power consumption can be reduced. On the other hand, in the case of having a storage circuit such as a register, the power supply voltage cannot be cut off in order to hold the storage information of the register or the like even in the standby mode where no operation is performed. Therefore, it was considered that the bias voltage is supplied to the back gate of the MOSFET to increase the effective threshold voltage, and the on / off state of the MOSFET is maintained as it is while greatly reducing the leakage current.

  Even in a circuit that does not have a problem in circuit operation even if the power is cut off, such as the ROM, in a circuit that requires a short start-up time from power-on until it becomes operable, the power supply voltage is cut off. It is convenient to provide a standby mode in which a bias voltage is supplied to the back gate and a standby mode in which a half-operation state is established. It has also been found that such a mode for supplying a back bias is effective in reducing the leakage current in order to perform a DC test with high accuracy. When a plurality of functional modules having different power specifications are configured in a semiconductor integrated circuit device as described above, it is necessary to design and lay out the power circuit for each functional module. Mistakes increase and design efficiency decreases. In addition, power supply wiring in the case of using a copper wiring layer in a semiconductor integrated circuit was also examined.

  An object of the present invention is to provide a semiconductor integrated circuit device in which design efficiency is improved while achieving high functionality including reduction in power source impedance. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a power supply main line that transmits a power supply voltage and a ground potential transmitted to an internal circuit using a bonding pad made of aluminum and an aluminum layer formed in the same process as the bonding pad is configured. A plurality of copper wiring layers arranged in the lower layer of the power source are connected between the power supply trunk line and the semiconductor region constituting the corresponding internal circuit.

  By using a low-resistance aluminum pad wiring as a power supply trunk line, the power supply impedance can be reduced. In addition, the power supply circuit can be shared for internal circuits that require low power consumption and restart in a short time while maintaining operation at the bag gate while maintaining power consumption by shutting off the power using such a power trunk line. The power supply circuit can also be applied to high-accuracy DC tests in functional blocks.

  FIG. 1 is a schematic layout diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention. In the figure, a layout centering on a power supply line formed in the semiconductor integrated circuit device according to the present invention is shown. The power supply line is a pair of a power supply voltage line and a circuit ground line, and a diagonal line is attached to the ground line side to make the wiring layout easy to understand.

  The semiconductor integrated circuit device of this embodiment is operated by two kinds of power supply voltages vcc and vdd. Although not particularly limited, the power supply voltage vcc is a relatively high voltage such as 3.3V, and the power supply voltage vdd is a low voltage such as 1.2V. The relatively high power supply voltage vcc is provided with an analog / logical power supply voltage vccaa, an input / output circuit power supply voltage vccq, and an internal circuit power supply voltage vcci. Circuit ground potentials vssaa, vssq, vssi are provided corresponding to the power supply voltages vccaa, vccq, vcci, respectively. A power supply line indicated by a thick wiring along the outer periphery of the semiconductor chip is divided into two parts for an analog circuit and a digital circuit, and the power supply voltages vccaa and vccq are arranged on the outside, and the circuit ground is inside each of them. Lines vssas and vssq are arranged. As the internal circuit having a specific circuit function as the vcc system circuit, there are a vcc system logic and an analog logic, and a power supply line shown by a thin wiring is provided so as to surround each of them. A power supply line surrounding the vcc logic is connected to power pads vcci and vssi. A power supply line surrounding the analog logic is connected to power pads (PAD) vccaa and vssaa together with the thick power supply line.

  The power supply lines vdd and vss are provided as a thin line in a ring along the inside of the power supply line indicated by the thick line and a line corresponding to an internal circuit described later. The ring-shaped vdd power supply line is provided with an operating voltage of a level conversion circuit that converts a vdd internal signal into a large amplitude signal such as the vcc system at an input / output interface, and an internal vdd system that operates constantly. It is used as an operating voltage of a circuit such as a micro io that exchanges signals with the vdd logic 1, the vdd logic 2, and the vcc logic. As internal circuits that operate in the vdd system, a vdd system logic 1 and a vdd system logic 2 are provided. A power supply line indicated by a thin wiring is provided so as to surround these circuit blocks. The vdd logic 2 is provided with independent power supply pads (PADs) such as vdddi and vssi for noise separation from the vdd logic 1 and the internal circuit operating with the annular power supply line.

  Corresponding to the power supply lines, a plurality of sets of power supply pads (PAD) vcc and vss, vdd and vss, vccq and vssq, and vccaa and vssaa are provided as necessary. As other pads (PADs) exemplarily shown as representatives, aio is for inputting / outputting analog signals, vdd-related dio is for performing digital input / output, and the vdd-related logic 1 The signal is directly input / output from / to the vdd logic 2. The vcc input / output pads are omitted in FIG. The square blocks shown corresponding to the pads constitute an input / output interface circuit. The signal input / output pads corresponding to the input / output interface are exemplarily shown as representative pads such as pads dio and aio. In particular, a large number of digital input / output pads are provided so as to surround the outer periphery of the semiconductor chip along with the power supply pads.

  In this embodiment, the internal circuit block of the vdd system logic 1 and the vdd system logic 2 is provided with a function to enter a low power consumption mode when no operation is performed even when the power is turned on. In order to realize this low power consumption mode, a power switch PSW is provided below the power supply line formed so as to surround the internal circuit, and at the corner (corner) of the power supply line below the power supply line. A power switch control circuit PSWC is arranged. Further, for the purpose of lowering the impedance of the power supply line as will be described later, each power supply main line (vcc and vss, vdd and vss, vccq and vssq, vccaa and vssaa) formed so as to surround the corresponding circuit. ) Is formed of a relatively thick aluminum pad wiring ALP formed in the same process as the bonding pad.

  FIG. 2 shows a layout diagram of an embodiment of a power supply line corresponding to the vdd logic 2 of FIG. In this embodiment, the power supply line is constituted by a cell system. The type of cell is not particularly limited, but can be roughly divided into four types A to D. According to the direction of letters A to D in the drawing, the cell C constitutes a power supply line extending in the vertical direction. The cell B constitutes a power supply line extending in the horizontal direction. The cell A constitutes a power supply line at a corner portion that connects the vertical and horizontal power supply lines. The cell B is not particularly limited, but a standard cell and a small cell B for length adjustment are provided.

  The cell E constitutes a power supply line that extends in the vertical direction above the vdd logic 2 and connects the cells B facing each other. The cell E is used to configure a power mesh described later. The cell D is an internal connection cell, which extends in the horizontal direction from the power supply line extending in the vertical direction and is used for connection to the internal power supply line of the internal circuit. Among the cells A to E, circuit elements constituting the power switch element and the power switch control circuit are disposed below the cells A, B, and C. On the other hand, the cell E has only a power supply line. The cell D is provided with a lower layer wiring connected to the internal power supply line.

  FIG. 3 shows a schematic layout diagram of an embodiment of the lower part of the power supply line corresponding to the vdd system logic 1 of FIG. In this embodiment, the relationship between the cell C and the cell A is mainly shown as an example. The cell C is provided with a switch. Although this switch is not particularly limited, one of the power supply voltages vddi and vssi provided at the upper end is connected to the circuit ground line vssi, and the other end is connected to the ground line for supplying the circuit ground potential to the internal logic region. Connected to. Although not particularly limited, the internal logic region has a well region in which a P-channel MOSFET and an N-channel MOSFET that form a CMOS logic circuit are formed in a horizontally long shape, such as a gate air, as will be described later. A corresponding switch is provided along. A ground line vss of the internal circuit is disposed laterally along the P-type well where the N-channel MOSFET is formed. On the other hand, the power supply line vdd is arranged in the lateral direction along the N-type well region where the P-channel MOSFET is formed. In the figure, a block that divides an internal logic region into a vertical product corresponds to a circuit region in which the N-channel MOSFET and the P-channel MOSFET are formed.

  The cell A arranged in the upper left corner is provided with a power SW controller (power switch control circuit PSWC) for controlling on / off of the switch provided in the cell C. The switch control signal formed by the power supply SW controller is transmitted to each switch through the power supply SW control signal line as shown by the dotted line in FIG. In the figure, a power supply SW control signal line for controlling a power supply SW (switch) provided in a cell C arranged on the left side of the internal logic area is connected to each cell C using a wiring area provided in the cell C. To the switch.

  The power supply SW control signal lines for controlling the power supply SW provided in the cell C arranged on the right side of the internal logic area are a wiring area provided in the cell B arranged in the horizontal direction and a wiring area provided in the cell A. Is transmitted to the switch of the cell C arranged on the right side. Since the switch is used for power supply control of the internal circuit as described above, it is not necessary to provide such a switch at the corner. Therefore, by arranging the power SW controller (power switch control circuit PSWC) as described above, the circuit formation region in the lower part of the power supply line is effectively used.

  FIG. 4 shows a circuit diagram of an embodiment for explaining the relationship between the power SW controller (PSWC) of FIG. 3, the power SW and the internal logic. The inverter circuit shown as a circuit representing the internal logic operates at an operating voltage transmitted through the power supply line vdd and the internal ground line vssm. The power supply voltage vdd of the internal logic is steadily transmitted with the power supply voltage supplied from the external terminal through the pad and the wiring path as described above. The internal ground line vssm is connected to a ground line vss formed so as to surround the internal circuit through N-channel MOSFETs Q1 and Q2 as power sources SW (switches) shown as representative examples. A power supply SW control signal is commonly supplied to the gates g of the MOSFETs as a plurality of switches provided corresponding to the cell C as described above.

  The power SW controller (PSWC) generates switch control signals for the MOSFETs Q1, Q2, etc. in response to the control signal req. In the internal logic, when the MOSFETs Q1 and Q2 are switched from the OFF state to the ON state at high speed, current flows all at once in response to the input signal being indefinite in the inverter circuit or logic gate circuit of the internal logic. A large noise is generated in the voltage vdd or the ground potential vss of the circuit, or a large current supply is instantaneously applied to the power supply device of the system. Therefore, in this embodiment, the MOSFETs Q1, Q2, etc. are provided by the two drive circuits C1drv and C2drv, the output circuits C1 and C2 that generate output signals thereby, and the determination circuit C3 that determines the level of the power supply SW control signal and the timer circuit Timer. The power SW control signal is generated so as to drive in two stages.

  When a power-on operation is instructed by the control signal req, the drive circuit C1drv responds to this and raises the gate voltages of the MOSFETs Q1 and Q2 as the power switches through the output circuit C1. The output circuit C1 is formed of a MOSFET having a small current supply capability, and the level of the power supply SW control signal line having a large load capacity by connecting the gates g of the MOSFETs Q1, Q2, etc. as a large number of power switches. Get up gradually. As a result, the MOSFETs Q1, Q2, etc. as power switches are controlled so that a relatively small current flows when the gate voltage exceeds the threshold voltage. Limiting the current due to the input signal being indefinite in a logic gate circuit or the like to generate a large noise in the power supply voltage vdd or the circuit ground potential vss, or causing a large current supply in the power supply device instantaneously. Prevent stripping. Note that the occurrence of noise is thought to adversely affect other operating logic circuits, interface circuits, analog circuits, etc., so shut off the power when no operation is performed on some circuits. This is a problem that must be taken into account when providing a function for the low power consumption mode.

  The timer circuit Timer operates the output circuit C2 via the drive circuit C2drv when the level of the power supply SW control signal line exceeds a certain level by the voltage determination circuit C3 having hysteresis characteristics. The output circuit 2 is formed of a MOSFET having a large current supply capability, and raises the gates g of the MOSFETs Q1, Q2, etc. as a large number of power switches to the power supply voltage vdd at high speed. As a result, the internal logic of the vdd system is brought into an operating state. The timer circuit Timer outputs a signal ack indicating that the operation of the internal logic is effective with a delay time, and notifies other circuits. The signal cds / cdr is a signal for controlling the micro io, and is used to limit the signal output transmitted to the micro io, for example, until the internal logic signal is validated.

  FIG. 5 is a schematic layout diagram of an embodiment of the cell C. In the figure, the uppermost power supply line and the element formation portion provided below the uppermost power supply line are shown side by side. The figure (lower) shows the uppermost power supply line, where vdd and vss are provided as a pair. Although not particularly limited, in this embodiment, the power supply lines vdd and vss are formed of an aluminum layer (ALP) formed in the same process as the bonding pad and having a relatively thick thickness. The core side is the internal logic area side, and the pad metal wiring on the core side is changed according to the potentials vdd, vss, vssm to be connected.

  The figure (upper) is an element formation portion, and a plurality of gate electrodes extending in the horizontal direction are arranged in the vertical direction. Diffusion layers constituting the source and drain are formed so as to sandwich the gate electrode. The diffusion layer sandwiched between the two gate electrodes serves as a common source or drain of the MOSFET having the two gate electrodes, and every other source and drain are alternately disposed across the gate. On the I / O side (right side), every other diffusion layer is made common, used as a source, and connected to the power supply line vss. On the core side, every other diffusion layer different from the above is made common and used as the drain and connected to the vssm metal wiring which is the ground line of the internal logic circuit. A plurality of wiring layers extending in the vertical direction are provided on the right side in the cell frame, and are used as wiring between the corner control circuits and wiring for transmitting a power SW control signal.

  FIG. 6 shows a schematic layout diagram of an embodiment of the lower part of the power supply line corresponding to the vdd system logic 1 of FIG. In this embodiment, the relationship between the cell B and the cell A is mainly shown as an example. Cell B is provided with two switches. One switch is connected to the power supply voltage vddi provided on the upper side, and the other switch is coupled to the N-type well provided in the internal logic region. Connected to the bias voltage line vbp. One end of the other switch is connected to a ground line vssi provided on the upper side, and the other end is connected to a bias voltage line vbn coupled to a P-type well provided in the internal logic region. Instead of this configuration, two switches may be formed like the cell C, and the two cells B may be used to connect to the bias voltage lines vbp and vbn.

  The slave switches provided in these B cells selectively apply bias voltages vddi and vssi during normal operation to the N-type well in which the P-channel MOSFET of the CMOS circuit is formed and the P-type well in which the N-channel MOSFET is formed. Supply. As described above, since the P-type well and the N-type well are alternately arranged in the horizontal direction, the bias voltage lines vbp and vbn through the switch are connected to the power supply line of the cell E shown in FIG. Then, the bias voltage is supplied to the P-type well and the N-type well extended in the vertical direction. A master switch and a control circuit are provided in the three cells A shown in FIG.

  FIG. 7 shows a circuit diagram of an embodiment of the master switch, the control circuit and the slave switch provided in the cell A. When the internal logic does not perform any operation, the master switch does not shut off the power to the CMOS circuit of the internal logic like the cell C, and maintains low power consumption while maintaining the operation as the CMOS circuit. A P-channel MOSFET Q5 for supplying a back bias voltage vbgp (vddi + Δv) boosted higher than the power supply voltage vddi to the bias voltage line vbp coupled to the N-type well, and a bias coupled to the P-type well The voltage line vbn includes an N-channel MOSFET Q6 that supplies a negative back bias voltage vbgn (vss−Δv) lower than the circuit ground potential vssi. During such low power consumption operation, the P-channel MOSFET Q3 and the N-channel MOSFET Q4 constituting the slave switch provided in the cell B are turned off.

  In the cell A, in addition to the MOSFETs Q5 and Q6 constituting the master switch, drive circuits DV1 to DV6 for forming control signals are provided. On the one hand, the power down signal PDM is transmitted through the series circuit of the drive circuits DV1-DV2-DV3, the output signal of the drive circuit DV2 is transmitted to the gate of the P-channel MOSFET Q5, the switch control is performed, and the output of the drive circuit DV3 A signal is transmitted to the gate of the MOSFET Q3 to perform switch control. These drive circuits DV1, DV2 and DV3 operate at the boosted voltage vbgp and the circuit ground potential vss (0V), and the output signals thereof are vbgp / 0V, 0V / vbgp and vbgp / 0V, respectively. As a result, the P-channel MOSFETs Q5 and Q3 can be complementarily turned on / off so that the boosted voltages vbgp and vdd are switched according to the power-down signal PDM.

  On the other hand, the power-down signal PDM is transmitted through the series circuit of the drive circuits DV4-DV5-DV6, and the output signal of the drive circuit DV5 is transmitted to the gate of the N-channel MOSFET Q6 to perform switch control. An output signal is transmitted to the gate of the MOSFET Q4 to perform switch control. These drive circuits DV4, DV5 and DV6 operate with a power supply voltage vdd and a negative voltage vbgn (−ΔV), and output signals thereof are vbgn / vdd, vdd / vbgn and vbgn / vdd. Thus, the N-channel MOSFETs Q6 and Q4 can be complementarily turned on / off so as to switch the negative voltage vbgn and the circuit ground potential vss in accordance with the power-down signal PDM.

  When the power down signal PDM is at a low level (0V), the drive circuit DV1 outputs 0V as described above, and the drive circuit DV4 outputs vdd as described above. As a result, the output signals of the drive circuits DV2 and DV5 turn off the MOSFETs Q5 and Q6 as the master switches, and the output signals of the drive circuits DV3 and DV6 turn on the MOSFETs Q3 and Q4 as the slave switches, A bias voltage such as vdd is supplied to the N-type well where the logic P-channel MOSFET is formed, and a bias voltage such as vss is supplied to the P-type well where the N-channel MOSFET is formed. As a result, the threshold voltage between the P-channel MOSFET and the N-channel MOSFET of the internal logic is reduced, and high-speed operation is performed.

  When the power down signal PDM is at the high level (vdd), the drive circuit DV1 outputs vbgp as described above, and the drive circuit DV4 outputs the negative voltage vbgn as described above. Thereby, the output signals of the drive circuits DV2 and DV5 turn on the MOSFETs Q5 and Q6 as the master switches, and the output signals of the drive circuits DV3 and DV6 turn off the MOSFETs Q3 and Q4 as the slave switches, A bias voltage such as vbgp is supplied to the N-type well where the logic P-channel MOSFET is formed, and a bias voltage such as vbgn is supplied to the P-type well where the N-channel MOSFET is formed. As a result, the threshold voltage of the P-channel MOSFET and N-channel MOSFET of the internal logic is increased, and leakage (subthreshold leakage) flowing through the P-channel MOSFET or N-channel MOSFET in the off state is limited.

  FIG. 8 shows a schematic layout of another embodiment of the lower portion of the power supply line corresponding to the vdd system logic 1 of FIG. This embodiment is a modification of FIG. 3 and mainly shows the cell C as an example. In the cell C, the cell provided with the switch and the cell C provided with a capacitor element as representatively shown in FIG. As shown in the equivalent circuit diagram of FIG. 9, this capacitor is provided between the power supply voltage line of the internal logic and the ground line of the circuit so as to perform the power supply stabilization operation. As described above, the switch provided in the cell C is provided corresponding to the ground line vssm of the circuit of the internal logic. Therefore, the switch is assembled corresponding to the ground line vssm, and the cell C is disposed. The cell C in which the capacitor element is incorporated is disposed. As a result, the element formation region below the power supply line extending in the vertical direction of the internal logic can be effectively used.

  FIG. 10 shows a schematic layout of another embodiment of the lower part of the power supply line corresponding to the vdd logic 1 of FIG. This embodiment is a modification of FIG. 6 and mainly shows the cell B as an example. In the cell B, a cell provided with the switch and a cell B provided with a capacitor as shown as a representative example in FIG. As shown in the equivalent circuit diagram of FIG. 9, this capacitor is provided between the power supply voltage line of the internal logic and the ground line of the circuit so as to perform the power supply stabilization operation. As described above, the switch provided in the cell B is provided corresponding to the substrate bias lines vbp and vbn of the internal logic. Therefore, the switch is assembled corresponding to the substrate bias lines vbp and vbn, and the cell B is arranged. Otherwise, the cell B in which the capacitor element is incorporated is disposed. As a result, the element formation region under the power supply line extending in the lateral direction of the internal logic can be effectively used. Although not shown in the figure, a switch and a capacitor are appropriately provided in the cell C arranged in the vertical direction as in FIG.

  FIG. 11 shows a circuit diagram of an embodiment corresponding to the embodiment of FIG. The circuit diagram of this embodiment includes a switch for shutting off the power supply of the internal logic as shown in FIG. 4 and its control circuit, and a switch for switching the substrate bias voltage applied to the internal logic as shown in FIG. The relationship between the control circuit and internal logic is shown. As described with reference to FIG. 4, the internal logic of this embodiment includes an operation for cutting power and reducing power consumption when no operation is performed by the internal logic, and referring to FIG. As described above, the operation of the CMOS circuit is maintained, and the operation of reducing the leakage current and reducing the power consumption is performed.

  As described with reference to FIG. 7, the operation of reducing the leakage current and reducing the power consumption while maintaining the operation of the CMOS circuit is effective when the internal logic has a storage circuit such as a register. . On the other hand, as described with reference to FIG. 4, the operation for shutting down the power and reducing the power consumption when the internal logic does not perform any operation needs to maintain the state before the power is shut off. This is effective when there is no logic circuit. However, even in the case of a logic circuit that does not need to maintain the state before the power supply is cut off, the master switch and the slave switch are provided as in this embodiment, and the substrate bias voltage applied to the internal logic as described above is provided. It is effective to reduce the leakage current of the MOSFET by switching the following.

  In a semiconductor integrated circuit device, there is a test item for performing a direct current test by turning on the power. In this test item, it is possible to detect a short circuit between a power supply line and a ground line that are complicatedly wired in the internal logic. However, due to the miniaturization of elements and the lower threshold voltage, the leakage current flowing through the MOSFET in the off state increases, and in a semiconductor integrated circuit device in which a large number of elements are formed as in a system LSI, the leakage current is large. Therefore, it becomes difficult to detect a DC fault current that flows due to a short circuit between the power supply line and the ground line.

  For this DC test, it is possible to effectively use an operation mode in which the substrate bias voltage applied to the internal logic is switched to reduce the leakage current of the MOSFET. That is, by supplying a substrate back bias that increases the threshold voltage of the MOSFET to the substrate as described above, the leakage current can be greatly reduced, so that the gap between the power line and the ground line can be reduced. This makes it easy to detect a defective DC current that flows due to a short circuit. Further, since the CMOS circuit is in an operating state, a DC failure between the signal transmission path and the power supply line or the ground line can be found by operating the internal logic at a low operating frequency.

  The cells A to C described above have been described by taking the vdd logic 1 of FIG. 1 as an example, but can be similarly applied to the cell cells A to C of the vdd logic 2 shown in FIG. As in the embodiment of FIG. 2, when the internal logic region is partially missing, six cells A are provided. For this reason, in the embodiment of FIG. 2, two or three cells A having the power SW controller as in the embodiment of FIG. 4 may be provided as the cell A.

  FIG. 12 shows a schematic configuration diagram of an embodiment of a well region corresponding to the vdd logic 2 of FIG. In the figure, the layout is shown on the upper side, and the corresponding cross-sectional structure is shown on the lower side. Below the power supply line corresponding to the vdd system logic 2 is formed from a well region having a deep depth for electrically isolating an element formation region (well region) for forming the switch MOSFET and the capacitor from the semiconductor substrate. An isolation region NISO is provided. For example, when the semiconductor substrate is made of P-type (P-SUB), the isolation region NISO is made of N-type. In the isolation region NISO, an N-type well region for forming a P-channel MOSFET is formed, and a P-type well region for forming an N-channel MOSFET is formed.

  Along with the power supply line extending in the vertical direction of the vdd logic 2, the N-channel MOSFETs Q1, Q2, etc. are provided as in the power switch of FIG. 11, so that a P-type well region is provided. On the other hand, the P-channel MOSFET Q3 and the N-channel MOSFET Q4 are provided along the power supply line extending in the lateral direction as in the slave switch of FIG. An N-type well region and a P-type well region formed as described above are provided. Also in the internal logic portion, N-type well regions and P-type well regions extending in the lateral direction are alternately arranged so as to form a CMOS circuit. At the corner of the vdd logic 2, the N-type well region and the P-type well region provided along the power supply line extending in the lateral direction extend as they are, and the P channel constituting the cell A is formed. MOSFETs and N-channel MOSFETs are formed.

  FIG. 13 is a circuit diagram for explaining the relationship between the internal logic portion of FIG. 12, the MOSFET of the power switch portion, and the well region. The P-channel MOSFET in the internal logic portion is formed in the N-type well NWELL and operates with a low power supply voltage vdd, and thus is composed of a thin film MOS. Here, the thin film MOS means that the gate insulating film is formed thin and has a low breakdown voltage (low threshold voltage). The N-channel MOSFET in the internal logic part is formed in the P-type well PWELL and operates with the low power supply voltage vdd, so that it is composed of a thin film MOS as described above. On the other hand, the power switch MOSFET Q1 is formed in the P-type well region PWELL extending in the vertical direction, and is formed of a thick film MOS in order to reduce leakage current. Here, the thick film MOS means that the gate insulating film is formed thick and has a high threshold voltage (high withstand voltage). Thereby, the leakage current flowing between the drain and the source when the MOSFET Q1 is turned off is reduced, and the power consumption can be reduced.

  FIG. 14 is a schematic layout diagram showing one embodiment of the power supply line of the semiconductor integrated circuit device according to the present invention. This figure shows the relationship between bonding pads PAD provided along the outer periphery of the semiconductor chip and power supply lines formed in the semiconductor integrated circuit device. The bonding pad PAD is composed of a relatively thick aluminum layer for bonding a wire made of a gold wire as shown in FIG. Between the bonding pad row and the internal circuit formation region, a power supply voltage line vdd and a circuit ground line vss are arranged side by side with an I / O ring interposed therebetween. In this embodiment, the power supply voltage line vdd and the ground line vss are formed by using the relatively thick aluminum layer ALP formed in the same manufacturing process as the bonding pad PAD.

  The power supply voltage line vdd is provided with a plurality of power supply lines extending in the lateral direction so as to cross the internal logic portion using the relatively thick aluminum layer ALP. Further, in the vertical direction, power supply lines made of a copper layer formed below the aluminum layer extend, and are connected to each other at the intersection to form a mesh on the internal logic unit. The ground line is provided by extending the ground line vssm in the lateral direction in the internal logic portion, and is composed of a relatively thick aluminum layer as described above. At both ends thereof, the power switch MOSFET Q1 is connected. In the figure, the connecting portion is omitted. Also in the ground line vssm, power supply lines made of a copper layer formed in a lower layer extend in the vertical direction, and are connected to each other at the intersection to form a mesh on the internal logic unit. Below the power supply lines vdd and vss formed so as to surround the internal logic unit, as described above, the power SW controller, power switch, slave switch, main switch for performing power supply control as shown in FIG. And its control circuit is provided as necessary. The ground line vss provided in the internal logic portion in parallel with the ground line vssm is, for example, for P-type well well power supply. The ground line vss may be omitted, and the well and source of the N-channel MOSFET may be connected to the ground line vssm.

  FIG. 15 shows an equivalent circuit diagram of the power supply line of FIG. This figure shows the power supply voltage vdd as an example. Among the mesh-like power supply lines as described above, the power supply lines extending in the lateral direction are formed using the relatively thick aluminum layer (ALP), and therefore, the figure is marked with a circle. The resistance value of the distributed resistance can be reduced. On the other hand, since the power supply line extending in the vertical direction is formed of the thin copper layer, the resistance value of the distributed resistance is larger than that of the thick aluminum layer. In other words, compared to the case where the power supply line is formed of a copper layer as in the prior art, the resistance value of the distributed resistance in the power supply line extended in the lateral direction is small, so that the internal logic flows during its operation. Power supply variation due to current can be suppressed.

  From another viewpoint, this can reduce one wiring layer required for the internal logic. That is, when the power supply line vdd is similarly formed in a mesh shape, it is necessary to use the copper layer for two layers in the vertical direction and the horizontal direction, but the above manufacturing process is the same as the bonding pad. By using a relatively thick aluminum layer, one layer of copper layer wiring can be omitted, and the manufacturing process can be simplified.

  FIG. 16 is a schematic structural perspective view of an embodiment of the power supply line in the semiconductor integrated circuit device according to the present invention. This figure three-dimensionally represents the relationship between a power supply bonding pad (AL pad) and an internal power supply line connected thereto. For this reason, an insulating film or the like between the wiring layers is omitted, and the wiring layer and the contact portion that interconnects the wiring layers are exemplarily shown. A bonding pad made of an aluminum layer having a relatively thick thickness is connected to a wiring made of a lower copper layer through a contact portion and extends to an internal circuit. This configuration is for avoiding an input circuit and a power supply line along the outer periphery as in the semiconductor integrated circuit device shown in FIG.

  The power supply main line ALP corresponding to the internal logic part is connected by a contact through a copper layer made of the relatively thick aluminum layer formed in the same manufacturing process as the bonding pad and extending toward the internal circuit. . In the figure, a power supply voltage line vdd is exemplarily shown as the power supply trunk line. The power supply main line (ALP) is connected to an N-type well region NW in which, for example, a P-channel MOSFET is formed, via a wiring and a contact made of a copper layer thereunder. The bonding pad vss for grounding is also connected to a wiring made of a lower copper layer via a contact portion and extends to an internal circuit, and on the other hand, is connected to a power supply trunk for grounding made of the relatively thick aluminum layer. On the other hand, it is connected to a P-type well region PW in which, for example, an N-channel MOSFET is formed, via a wiring or contact made of a similar lower copper layer. The power supply main line may be configured in the mesh shape by power supply wiring made of a copper layer provided below the power supply main line.

  FIG. 17 is a schematic cross-sectional view of an embodiment of the power supply voltage line in the semiconductor integrated circuit device according to the present invention. In the figure, the supply path of the power supply voltage vdd is exemplarily shown as a representative. As described in FIG. 16, the bonding pad made of thick aluminum or the like is connected to the wiring layer made of the lower copper layer, and on the other hand, the power supply main line ALP made of aluminum or the like formed in the upper layer is connected to the power supply main line ALP made of aluminum or the like. It is connected via a contact, and on the other hand, it is connected via a wiring layer provided in a lower layer and an N-type well region NW where a P-channel MOSFET is formed via a contact. In this configuration, the wiring composed of the lower copper layer and the power supply trunk line composed of the upper aluminum layer are in parallel. As a result, the current necessary for the operation of the internal logic flows in a distributed manner in the two power supply paths, and particularly flows largely on the main line side, so that the impedance as the power supply line can be kept low. For this reason, it is possible to suppress variations and fluctuations in the power supply voltage in individual logic circuits during operation of the internal logic. When the internal logic operates at a low voltage (or lower) such as 1.2V, variations and fluctuations in the power supply voltage have a great influence on the circuit operation. Therefore, stable operation of the internal logic circuit is expected by this embodiment. it can.

  FIG. 18 is a schematic cross-sectional view of another embodiment of the power supply voltage line in the semiconductor integrated circuit device according to the present invention. In the figure, the supply path of the ground potential vss is exemplarily shown as a representative. Similarly to the ground line vss described with reference to FIG. 17, the bonding pad made of thick aluminum or the like is connected to the wiring layer made of the lower copper layer, and on the other hand, from the aluminum or the like formed in the upper layer. The power supply main line ALP is connected via a contact, and on the other hand, is connected to a P-type well region PW where an N-channel MOSFET is formed via a wiring layer and a contact provided in the lower layer. With this configuration, the impedance as the ground wire can be kept low as described above. For this reason, it is possible to suppress variations and fluctuations in the ground potential in individual logic circuits during operation of the internal logic. When the internal logic operates at a low voltage (or lower) such as 1.2V, variations and fluctuations in the ground potential have a great influence on the circuit operation. Therefore, stable operation of the internal logic circuit is expected by this embodiment. it can.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, only a master switch and a slave switch are provided for all circuits in a semiconductor integrated circuit device as shown in FIG. 7, and threshold values are set for all P-channel MOSFETs and N-channel MOSFETs only during the DC test as described above. The back bias voltage may be switched to increase the voltage. Also in this case, the mask switch and the slave switch as described above are provided below the power supply line provided along the outer periphery of the chip. Since the power switch is not necessary, an oscillation circuit, a charge pump circuit, and a control circuit for forming back bias voltages vbp and vbn may be provided in that portion. The present invention can be widely used in semiconductor integrated circuit devices such as microcomputers and system LSIs.

1 is a schematic layout diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention. FIG. 2 is a layout diagram illustrating an example of a power supply line corresponding to the vdd system logic 2 of FIG. 1. FIG. 2 is a schematic layout diagram showing an embodiment of a lower portion of a power supply line corresponding to the vdd system logic 1 of FIG. 1. FIG. 4 is a circuit diagram of an embodiment for explaining the relationship between the power SW controller (PSWC) of FIG. 3, the power SW, and internal logic. FIG. 3 is a schematic layout diagram of an embodiment of the cell C in FIG. 2. FIG. 2 is a schematic layout diagram showing an embodiment of a lower portion of a power supply line corresponding to the vdd system logic 1 of FIG. 1. FIG. 3 is a circuit diagram illustrating an embodiment of a master switch, a control circuit, and the slave switch provided in the cell A of FIG. 2. FIG. 10 is a schematic layout diagram showing another embodiment of the lower portion of the power supply line corresponding to the vdd system logic 1 of FIG. 1. FIG. 9 is an equivalent circuit diagram corresponding to FIG. 8. FIG. 10 is a schematic layout diagram showing another embodiment of the lower portion of the power supply line corresponding to the vdd system logic 1 of FIG. 1. It is a circuit diagram which shows one Example corresponding to the Example of FIG. FIG. 3 is a schematic configuration diagram showing an example of a well region corresponding to the vdd system logic 2 of FIG. 2. FIG. 13 is a circuit diagram showing the relationship between the internal logic part of FIG. 12 and the MOSFET and well region of the power switch part. 1 is a schematic layout diagram showing one embodiment of a power supply line of a semiconductor integrated circuit device according to the present invention. FIG. 15 is an equivalent circuit diagram of the power supply line of FIG. 14. 1 is a schematic structural perspective view showing one embodiment of a power supply line in a semiconductor integrated circuit device according to the present invention. 1 is a schematic cross-sectional view showing an embodiment of a power supply voltage line in a semiconductor integrated circuit device according to the present invention. It is a schematic structure sectional view showing another embodiment of the power supply voltage line in the semiconductor integrated circuit device according to the present invention.

Explanation of symbols

ALP ... Power supply trunk line, A to D ... Cell, C1drv, C2drv ... Drive circuit, Timer ... Timer circuit, C1, C2 ... Output circuit, C3 ... Voltage judgment circuit, PSWC ... Power switch controller, Q1-Q13 ... MOSFET, DV1 DV6: drive circuit, PW: P-type well region, NW: N-type well region, NISO: element isolation region (deep well), P-SUB: semiconductor substrate.

Claims (6)

A bonding pad made of aluminum;
A power supply main line that transmits a power supply voltage transmitted to an internal circuit and a ground potential, and includes an aluminum layer formed in the same process as the bonding pad.
A plurality of wiring layers made of a copper wiring layer disposed below the power supply trunk line and connecting between the power supply trunk line and a semiconductor region constituting the corresponding internal circuit;
The power trunk line
A first power supply line including a power supply voltage line extending in parallel with the first direction and a circuit ground line; and disposed on a lower layer including the semiconductor substrate of the first power supply line. A first cell including a first switch element provided between the ground line and a corresponding power supply line of the internal circuit;
A second power supply line including a power supply voltage line extending in parallel with a second direction orthogonal to the first direction and a circuit ground line, and disposed in a lower layer including the semiconductor substrate of the second power supply line; The second switch element provided between the first bias wiring connected to the first well region where the first conductivity type MOSFET of the internal circuit is formed and the first back bias wiring or the second conductivity of the internal circuit. A second cell including any one of the third switch elements provided between the second bias wiring and the second back bias wiring connected to the second well region in which the type MOSFET is formed;
Corresponding to the corner of the element region where the internal circuit is formed, the corner power supply line connecting the first power supply line, the second power supply line, the power supply voltage line, and the circuit ground line to each other; A power switch controller that is disposed in a lower layer including the semiconductor substrate of the corner power supply line and controls the first switch element of the first cell, and the power supply voltage corresponding to the first bias line and the second bias line. A fourth switch element and a fifth switch element for connecting the line and the ground line of the circuit, and a control circuit for controlling switching between the fourth switch element, the fifth switch element, the second switch element, and the third switch element. A plurality of types of distributed third cells, and the first cell, the second cell, and the third cell surround the internal circuit and the corresponding power supply lines are connected to each other. A semiconductor integrated circuit device comprising a plurality of the internal circuits corresponding to the size of the internal circuit. In claim 1 ,
Corresponding to the first direction, including the first power supply line and a capacitor element disposed on a lower layer including the semiconductor substrate of the first power supply line and provided on the power supply voltage line and a ground line of the circuit. A fourth cell;
A fifth power supply line corresponding to the second direction, and a fifth power supply line disposed on a lower layer including the semiconductor substrate of the second power supply line, and a capacitive element provided on the power supply voltage line and the ground line of the circuit A cell,
The fourth cell is arranged alongside the first cell,
A semiconductor integrated circuit device, wherein the fifth cell is arranged alongside the second cell. In claim 2 ,
Among the corner power supply lines, the sixth cell is provided with a power switch controller that controls the first switch element of the first cell corresponding to one corner power supply line.
A fourth switch for connecting the power supply voltage line corresponding to the first bias line and the second bias line to the ground line of the circuit corresponding to the remaining corner power supply line among the corner power supply lines. A seventh cell in which elements, a fifth switch element, the fourth switch element, the fifth switch element, and a control circuit for controlling switching of the second switch element and the third switch element are distributed; A semiconductor integrated circuit device. In claim 3 ,
An eighth cell having the first power supply line that is shorter in the first direction than the first cell corresponding to the first direction;
8. A semiconductor integrated circuit device, wherein the eighth cell is arranged side by side with the first cell and the fourth cell. In claim 4 ,
In the first, fourth, and eighth cells arranged in the first direction, a plurality of first wiring layers extending in the first direction are disposed below the first power supply line,
The semiconductor integrated circuit device according to claim 1, wherein the first wiring layer includes one used for transmission of a control signal for performing switch control of the first switch element. In claim 1 ,
On the semiconductor region where the internal circuit is formed, further includes a power supply line that is grid-connected by mutually connecting the power supply lines provided on the inner side of the second power supply line,
A semiconductor integrated circuit device comprising a plurality of wirings provided in a lower layer of such a power supply line and extending in a first direction so as to cover a semiconductor region in which the internal circuit is formed in a mesh pattern.

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