WO1997032399A1 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
WO1997032399A1
WO1997032399A1 PCT/JP1997/000608 JP9700608W WO9732399A1 WO 1997032399 A1 WO1997032399 A1 WO 1997032399A1 JP 9700608 W JP9700608 W JP 9700608W WO 9732399 A1 WO9732399 A1 WO 9732399A1
Authority
WO
Grant status
Application
Patent type
Prior art keywords
circuit
power
wiring
type
voltage
Prior art date
Application number
PCT/JP1997/000608
Other languages
French (fr)
Japanese (ja)
Inventor
Masahiro Kanai
Original Assignee
Seiko Epson Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0016Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507Interface arrangements
    • H03K19/018521Interface arrangements of complementary type, e.g. CMOS

Abstract

A semiconductor integrated circuit device generates an output signal (Vpw) having a logical amplitude specified by a first power source (Vssl) and a third power source (Vss2) which is lower in potential than the first power source (Vssl) from a substrate bias control signal by means of a first signal voltage level converting circuit (A1) and a first logic circuit (A2) and impresses the output signal (Vpw) upon a P-well in an N-channel MOS transistor formed in a function module in the device. The device also generates another output signal (Vnw) having a logical amplitude specified by a second power source (Vdd1) and a fourth power source (Vdd2) which is higher in potential than the second power source (Vdd1) from the substrate bias control signal by means of a second signal voltage level converting circuit (B1) and a second logic circuit (B2) and impresses the signal (Vnw) upon an N-well in a P-channel MOS transistor formed in the functional module in the circuit device. When this semiconductor integrated circuit device is used, the power consumption of the device can be reduced in a standby mode by raising the threshold voltage by impressing a substrate bias, and the operating speed of the device can be increased in an operation mode by lowering the threshold voltage by releasing the device from the substrate bias. The increase of the operating speed at the operating time and the lowering of the power consumption at the standby time are simultaneously realized by securing a new power supply wiring area for controlling PMOS and NMOS back gate electrodes which are different in potential from power supply wiring and grounding wiring and providing a wiring rule which permits efficient wiring layout, and then, making the layout design of the power supply wiring and signal wiring easier.

Description

Akira fine manual semiconductor integrated circuit device

[Technical field]

The present invention relates to a semiconductor integrated circuit device comprising a substrate Baiasu control circuit for controlling the threshold voltage of the MO S transistor by applying a substrate Baiasu.

[Background Art]

In general, as the semiconductor integrated circuit device, a semiconductor memory device, but are various gate arrays and the like, a semiconductor integrated circuit device is intended to be composed of a plurality of MO S transistor formed on a semiconductor substrate . Moreover, usually such a semiconductor integrated circuit device is maintained within a range where the potential of the semiconductor substrate is always defined.

Figure 31, such a semiconductor integrated circuit device, for example, a schematic diagram of a chip layout of the gate array is shown. The semiconductor integrated circuit device is constituted by functional modules MO and the peripheral circuit I 0 is formed on a single semiconductor substrate, the peripheral circuits 10, for example, including the input and output control circuit, and the like. Function module M0 is to realize the required functions of the semiconductor integrated circuit device, which is thus composed of so-called internal circuits into a plurality of MOS transistors. Then, peripheral circuits including the input-output control circuit and the like are also configured by MOS transistors.

For example, using the layout pattern of the power wiring features proc in master-slice type semiconductor integrated circuit device, FIG. 33, and FIG. 34 (a), the anti-rolling logic circuit (hereinafter referred to as Invar evening circuit) shown in (b) It described Te.

Mass evening slice type semiconductor integrated circuit device, the inverter circuit, the inversion logical product circuits (hereinafter referred to as NAND circuits), the lattice basic cell corresponding to the logical gates such as NOR circuit (hereinafter referred to as NOR circuit) those aligned with Jo. That is, the semiconductor integrated circuit device of this type is due to previously LS I previously formed on the chip, to obtain a desired LSI by adding only wiring design between basic cell method basic cells. However, the power supply wiring and ground wiring is previously layout scheme Suyo also meet specifications for electrical properties which basic cells are determined. Then, the basic cell have a several and summer as logical function blocks can be realized, the wiring path evening Ichin to 实現 the Kowara is pre Reiau Bok design, are those prepared as a library. The FIG. 34 (a), the indicated symbol of the inverter circuit I NV 5 is one in which an output signal X with respect to the input signal A is output at inverted logic. When indicating this Inba Isseki circuit in the circuit diagram of Bok flange disk level, the circuit configuration as shown in FIG. 34 (b).

Inpata circuit I NV 5 shown in FIG. 34 (b) input terminal to which an input signal A is input, (denoted hereinafter PMO S) P-channel M_〇 S transistor gate of Q 14 - Bok terminal and N-channel MO it is intended to be connected in common to S Torasojisuta (denoted hereinafter NM OS) gate terminal of Q 1 7. Furthermore, before ^ the source pin and back gate Ichito terminal and the power supply line Vddl of PMO SQ 14, the source terminal and the server Kkuge Ichito terminal of NMO SQ 17 are respectively connected to the ground line Vss 1, the PM0 SQ 14 drain terminal and the drain terminal of NM_〇 SQ 1 7 has become connected to each other at the output terminal of the output signal X is output.

The Inba Ichita circuit, the matrix to Bok wiring Reiau on one basic cell of a plurality located base cell group, the wires Reiauto as shown in Figure 33.

The transistor structure of the present cell shown in FIG. 33 is a company all sorts, where the gate electrode G 23, G 25 and the channel width than the gate electrode G 23, G 25 is small Saigeichito 鼋極 G 27, leasing 'and drain electrode SD 33, SD 35, SD 37. and NMO SQ 1 7 made of SD 39 or the like, the gate electrode G 18, and G 20, source. the drain electrode SD 28, SD 30, and SD 32 wiring Reiau to Bok using PM0 SQ 14 basic units (two PM_〇 S + two NMO S + 1 sub 'NMO S) and basic cells you the like made of.

Figure 34 (a) as the basic cell and constituting an inverter circuit INV [delta] shown in FIG. 34 (b), the wiring Reiauto shown in Figure 33. That is, the ground wiring layer Vss 1 is formed by first metal wiring layer which is extended in the channel length direction of the MO S transistor. Through the connection holes,! The source electrode SD 35 of the serial ground wiring layer Vssl and MMOSQ 17, and a source 'drain electrode SD 33 not used © E Le electrode B 1 1 is that it ¾ gas connected.

The power supply wiring layer Vddl is formed from first gold 厲配 line layer which is extended in the channel width direction of the MO S Bok Rungis evening. Through a connection hole, wherein the power supply wiring layer Vddl and P MO SQ source electrode SD 30 15 and source 'drain electrode SD 28 not used and Ueru electrode B 12, are electrically connected.

The Ueru electrode B 1 1 is extended in the channel width direction of the MO S transistor evening. And it is electrically connected through the Ueru electrode B 1 1 and the ground wiring layer Vssl and power connection hole C 1. On the other hand, Ueru electrode B 12 is extended in the channel width direction of the MO S transistor. Wherein the Ueru electrode B 12 and the power supply wiring layer Vddl is electrically connected through a contact hole C 2.

Furthermore, inverter Ichita circuit input signal A for controlling the I NV 5 is applied to the first metal interconnection layer Ml A, gate electrodes G 20 connection NM 0 SQ gate electrode G 25 14 and PM 0 SQ 17 by each being electrically connected to the first metal wiring layer M 1 a through hole, the input signal a is applied to the gate electrode G 25 and G 20.

- How, the output signal X of which are output to the first metal wiring layer M 1 X, at the output of the inverter I NV 5, a drain electrode SD 37 of NMO SQ 14, drain of P MOSQ 17 through the emission ¾ electrode SD 32 and is connecting hole, are respectively connected to the first metal wiring layer M 1 X. Thus, typical CMO S circuit each drain electrode SD 37, SD 32 is including the inverter as evening circuit output signal is electrically commonly connected are formed of the NMOSQ 14 and PMOSQ 17 is PM_〇_S was achieved, and each common potential NMO S both the source electrode and the Ueru electrode.

By the way, in recent years, is an information processing apparatus no Bok 'PCs microprocessor, and the and the surrounding LS I, and the mode of operation speed at the time of such as a portable information terminal for LSI, strong low power consumption in the standby mode It has been summer as required. For example, the development of battery powered form information terminal, a small-type 'weight by reducing the number of cells in a cellular phone or the like, has come to a long time operation including a standby is required. In addition, the development of digital data processing, voice, data, processing of information such as an image becomes enormous, and since the high-speed clock has become exothermic limit, has come to a high speed is required . Further, CMO by SLSI branch surgery exhibition, di - by the Pusabumikuron CMO SLSI improve integration, but has become the power consumption in the single level reduced, the power consumption of the LSI for has decreased a lot number of elements has been increased summer . From these ¾ reason, the development of high-speed and low-power consumption CM 0 S technology has been summer to be recommended.

As the Padzukeji for accommodating the LSI, plastic package, although ceramics package and the like, expensive Ceramic box package is used for high power consumption LSI. As described above, the high integration of a semiconductor integrated circuit device, power consumption has been greatly summer force; believed to lower power consumption is desirable in terms of cost.

Here, the consumption power POWER is the load capacitance 鲎 C, are those represented a clock frequency f, and m source 鼋圧 by Formula 1 as follows to Vdd.

Equation 1: POWER = C · f · Vdd J

As can be seen from Equation 1, for the realization of lower power consumption, the load capacitance C, clock frequency f, but to lower the power supply voltage Vdd Te to base is ideal, the Te these to base things the 夬 s lowered, and the speed of operation modes, it is extremely difficult to achieve both low power consumption in the standby mode. In other words, the load capacitance C is dependent on the manufacturing process, E 夬 in the process requires, it is difficult to reduce the load capacitance C. One our, ^ to the operation of the conductor integrated circuit instrumentation ia at high speed, since is possible to increase the clock frequency becomes necessary, it is desirable to be for lower power consumption lowers the clock frequency f Absent. Therefore, in order to reduce the power consumption, is possible to lower the power supply voltage Vdd from the formula 1 is most effective.

Incidentally, the delay time is proportional to the expression 2 shown below. Here, in equation 2 indicates the expression 2 coefficients 5, the threshold voltage of the transistor evening as Vth.

Equation 2: C · Vdd / 3 (Vdd- Vth) - '

However, as can be seen from Equation 2, by lowering the power supply voltage Vdd, increases during the time delay, hinder speed. Therefore, in order to speed up the semiconductor integrated circuit device without increasing the delay time, it is effective to lower the threshold voltage Vth of Bok Rungis evening, it is possible to speed without slowing down the delay time.

Further, the leak current during standby is proportional to Equation 3 shown below. Here, the equation 3 the slope of the current I d with respect to the voltage V g of Sa Busuretsushorudo region as S. Equation 3: e X p (- Vth / S)

As can be seen from Equation 3, by lowering the 閲値 voltage Vth, because the drain-Zosu question current of the transistor flows during standby increases, the leakage current is increased. Therefore, changing the threshold voltage in the standby and during 勁作, and to satisfy both the operating speed and the standby leakage.

That is, to satisfy the both sides of the speed and the standby mode power consumption during the time of this mode of operation - as a step, it is effective to positively utilize the substrate bias effect (or the substrate effect).

The substrate bias effect, by applying a substrate by § scan the back gate electrode of the MOS transistor, the threshold voltage changes in the MO S transistor, drain-source current versus gate-source voltage in the substream Redzushorudo region characteristics are those that change.

For example the drain-source current characteristics with respect to the gate-source voltage in the subthreshold area of ​​NMO S transistor shown in FIG. 32 (a) described below.

NMO S of the back gate electrode to the source electrode and the same applied to the state of the potential N 3 (threshold voltage -. About +0 7 V) and then, when a positive potential is applied to the back gate electrode to the source electrode, the state N 3 (threshold voltage -. about +0 7 V) from the state N2 (. threshold voltage = about +0 5V) or changes to state N 1 (threshold voltage = about +0 3V.). Then, the off current increases along with the threshold voltage of the NMO S is reduced.

Further, the source electrode, applying a negative potential to the back gate electrode, the state N3 (threshold voltage -. About +0 7 V) from the state N4 (. Threshold voltage = about +0 9 V) or N 5 (閩値 voltage - about + 1. 1 V) changes into. Then, the off-current decreases as the threshold value voltage of NMO S is increased.

This PM_〇 S transistor (hereinafter PMO shown as S) is intended to indicate similar characteristics change even, drain for example FIG. 32 (b) to PMO sub Threading Scholl de that put a region gate one Zosu voltage of S source question current characteristics are shown.

Source to the back gate one Bok electrode of PM 0 S? The state of applying the same ¾ position as the g-pole p 3

(Threshold voltage = about a 0. 7V) and, when a negative potential is applied to the back gate one gate electrode to the source electrode in contrast to the NMO S, the state P 3 (閬値 voltage = about a 0. I from V), the state P 2 (threshold voltage = about - 0. 5V) or condition P 1 (threshold voltage = about - changes 0. to 3 V). Then, the off current increases in absolute value to the co-the threshold voltage of the PMO S decreases in absolute value.

Moreover, contrary to the NMOS, Uz when a positive potential indicia pressure to the back gate electrode with respect Ichisu electrode, PMOS, the state P 4 from the state P 3 (threshold voltage = about a 0. 7V)

(Threshold voltage - about - 0. 9V;), or condition P 5 (threshold voltage = about a 1. IV) to vary the. The upper 悶値 electrostatic 压 is in absolute value - off current decline in absolute value as well as?.

Using this characteristic, the child Me NMOS, PMO sub Threading Scholl de region characteristic state of S N2 (threshold voltage = about +0 5 V.), The state P 2 (threshold voltage = about - 0. 5V) or further absolute condition N 1 threshold voltage is low in value (threshold voltage = about +0. 3 V), to form formed as a sub-Threading Scholl de region characteristic of state P 1 (閟値 voltage = approximately -0. 3 V) . Further, the operation mode, the source electrode and the back locate the electrode by the same potential, to lower the threshold voltage of the M_〇 s transistor in absolute value, to flow a large amount of a Ddo rain 'lease current in absolute value . Thereby, the sweep rate pitch control of the MOS transistors constituting the function modules to improve the drive capability causes faster, it is possible to speed up the semiconductor integrated circuit device.

The standby mode Conversely, the back by the gate electrode to apply a substrate bias connexion, MO S to increase the threshold voltage of the transistor in absolute value, and very small in absolute value the off current state N 3 (threshold voltage = about +0. 7 V), the state P3 (threshold voltage two about a 0. 7 V). Alternatively, the absolute value the threshold voltage is high N 4 in the ^ (threshold voltage = about +0. 9 V), the state P4 (threshold voltage = about a 0. 9V) or condition N 5 (threshold voltage = about + 1 . IV), and alter the properties to the state P5 (threshold voltage = about a 1. IV). Therefore, the standby current of the functional modules can and child very small, it is possible to reduce the power consumption of the semiconductor integrated circuit device.

As described above, applied to a semiconductor integrated circuit device of the substrate bias effect, it has been researched and developed in recent years, in order to apply the substrate bias effect to the semiconductor integrated times device adjusts the substrate potential or Ueru potential, it is necessary to mount a substrate bias control circuit to the semiconductor integrated circuits devices.

That is, in order to apply the substrate bias effect to the foregoing CMO S circuit, PMO S, is independently each source electrode and the back gate Ichito electrode of NMO S, the potential of the power supply line or ground line is supplied to the source electrode different new power supply wiring of each back gate electrode control is required. Further, when the master-slice type semiconductor device that apply this effect, the power supply wiring, the wiring layout including ground wiring and the signal wiring is to be ray © preparative designed by software Touea such automatic placement and routing, new providing PMOS, NM 0 S how efficiently wiring or a power supply wiring for the control each back gate electrodes of, along with ensuring the wiring space is an issue, it is necessary to define the Haihanada rules.

Incidentally, it mounted on the semiconductor integrated circuit device using the substrate bias effect, as a conventional technique of the substrate bias control circuit, day 絰 BP published by "Nikkei Micro Device, 1 995, March ¾, P. 58 to 60" Toshiba semiconductor devices Institute of technology published in, Mr. Tadahiro Kuroda, there is a substrate bias control circuit in accordance with Takayasu Sakurai said.

C of the substrate bias control circuit 35, the evening I timing chart showing the signal waveforms shown in FIG. 36, FIG. 37

Substrate bias control circuit shown in FIG. 35, ^ conductor integrated circuit device external from the power supply voltage Vdd = + 2V, and the ground voltage Vss = ± 0 V, the voltage VPBB-- 2V newly NM 0 S of P Weru for, voltage VNBB = + 4 V is intended to be supplied to the N Ueru for the PMO S. Then, by changing the substrate Baiasu functional module units of the semiconductor integrated circuit device, optimally controls the power and speed dynamically for all circuits.

Next, the operation of the substrate bias control circuit shown in FIG. 35, FIG. 36 is described with reference to FIG.

By chip 'Ineburu signal CE is set to the high level, the inverted signal CE (bar) is set to the mouth first level operation mode one de of the chip Ineburu signal CE is set.

By the chip Ineburu signal CE is set to the high level, NMO SQ 47 is turned on, the potential of the line VN 1 is to ± 0 V, NMO SQ 49 is turned on.

Then, the N MO SQ 49 force 'when it is turned on the potential of the line VX 2 is a ± 0 V, Gui man-de D 1 potential connected in series in the forward direction of the line VN 3, D 2 approximately equal to the connection number to a potential obtained by multiplying the threshold electrostatic FE of Guiodo. For example, da Iodo is connected to three series, if the threshold voltage of ¾ Symbol diode is + 0. 6V, the potential of the line VN 3 is about + 1. 8 V. Incidentally, PMO SQ 48 is turned on at all times.

By the ^ position said line VN 3 is about + 1. 8 V, PMO SQ 50 is turned on, NMO SQ 57 is turned off, the potential of the line VN 4 is a +4 V. When the potential of the line VN4 is to +4 V, PMO SQ 52 Gao off state, NMO SQ 59 is turned on, the potential of the voltage Vnw = + 2 V is applied to the N Ueru in the functional module that.

- How by chip 'Ineburu signal CE of the inverted signal CE (bar) is set to a low level, PMO SQ 44 is turned on, the potential of the line VP 1 is a + 2V, PMO SQ 46 is turned on.

Then, ¾ Symbol PMO SQ 46 is once turned on, the potential of the line VP 2 is a + 2 V. The potential of the line VP 3 are serially connected diode D 3 in the forward direction, D 4 of the number of the connected Tohoho potential multiplied by the threshold ^ pressure of the diode to a value 'equal L, and potential, the potential of the line VP 2 It drops to minus from + 2 V. For example, three diodes are connected in series, when the threshold voltage of the diode is +0. 6 V, the potential of the line VP 3 is about + 0. 2 V. It should be noted, NMO SG 5 1 is always turned on.

By the potential of the line VP 3 is about + 0 · 2 V, PMO SQ 54 is turned off, NMO SQ 53 is turned on, the potential of the line VP 4 is as one 2 V. When the potential of the line VP 4 is as one 2 V, PMO SQ 56 is turned on, the NMO SQ 55 is turned off, the potential of the voltage Vpw = ± 0 V to P Ueru in the functional module It applied.

Then, the chip Ineburu signal CE by being set to the low level, the chip 'inverted signal "CE rice one table No. CE (bar) is set to the standby mode one de set to the high level.

When the Chibbu 'Ineburu signal CE is set to the mouth first level, NMO SQ 4 7 is turned off, the potential of the line VN 1 is Vdd- Vth: are (Vth the threshold voltage of the NM 0 SQ 49) Therefore, the NMO SQ 49 are turned off.

When the NMO SQ 49 is turned off, with respect to the potential voltage VNB B line VN 2, multiplied by the threshold voltage of Daio over de serially connected diodes D 1, D 2 of the connection number in the forward direction It drops by approximately equal potential and potential. For example, Daio one de is connected to three series, when faction value ¾ pressure of the diode is + 0. 6 V is, ¾ position of line VN 2 is about + 2. 2V. Since PMO SQ48 is always on, the potential of the line VN 3 is a +4 V.

When the potential of the line VN 3 is about + 4 V, PMOSQ 50 is turned off, NMO SQ 57 is turned on, the potential of the line VN 4 is a + 2 V. When the potential of the line VN 4 is a +2 V, PM_〇 SQ 52 is turned on, NMO SQ 59 is turned off, functions conductive position voltage Vnw = + 4 V to the N Ueru in the module applied It is. '

On the other hand, by the chip 'Ineburu signal CE of the inverted signal CE (bar) is set to a high level, PM_〇 SQ 44 is turned off, the potential of the line VP 1 is Vss + Vth (Vth: PMO SQ 46 to become a threshold voltage), PMO SQ 46 are turned off.

When the PMO SQ 46 is turned off, the potential of the line VP 2 were column I connected in the forward direction with respect to the voltage VP BB, diode D 3, D 4 of the connection number to the diode threshold 'I It rises by approximately equal to the potential obtained by multiplying the above. For example, Daio - de is connected to two series, if the threshold voltage of the diode is + 0. 6 V, the potential of the line VP 2 becomes about a 0. 8V. Since NMO SQ 5 1 is always turned on, the potential of the line VP 3 is as one 2 V.

Potential of the line VP 3 is about - When the 2 V, PMO SQ 54 is turned on, NM 0 SQ 5 3 is turned off, the potential of the line VP 4 is a 0 V. When the potential of the line VP 4 is to OV, PMO SQ 5 e is turned off, NMO SQ 55 is a O emissions state, voltage P Ueru in the functional module Vpw = - potential of 2 V is It applied.

Therefore, the imperial operation mode, by the source electrode and the back gate one Bok electrode is at the same potential, the threshold voltage is lowered MO S transistor in absolute value, and drain-Tsu Ichisu current flows more in absolute value Therefore, the drive capacity can be improved with the Suitsuchi control of MO S preparative transistors constituting the function module is faster.

Further, in the standby mode, by the this substrate bias to the back gate electrode is applied, the threshold voltage absolute value, it rots, II one for off-current is grass very small in absolute value, the standby current of the functional module It is very small. Chi words, "¾ in operation mode one de; was to realize the both surfaces of speeding up and ^ machine mode consumption turtle force of time.

However, the substrate bias control circuit of the prior art shown in FIG. 35, although the standby current not plow about 0.5 1〃Arufa after switching from operation mode one de in standby mode one de, the operation mode from the standby mode the standby current after switching to, PMOS Q48, Guiodo D l, the current path formed by D 2, NMO SQ47, Q 49, there is no MO S transistor walking diode element turned off. That is, the diode is always in order voltage is being applied element on the end, not the complete off-state, thus One Do equilibrium at a constant voltage. Accordingly, the substrate bias control circuit, the through current is flowing between the steadily voltage VNB beta · ground voltage Vss. This PMO SQ44, Q 46, also in the same way in the diode D 3, D 4, a current path formed by the NMO SQ 5 1, since there is no MO S transistor or Daiodo device turned off, constantly supply current was flowing in between the voltage Vdd ■ voltage VP BB. However, the steady current in the standby mode as described above, in particular, since the countermeasure against leakage current in the standby mode is a indispensable due to the spread of mobile phones, low power CMOS LSI it becomes a factor against the fact that the reduction and CM_〇 SLSI equipped with low power consumption of potential equipment. Also, the diode D l, in order to form the D 2, D 3, D 4, it is necessary to separate the Ueru region of each diode, NMO S Q47, Q 49, Q 57, Q 5 9 are formed that a P Weru region, and Ρ Ueru region NMO SQ 5 1, Q δ 3, Q 55 is formed, and PMOS Q44, Q 46, Q 54, Ν © E Le region Q 56 is formed, PMO SQ in addition to each © El separating 48, Q 50, New Ueru region Q 52 is formed, it is necessary to number only Ueru separation Daiodo used.

However, the separation of each Ueru, in order to further Ueru region and a non-conducting state adjacent, together with the need to provide a space of at least several 〃 m is present, the anode electrode extraction portion of Daio one de, and force cathode electrode extraction portion it is necessary to provide a, increases Reia © Bok area was preventing high integration of the semiconductor integrated circuit device.

Furthermore, in recent years LSI has taken the form of a two power mixed LS I, power is formed by the internal or LSI Chi-up external voltage supplied from the outside are Suitchingu internally. In particular, the high voltage is in many cases supplied from the outside, gate one WINCH oxide film of the larger voltage transistor to be applied is formed to be thicker.

However, as described above, because not recommended that high integration and miniaturization of LSI, although the thickness of the gate one Bok oxide film has come to be thinner, in the second power mixed LSI 2 the thickness of the gate oxide film in accordance with the higher voltage of the power supply is adjusted. Therefore, in the substrate bias control circuit, the thickness of the gate oxidation film has been formed thick, non ¾ occurs in long-term reliability and V, cormorants means of a gate oxide film of the transistor.

[Disclosure of the Invention]

An object of the present invention is to provide a semiconductor integrated circuit device having a substrate bias control circuit, by eliminating all current constantly flowing through path between the power supply, the standby current and standby mode after switching from the operation mode to the standby mode operation mode and both minute current standby current after replaced Ri switching to one de is to realize high-speed and low power consumption.

Furthermore, another object of the present invention, in the case of applying the substrate bias control circuit to a master-slice type semiconductors integrated circuit device, different PM 0 S is the potential of the power supply wiring and ground wiring, the back gates of NMO S securing a new power supply wiring area for electrode control, by providing efficient well wires Reiau Bok wiring rule is to realize high speed and low power consumption during waiting operation simultaneously.

The semiconductor integrated circuit device of the present invention,

In the semiconductor integrated circuit device having a transistor of a first conductivity type, a function module provided with the transistor of the second conductivity type,

Gate one Bok electrode to the control signal is applied on / off is controlled, and the source electrode first first conductivity type transient scan evening connected to the second power of 卨電 position than the first power supply When,

A gate electrode is controlled by an inverted signal of the control signal, the said first first conductivity type Bok transistors are exclusively on / off controlled and a source electrode connected to said second power supply a transistor 2 of the 1 ΐΐ¾,

Than the source electrode of the first 'sources are connected to a third power supply on the low potential, based on an operation of the operation and the first transistor of a first conductivity type second first-conductivity type Bok transistor and on / off of the first second conductivity type control transistor Te, a source electrode connected to the third power, the first conductive operation and the second of said first transistor of the first conductivity type a second second conductivity type transistor which is on / off controlled based on the operation of the types of transistors,

Interposed are connected in series between said first first-conductivity type transistor first second conductivity type transistor, the gate Bok electrode connected to the first power supply both tooth and register of the third first conductivity type connected to the drain electrode of the electrode of the first first conductivity type transistor,

Interposed are connected in series between the first transistor of the first conductivity type evening and the first second conductivity type transistor, both the gate one gate electrode is connected to said first power supply a source electrode connected to the drain electrode of the transistor of the first second conductivity type, the third second conductivity type which drain electrode is connected to the drain electrode of the transistor of the third first conductivity type and of the transistor,

Interposed are connected in series between said second first-conductivity type transistors evening and the second second-conductivity type transistor, the gate electrode coupled to the first power supply both the source and Bok Rungis evening fourth first conductivity type connected to the drain electrode of the electrode of the second first-conductivity type transistor,

Interposed are connected in series between said second first-conductivity type transistor and the second second-conductivity type transistor, the gate Bok electrode connected to the first power supply both the source electrode connected to the drain electrode of the transistor of the second second conductivity type, the fourth transistor of the second conductivity S of drain ¾ poles are contact with the drain electrode connection of the transistor of the fourth first conductivity type a first signal voltage level converting circuits including bets,

And buffer Aringu the output signal of the first signal voltage level converting circuit, a first logic circuit that controls the back gate electrode of Bok transistor of a first conductivity type constituting the function module,

Includes a substrate bias control circuit with,

In the first signal voltage level converting circuit, wherein the first second conductivity type Bok run drain electrode and said register third transistor of the second conductivity type source Ichisu electrodes comprises first second 2 is connected to the gate electrode of the conductivity type of the transistors, drain electrode and source electrode of the transistor of the fourth second conductivity type of the second second conductivity type transistor, the first second conductivity type is connected to the transistor evening gate one gate electrode, which the first transistor of the second conductivity type and the second second conductivity ¾ type flip-flop by comprising full Roh one Dobakkuru part Te transistor of the formed it is. Furthermore, the semiconductor integrated circuit device of the present invention,

In the semiconductor integrated circuit device having a transistor of a first conductivity type, a function module which is provided a Bok transistor of the second conductivity type,

Control signal to the gate electrode is applied on / off is controlled, and a transistor of the first second conductivity type source electrode connected to the first power supply,

A gate electrode is controlled by an inverted signal of the control signal from the evening of the first second conductivity type Bok Rungis are exclusively on / off controlled and a source electrode connected to said first power supply a transistor of the second conductivity type,

A source electrode connected to a fourth power supply, the first to the second operation and the first on / off based on transistor evening operation of the second conductivity type of the second conductivity type transistor is controlled a first conductivity type Bok Rungis evening, a source electrode connected to the fourth power, turned on based on the operation of the operation and the second second-conductivity-type transistor of the first transistor of the second conductivity type and / off of the second first conductivity type which is the control transistor,

Said first interposed are connected in series between the second conductivity type transistors evening and the first first-conductivity type transistor, and a gate electrode Ri higher potential der than the first power supply the It is connected to a second power supply potential lower than the fourth power supply, the third second conductivity type whose source electrodes are connected to the drain 'Susumukyoku transistor of the first second conductivity type and the transistor,

Interposed are connected in series between the first second conductivity type transistors evening and the first first-conductivity type transistor, the co the gate one Bok electrode connected to said second power supply , Zosu ^ pole is connected to the drain electrode of the transistor of the first first conductivity type I¾¾, transistor of the third first conductivity type which has a drain electrode connected to the drain of the transistor of the second conductivity type of the 3 When,

Said second interposed are connected in series between the second conductivity type transistor and the second first-conductivity type transistor, the co-when a gate electrode coupled to the second power supply, a source electrode There a fourth second conductivity type transistor that is connected to the drain electrode of the transistor of the second second conductivity type,

Said second interposed are connected in series between the second conductivity type transistor and the second first-conductivity type transistor, the co-when a gate electrode coupled to the second power supply, a source electrode There is connected to the drain electrode of the transistor before the second first conductivity type, transistor of the fourth first conductivity type which is connected to the drain electrode of the transistor of the second conductivity type drain electrode of the fourth evening and a second signal voltage level conversion circuit comprising,

The output signal of the second signal voltage level conversion circuit - to buffering, and a second logic circuit that controls the back gate electrode of the second conductivity ^ of the transistors constituting the function module,

Includes a substrate bias control circuit with,

In the second signal voltage level converting circuit, the first of the drain electrode of the first conductivity type Trang register third first conductivity type transistor evening of the source electrode of the second first conductivity type It is connected to the gate electrode of the transistor, a gate one of said second transistor wherein the drain electrode is the fourth first-conductivity-type source electrode of the transistor of the first first conductivity type transistor of the first conductivity type it is connected to the gate electrode, in which flip opening-up is formed by the front SL Fi one Dobadzukuru Ichipu made in the first first conductivity type Bok Rungis evening and the second first-conductivity type transistor . Therefore, the substrate bias control circuit for forming a signal to at least one of Ueru of the first conductivity type or the second conductivity type, to realize the both sides of the speed and the standby mode power consumption during the operation mode one de it possible, and, first Oyohi 'to eliminate fraud and mitigating risk constantly flowing a current path between a power source to at least one of the second I ^ voltage level converter circuit constituting the substrate bias control circuits can be, standby current after switching from the operation mode to the operation mode from the standby mode and ί temple motor mode can be very small, Ueru separation of Daio one de to reduce Reia © Bok area since unnecessary be able to.

Illustrate preferred semiconductor collector 楨回 path apparatus below.

(1) the substrate bias control circuit, said first, second, third, and transistor of the fourth first conductivity type is formed in Ueru region of the second conductivity type in the same region, the second conductive than is Ueru electrode in Ueru region of the mold the second power source or the second power is connected to the fourth power of a high potential, said first, second, third, and fourth second the conductivity type of the transistor is formed in Ueru region of the first conductivity type in the same region, with the said of the first conductivity type Ueru electrode connected to the third power supply first signal voltage level conversion circuit.

(2) the substrate bias control circuit, said first and second second conductivity type transistors in is formed in the first Ueru region of the first conductivity type of the same region, the first first-conductivity of is connected Ueru electrode type of Ueru region to said third power source, the third second-conductivity-type transistor is formed in Ueru region of the second first conductivity type of said second first conductivity type of being connected to the source electrode of the transistor of the second conductivity type Ueru electrode of the third, the fourth second conductivity type transistor is formed in the third Ueru area of ​​the first conductivity type, the third having a first conductivity type the first signal voltage level conversion circuitry which Ueru electrode Ueru region connected to the source electrode of the transistor of the fourth second conductivity type of the.

(3) the substrate bias control circuit, said first, second, third, and fourth transistors of the first conductivity type is formed on Ueru region of the second conductivity type in the same region of the second conductivity type is the connection to the power supply Ueru electrode of the fourth in the Ueru region, the first, second, third, and fourth second conductivity type transistor is formed in the first conductivity type Ueru region of the same region, a third pre-connected to a power supply of the SL second signal voltage level conversion circuit of the first conductivity type Ueru electrodes to open the Ueru region of the previous SL first power source or the first lower potential than the power supply .

(4) the substrate bias control circuit, the first 1 a single second first-conductivity-type transistors of is formed in Ueru region of the first second conductivity type in the same region, the first second conductive conductivity type Weru electrode Ueru region is connected to the fourth power of the third first conductivity type transistor is formed in Ueru region of the second conductivity type, the second second-conductivity wherein the Ueru electrode type of Ueru region third first conductivity type transistor of source - against the source electrode ^ is, the fourth conductive type of the transistor is formed in Ueru region of the third second conductivity type It is, with the third and the second signal 鼋 pressure level conversion circuit Ueru electrode connected before Symbol fourth first-conductivity-type transistor evening source electrode of the second conductivity type Ueru region of.

Therefore, in the present invention, by the back gate electrode of the transistor of the first conductivity type and a second conductivity type formed in the Ueru region is controlled, it can be changed the value voltage of the transistor next, it is possible to achieve low power consumption in the standby mode by decreasing the off-current, the drain-source - as scan 鼋流 flows many, high-speed of the second signal voltage level conversion circuit it is possible to improve the dynamic Sakuoyobi drive capacity.

Furthermore, to separate it has used the operation in the operation mode and the standby mode of the semiconductor integrated circuit device is preferably a semiconductor integrated circuit device illustrated below.

(5) the first signal voltage level conversion circuit, the third and of the fourth second conductivity type transistors, at least one of the channel length, said first and second second conductivity type transistor that the channel in which shortened formed from long, the third and least also one channel width of the fourth second-conductivity-type transistor of said first and second second conductivity type channel transistor it is those which are larger than the width, and the third and least one of the threshold voltage of the fourth second conductivity type transistors are of the first and second second conductivity type Bok transistor than the threshold voltage and is formed lower in absolute value, meet one of the conditions of the.

(6) the substrate bias control circuit, the first power supply and the third power supply, the output signal of the first logic a path logic amplitude is defined is, the first signal voltage level conversion circuit rather than regions where said first logic circuit is formed with, coupled to Ueru region of the first ^ conductivity type other functional modules forming region, the back gate one Bok transistor of the second conductivity type constituting the functional module gate electrode is the potential control.

(7) Symbol substrate bias control circuit, in the a i ij Symbol first power third power supply, the back gate of the transistor of the first conductivity type constituting the first logic circuit logic amplitude is defined - gate electrode is the fourth power supply and SeMMitsuru of the second power or said second potential higher than the power supply.

(8) ¾ Symbol substrate Baiasu control circuit, the first power source before | i in the third power source, back gate of the transistor of the first conductivity type constituting the first logic circuit logic amplitude is defined one Bok electrode is connected to the first power supply is a source electrode of the same potential of the transistor of the first conductivity type.

(9) said second iS voltage level conversion circuit of the transistors of the third and fourth first conductivity type, at least - the channel length of the square is, the first and second first conductivity type that the transistor and is formed shorter than the channel length of said third and at least one of the channel width of the fourth first-conductivity-type transistor of said first and second first-conductivity type transistor evening Bok that is obtained is larger than the channel width, and the third and least one of the threshold voltage of the fourth first conductivity type transistors are of the first and second first conductivity type satisfying one of the conditions of it than the threshold voltage of the transistor and is formed lower in absolute value.

(1 0) the substrate bias control circuit, in the name Symbol fourth 鼋源 and ¾ Symbol second power supply, the output signal of the second logic circuit for logical amplitude is defined, said second signal is connected to the voltage level converting circuit and the Ueru region of the second conductivity type second other functional modules forming region rather than the region where the logic circuit is formed, a transistor of a first conductivity type constituting the function module a back gate electrode of the potential control.

(1 1) the substrate bias control circuit, in the fourth power supply and the second power supply, of the second conductivity type constituting the second logic circuit logical amplitude is defined Bok Rungis evening the back gate electrode is connected to the third power of the first power source or the first potential lower in absolute value than the supply.

(1 2) the substrate bias control circuit, the fourth power supply and the second power supply, before logical 扳幅 are defined ^ the second conductivity type Bok Rungis constituting a second logic circuit other bar 'Sokuge one Bok electrode is characterized in that it is connected to the second ¾ source is Bok Rungis evening source electrode and the same potential of the second conductivity type.

Therefore, the output signal of the base bias control circuit, the operation mode / standby mode to be able to control the back gate Bok electrode of the transistor, during the operation mode, Suitsuchi control transistor evening in the function module can experience a faster with it, can improve drive capability, the functional module can be operated at high speed. Further, since the stand-by mode can be reduced off current Tran register in the function module, the power consumption of the semiconductor integrated circuit device can be realized.

The semiconductor integrated circuit device of the present invention is desirably a this having circuitry illustrated further below.

(1 3) the substrate bias control circuit includes a first inverted logic circuit for waveform shaping, for the waveform shaping to the first output terminal or the second output terminal of said first signal voltage level conversion circuit human power terminal of the first inverting logic circuit is connected to said first logic circuits to the output terminal the input terminal is connected to the logic amplitude is defined the first power supply and in the third power source, and the first of the first conductivity type is large channel length Ri by transistors constituting the logic circuit, the first conductivity type Bok transistor formed by any of the conditions of the small channel width and a high threshold voltage having a first inverting logic circuits for waveform shaping which includes.

(1 4) the first output terminal or the input terminal to the second output terminal of the second signal voltage level conversion circuit is connected, an output terminal to an input terminal of the second logic circuit is connected, the It defined logical amplitude at the fourth power supply and the second power source, and the larger channel length than transistor of a second conductivity type constituting the second logic circuit, one of the small channel width, and a high threshold voltage a second inverting logic circuit for waveform shaping by the second conductivity type transistors that are formed in any of the conditions.

Thus, the once after waveform shaping the output signal of the first signal voltage level conversion circuit, it is possible to buffer-ring by the first logic circuit, the signal of the input signal to the first logic circuit amplitude can and said first power supply and the third power supply and child, and after once waveform shaping the output signal of the second signal voltage level converting circuit, buffering by the second logic circuit it is possible, since the signal amplitude of the input ί word No. to the second logic circuit can and said second power supply and the fourth power supply and child, it is possible to reduce the leakage current of the machine mode it can.

Further, the first logical circuit and the second logic circuit is desirably configured as follows.

(1 5) said first logic circuit or the second logic circuit, and a small logic circuit driving capability which is formed on the input side, and a large logic circuit formed drivability is connected to the output side it is made of formed.

(1 6) The semiconductor integrated circuit instrumentation £ is formed on the second conductivity type on the substrate, wherein the first signal voltage level converting circuit, the first logic circuit or said first signal voltage level converting circuit, , the first logical 冋 ¾, by the first inverted logic circuit, the first signal voltage level converting circuit, the first logic circuit or said first signal voltage level converting circuit, wherein the first, logic circuits, only ½ Symbol first reversing back gate electrode of the second conductivity type transistor formed in the first conductivity type Ueru region is another functional modules forming region rather than the realm in which the logic circuit is formed There is potential control.

(1 7) The semiconductor integrated circuit device is formed on a first conductivity type on the substrate, the second signal voltage level converting circuit, the second logic circuit or said second signal voltage level converting circuit, It said second logic circuit, by the second inverting logic circuit, the second signal voltage level converting circuit, the second logic circuit or said second signal voltage level converting circuit, the second logic circuit, said second inverting first conductivity type Bok Rungis evening back gate formed on the second conductive type Ueru region is another functional module Ichiru forming region rather than the region in which the logic circuit is formed only the electrodes are potential control.

Accordingly, performs waveform shaping by the logic circuit formed on the input side, the larger logical circuit before Symbol Kamikotonori capacity formed on the output side, the second conductivity type constituting the functional module or said first conductive it is possible to form a signal for controlling the back-bias controlling voltage type transistor at high drive capability, it is possible to reduce the charge and discharge current when the mode switching operating modes / standby mode. Further, the output of the first logic circuit and the second logic circuit is the same as the output of each said substrate bias control circuit, wherein the output signal of the substrate bias control circuit, constituting the front Symbol function module second conductivity type transistor is formed, and by being applied before Symbol second conductive substrate and 'air-isolated first conductivity type S1 Ueru, first / second to the operation mode / standby mode the second voltage may be applied to the back gate electrode of the second conductivity type transistor.

Furthermore, the output of the substrate bias control 冋路 iS ^ is, the first conductivity type transistor is formed, and a second conductivity type substrate and electrically isolated from said first conductivity type constituting the function module Ueru in by being applied, the second / voltage of the fourth power supply during operation mode one read / wait mode one de, Ru can be applied to the transistor of the second conductivity ¾ type.

Functional modules of the present invention, it is desirable that the following configuration.

(1 8) A semiconductor integrated circuit device comprising a functional module forming region constituting a predetermined function module, a peripheral circuit including input and output circuit forming region external instrumentation ^ and fin evening one face input and output signals of the function module in the threshold electrostatic 压 of Bok transistors provided in the peripheral circuit formation region is formed in the first threshold value Den压, the threshold voltage of the transistor provided in the functional module formation region, the peripheral circuit formation territory is formed in the first than the threshold voltage lower second threshold value voltage with an absolute value of the transistor provided in frequency, by the functional module is set in the standby state, provided in the functional module formation regions has been been electrodeposition-position control of the back gate electrode of the transistor is set to a third threshold voltage higher in absolute value than said second threshold voltage. (1 9) and the functional modules forming region constituting a predetermined function module, the ^ conductive integrated circuit device having a peripheral circuit including input and output circuit forming area with external devices interface input and output g No. of the function module the functional module area and transistor evening threshold voltage provided on the input-output circuit formation region is formed in the first threshold voltage, by ι½ Symbol function module is set to the standby state, before Symbol function the potential of the back gate Ichito electrode of a transistor provided in the module formation region is controlled, it is set to a higher second threshold voltage in the absolute value than the first threshold voltage. Therefore, when the functional module is set in the standby state, the functional module - back gate one Bok electrode of transistor is formed on Le forming region evening is the potential control, the function speeding up of the functional module can be achieved low power consumption of the module Ichiru can be achieved.

Functional modules of the present invention are layout in the configuration illustrated below

Semiconductor 粜積 circuit device of the present invention, a transistor of the first conductivity type, comprising a basic cell constituted by transistors of a second conductivity type, Ma Bok Rikusu to configure the predetermined function circuitry by wiring change a functional module composed of a plurality of the basic cells placed in Jo, output cell to interface one face of the input and output signals and arranged external device to the peripheral edge of the functional module arranged by the cell group in the semiconductor integrated circuit device having a including a peripheral circuit of the group,

Power supplied to the plurality of basic cell groups are those supplied by the second gold 厲配 line layer above debris than the first metal interconnect layer and the first metal wiring layer,

In said first and said second conductive 鼋型 before Symbol first metal wiring layer which is extended in the channel length direction of the transistor, and the second power source, a first low-potential than the second power supply and a power is supplied to the cell group,

In said first and said second conductivity type Bok transistor before Symbol second metal wiring layer which is extended in the direction of the channel width of the fourth power of the second power supply and the same potential or a high potential, said first and a third power of the first power source and the same potential or a low potential is supplied to the serial cell group.

Therefore, said first metal wiring layer, more to the use of a second metal interconnection layer, it is possible to perform power supply efficiently. Furthermore, Reiau Bok semiconductor integrated circuit of the present invention is desirably Rukoto performed as exemplified below.

(2 0) supplying the first and formed by the second metal wiring layer which is extended in the direction of the channel width of the transistor of the second conductivity type, and said third power supply and the fourth power supply power wiring is disposed wires on the wiring grid Dokatsu Ueru electrodes of the first and the channel width direction of the second conductivity type Bok transistor.

Thus, the third and the second metal wiring layer power supply and the fourth power is supplied is, by being placed and routed on the Ueru electrode, the Ueru electrode, and said second metal interconnect layer it can be easily connected.

Furthermore, it is ¾ preferable that arrangement of the connection hole of the semiconductor integrated circuit device of the present invention is carried out as illustrated below.

Further, 'the conductor 粜穑 circuit device of the present invention, further a this having ί column Shimesuru circuit or less.

(2 1) and the second metal interconnect layer by prior to the second conductivity type © El electrode of the transistor of the first conductivity type ^ feeding the fourth power supply connection hole or the connecting hole and the first metals It performed via the wiring layer, wherein in the second first conductivity type Ueru electrode of the second conductivity type of the transistor due to the metal wiring layer third feed of power, connection holes or connecting hole and the first, It takes place via a metal wiring layer.

(2 2) the connection hole in which the transistors of the first and the second conductivity type is connected to Ueru electrodes formed is formed by the first metals wiring layer is wired and connected to said basic cells is, the conjunction is placed first between the power line and the second power line, said first and said second conductivity type on the wiring Guritsu de which is adjacent to the channel width direction of the transistor , wherein the Ueru electrodes of the first conductivity type transistor is connection hole for connecting the first power supply wiring is arranged, it is adjacent to the first and the channel width direction of the transistor of the second conductivity type and the wiring grid on, connection holes for a Ueru electrode of the transistor of the second conductivity type connected to said second power supply wiring is disposed.

Accordingly, by providing the connecting hole, the supplied to the second metal wiring layer, the third power supply and the fourth power supply, via the connection hole or the connecting hole and the first metal interconnect layer , it is possible to supply to the Ueru and said second conductivity type Ueru transistor of the first conductivity type, said transistor of the previous SL first conductivity type to the first power supply wiring, the second for ¾ Symbol second power line each source potential of the second conductivity type tiger Njisuta can be stabilized.

Furthermore, the semiconductor integrated circuit device of the present invention, it is desirable to control the Ueru potential as exemplified below.

(2 3) the case where the semiconductor integrated circuit device is formed on the first conductivity type on the substrate, before Symbol first and second power supplies are, before the transistor of his own first and the second conductivity type It is supplied at the first metal wiring layer which is extended to switch Yaneru length direction only and power wiring for supplying the third power source is extended in the direction of the channel width of the transistor of the first and the second conductivity type is formed by the second metal wiring layer, or the case where the semiconductor integrated circuit device is formed in the second conductivity type on the substrate, said first and second power supplies is the first and the second 2 is supplied at the conductivity type first metal wiring layer which is extended in the channel length direction of the transistors of, and the fourth channel of the transistor only supplies power wiring of the first and the second conductivity type power the second metal wiring layer which is extended in the width direction Is formed, Ueru of the second electrically 鼋型 said Ueru or said first conductivity type transistor of a second first conductivity type conductivity type transistor is formed is formed is separated from the substrate of the semiconductor integrated circuit ¾ location that.

(2 4) comprises a first Shirubekame type Bok Rungis evening and the basic cell that will be formed using the second Shirubekame type transistors, arranged in Matrix form constituting a predetermined function circuit by ¾ lines varying ¾ in the semiconductor integrated circuit device having a peripheral circuit including a plurality of said cell group, the input and output cell group Intafe Ichisu input and output signals and are arranged around the cell group external equipment, said plurality of power supplied to the cell group is the first power of the second power source and said second lower potential than the power supply, is extended to the first and the channel length direction of the second conductivity type transistor was fed in the first metal interconnect layer, and a fourth power of the second power supply and the 鼋位 or said second potential higher than the power supply, from the first power supply and the same potential or the first power supply also first aid and the third power of the low potential, the first power supply 1 and an auxiliary power source, and a second auxiliary power supply for assisting the second power source, the upper layer than the first metal interconnect layer while being extended in the first and the channel width direction of the second conductivity type transistor It is supplied at the second metal interconnection layer further before Symbol third auxiliary S source to assist the third power source, and a fourth auxiliary power to assist the fourth power of the first and the second conductivity type It is extended in the channel length direction of the transistor, and is supplied by the third gold 厲配 line layer above debris than the second metal wiring layer.

(2 5) said first and said second conductivity type Bok Rungis extended to evening in the channel width direction is formed in the first auxiliary power supply and the second auxiliary supplied by the second metal wiring layer power source via a connecting hole, the first with power and Become bound connected to the second of the first gold 厲配 line layer camera turns is supplied, the first and the second conductivity type tiger Njisuta said third auxiliary power source and the fourth auxiliary power is supplied by the channel i¾ direction is Nobekashiko the third metal interconnection layer via a contact hole, the third power and the fourth power supply It is connected to the second metal interconnection layer to be.

Thus, applied to the source electrode / drain electrode of Bok run register of the first conductivity type and the second conductivity type in first gold 厲配 ^ layer, supplies the first and second voltage, the substrate the first conductivity type field ^ is electrically separate the substrate Ueru the first conductivity type of the first conductivity type, and via the second metal wiring layer on the first conductive type Ueru , and it supplies the third power supply, the substrate in the case of the second conductivity type to electrically isolate the substrate of the second conductivity type and Ueru of the second conductivity type, the second conductivity type wherein the © E Le through the second gold 厲配 line layer, the fourth power supply by supplying it Ueru the potential of the case it as a back bias electrode it its' PS type Bok transistor it is possible to control. Furthermore, the first auxiliary power supply, the second auxiliary power supply, the third auxiliary power, using the fourth auxiliary power, said it that of the first conductivity type Bok Rungis motor and said second conductivity type transistor in electrodes, said first power supply, the second power source, it is possible to perform supply of the third power and the fourth power supply, the first auxiliary power supply, the second auxiliary power supply, the third auxiliary power, said fourth auxiliary power, can either be electrically connected through said cell group, the connection hole.

Furthermore, the semiconductor collector 稍回 channel device of the present invention, it is desirable that the layout as illustrated below.

(2 6) the third power supply, the fourth power supply, the first auxiliary power supply, the second auxiliary power supply has been extended in the direction of the channel width of the first and the second conductivity type Bok transistor is supplied to the basic cell groups by the power supply line and the auxiliary power wiring formed in the second metal interconnect layer, said power supply wiring lines of the first and the second conductivity type Bok Rungis data in the channel width direction It is coordinating ¾ wiring in the grid and Ueru on the electrode.

Therefore, the first power supply, the second power supply, the third power and the fourth power supply, without changing the library of placement and routing, the first and second conductive in the cell group can Reiauto the wiring for supplying the Ueru in types of transistors, Ru can be prevented a voltage drop in the semiconductor integrated circuit device center.

Furthermore, the semiconductor integrated circuit device of the present invention, it is desirable that the structure to have a device structure as illustrated below.

(2 7) The semiconductor integrated circuit device is formed on a substrate of a first conductivity ¾, said first and second power supplies is, extending in the first and the channel length direction of the second conductivity type transistor is supplied at the first gold 屈配 line debris is, and the fourth power supply, the first auxiliary power, extending in the channel width direction of the second only auxiliary supply of said first and said second conductivity type transistor is supplied at the awe has been the second metal wiring layer, I by further only the fourth auxiliary supply, the third metal interconnection layer extending in the first and the channel length direction of the second conductivity type transistor co feeding, or the semiconductor integrated circuit device is formed on the second conductivity type on the substrate, said first and second power supplies is the channel Ushitora transistor of the first 及 beauty the second conductivity type is supplied at the first metal wiring layer which is extended in the direction, one said Third power supply, the first auxiliary power, only the second auxiliary power is supplied by said first and said second metal wiring layer which is extended in the direction of the channel width of the second conductivity type transistors, further wherein only the third auxiliary power is supplied at the first and before Symbol said third metal wiring layer which is extended to the switch channel length direction of the transistor of the second conductivity type, evening transistor of the second conductivity type is formed second conductivity type Ueru the first conductivity type Ueru or transistor of the first conductivity type is formed is ¾ plate and electrically isolated in the semiconductor integrated circuit device has.

Thus, it applied to the source electrode / drain electrode of the first conductivity type and the second conductivity type Trang register in said first metal wiring layer, and supplies the first and second voltage, the substrate is first for conductivity type to electrically separate the substrate Ueru the first conductivity type of the first conductivity type, and via the second metal wiring layer on the first conductive type Ueru, the first 3 of the power supply, the substrate in the case of the second conductivity type wherein the second conductivity type Ueru and the second conductivity type of the substrate '¾; separated ¾ manner, of the second conductivity type wherein the © E Le via the second metal wiring layer, by supplying the fourth power supply, it is possible to control the potential of Ueru as Bakkubaiasu electrode of the transistor of that it conductivity type in each case and it is possible to prevent the voltage drop.

Furthermore, the semiconductor integrated circuit device of the present invention preferably has the following functions.

(2 8) said first and said third power supply and the fourth power source supplied by the second metal wiring layer which is extended in the direction of the channel width of the transistor of the second conductivity type, if Ku is wherein the third power and the fourth power supplied by the second gold 厲配 line layer, and the first and before ^ third metal wiring layer which is extended in transistors evening in the channel length direction of the second conductivity type ½ Symbol a third auxiliary power that is supplied by the fourth auxiliary power source, a sleeve-mode formed chip 'rice one enable signal is manually from an external device, or at an internal external device or a semiconductor integrated circuit device potential functional modules are controlled by a control signal.

(2 9) said first and said third power supply and the fourth power source supplied by the second metal wiring layer which is extended in the direction of the channel width of the transistor of the second conductivity type, if Ku is wherein said third auxiliary power that is supplied by the first and the second conductivity type Bok Rungis evening the third metal wiring layer which is extended in the channel length direction, the fourth auxiliary power source, said semiconductor current draft circuit instrumentation; each power supply wiring or the auxiliary power wiring are separated for each functional module in the chip 'Ineburu signal input from the β single external device, the sleeve or is formed within the external device or a semiconductor integrated circuit device · mode one de control signal is input to the selector first circuit.

Therefore, it is possible to choose their own potential control for each potential control or the respective functional modules of all functions modules, the chip 'Ineburu signal and the ground -. The flop mode control signal, in the operating state / standby state, the supply of the third power and the fourth power to unit cell group can be controlled.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a circuit diagram showing a substrate bias control circuit of Ν channel M_〇 S transistor of the first embodiment of the present invention.

Figure 2 is a timing chart showing signal waveforms of respective units in that the substrate bias control circuit of the N-channel MOS transistor of the first embodiment of the present invention.

Figure 3 is a circuit diagram showing a substrate Baiasu control circuit of P-channel MOS transistor of the 2 ¾ 施例 of the present invention.

Figure 4 is a evening I timing chart showing signal waveforms at various parts in the substrate Baiasu control circuit of P-channel MOS transistor of the second embodiment of the present invention.

Figure 5 is a circuit diagram showing a substrate Baiasu control circuit of N-channel M_〇 S transistor of the third embodiment of the present invention.

6 is a tie Minguchiya one preparative showing signal waveforms of respective units in the substrate Baiasu control circuit of N-channel MOS transistor of the third embodiment of the present invention.

Figure 7 is a circuit diagram showing a substrate Baiasu control circuit of P-channel MOS transistor of the 4 ¾ 施例 of the light.

Figure 8 is a timing chart showing the various parts of fg No. waveform in the substrate bias control circuit of P-channel MOS transistor of the fourth embodiment of the present invention.

Figure 9 is a circuit diagram showing a substrate bias control circuit of the N-channel M_〇 S transistor of the fifth embodiment of the present invention.

Figure 1 0 is a Ti timing chart showing signal waveforms at various parts of the substrate Baia scan control circuit of the N-channel MOS transistor of the fifth embodiment of the present invention.

Figure 1 1 is a timing chart showing signal waveforms of respective units in that P-channel MOS transistor evening substrate Baia scan control circuit of the sixth embodiment of the present invention.

Figure 1 2 is a timing chart showing signal waveforms at various parts of the substrate Baia scan control circuit of P-channel MOS transistor of the sixth embodiment of the present invention.

Figure 1 3 is a circuit diagram showing a substrate Baia scan control circuit of the N-channel MOS transistor of the seventh embodiment of the present invention.

Figure 1 4 is a seventh embodiment of the N-channel timing Chiya one Bok showing each part of ί saying No. waveform in substrate Baia scan control circuit of the MOS transistor of the present invention.

Figure 1 5 is the eighth in Thailand Minguchiya one Bok showing signal waveforms of respective units in that Ρ channel MOS Bok Rungis evening substrate Baia scan control circuit according to an embodiment of the present invention. Figure 1 6 is a tie Mi ing chart showing signal waveforms of respective units in that P-channel M 0 S transistor substrate Baia scan control circuit of the eighth embodiment of the present invention.

Figure 1 7 is a diagram showing an outline of a chip layout of the ¾ Ming ^ conductor 柒積 circuit device.

Figure 1 8 is a diagram showing a wiring layout of the inverter Ichita circuit of the ninth embodiment of the present invention.

Figure 1 9 is a diagram showing a circuit of a 1 ¾ 施例 and Inbata circuit of the ninth embodiment of the present invention.

2 0 is a diagram showing a wiring Reiau bets NAND circuit of the first 0 embodiment of the present invention.

Figure 2 1 is a diagram showing a circuit of a NAND circuit in the first 0 embodiment of the present ¾ bright. 2 2, Ru FIG der showing a wiring Reiauto of the 1 1 NOR circuit ¾ facilities one column of the present invention.

Figure 2 3 is a diagram showing a circuit of a NOR circuit of the first embodiment of the present invention.

2 4, Ru FIG der showing a wiring Reiauto the RAM circuit of the first and second embodiments of the present invention.

2 5 is a diagram showing an outline of a RAM circuit of the first and second embodiments of the present ¾ bright.

2 6 is a diagram for explaining a control method of the entire functional module by the substrate bias control circuit in the semiconductor integrated circuit device of the first third embodiment of the present invention.

2 7, in controlling all functions module by the substrate bias control circuit in the semiconductor integrated circuit device of the first 3 突施 of the present light, are cross-sectional views of the MOS transistors that make up the functional module.

2 8, M_〇 S transistors constituting the drawing for the control method will be described of a part of the functional module by the substrate bias control circuit in the semiconductor integrated circuit device of the first 4 embodiment of the present invention, the functional modules it is a cross-sectional view of.

2 9 is a diagram showing a layout of the power supply wiring and ground wiring in the semiconductor integrated circuit device of the first 5 embodiment of the present invention.

3 0 is a diagram showing a first 6 embodiment, and Chidzubureiau bets outline of a semiconductor integrated circuit device of the first 5 embodiment of the present invention. 3 1, Ru FIG der showing an outline of Chippureiau Bok of a conventional semiconductor integrated circuit device.

3. 2 shows a sub-Threading Scholl de region characteristic of the drain-source current against gate voltage in the MOS transistor for explain the present invention, showing the characteristics of (a) is N-channel M 0 S transistor a characteristic diagram, (b) is a characteristic diagram showing the characteristics of the P-channel M 0 S transistor.

Figure 3 3 is a diagram showing a wiring Reiau bets inverter Isseki circuit in a conventional semiconductor integrated circuit device.

3 4 is a diagram showing a circuit of Inba Ichita circuit in a conventional semiconductor current draft circuit device.

3 5 is a circuit diagram showing a conventional substrate bias control 冋路.

3 6 is a Ti Minguchiya one Bok showing the N-channel M 0 S transistor signal waveforms of the substrate bias control unit of the motor in the conventional ½ plate Baiasu control circuit.

3 7 is a tie Mi Nguchiya one preparative showing the signal waveforms of the substrate bias control unit of the P-channel MOS transistor capacitor of the conventional substrate bias control circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

Each embodiment of the semi-conductor integrated circuit device having a substrate bias control circuit and the substrate bias control circuit according to the present invention will be described with reference to the accompanying drawings.

1 7 is a schematic diagram of Chippureia © bets showing an 'embodiment of a conductive integrated circuit device according to the present ^ Akira is shown. The semiconductor integrated circuit shown in FIG. 1 7, for example, it is described as a mass Tasuraisu type semiconductor integrated circuit device. The semiconductor integrated circuit device of the present invention, the functional module MO which is formed on a single silicon substrate, a peripheral circuit 1 0 like. The functional modules M 0 in the figure, it is formed more configured basic cell columns to the basic unit as described above, although not particularly shown, the wiring connection between the basic cells is performed in the second metal interconnect layer it is intended to be. Then, in the peripheral circuit 1 0 includes output control circuit, board bias control circuit BB for performing the back-bias control to the function proc is also mounted on the chip. The substrate bias control circuit BB is the functional modules forming region M 0 not disposed, of the peripheral circuit formation region 1 0, for example, is distribution S on the corners of the chip. That is, the substrate bias control circuits BB is, by being positioned at a corner of the chip, in the semiconductor integrated circuit device such as a gate array, that using the free space of the chip, constituting a chip layout efficiently can.

<First embodiment>

Next, a description will be given of a substrate bias control circuit of the present embodiment. 1 shows a substrate Baiasu control circuit for NMO S according to the first embodiment of the present invention is shown, Ti Minguchiya one Bok diagram showing signal waveforms of respective parts in FIG. 2 is shown. Hereinafter, the substrate bias control circuit for NMO S of the present invention will be described with reference to FIGS.

S plate bias control circuit shown in FIG. 1 is constructed by One Manzanillo the first signal voltage level conversion circuit (the block A 1) a first buffer logic circuit (block A 2), a semiconductor collector 桢the supply voltage for more circuit devices outside Kiyoshie if the power supply voltage Vddl two + 2 V, a ground voltage Vss 1 = ± 0 V, newly NMO S of P Ueru for the example grounding voltage Vss2 = - 2 V supply It is. The switching of the operation mode and the standby mode, for example, the power supply voltage Vd 1 = + 2 V and chip Ineburu signal CE logic amplitude is defined by the ground voltage Vss 1 = ± 0 V, the sleeve-mode control signal SM, It performed Te cowpea to any one of the power 'down signal PD. Power down signal PD, the sleeve 'mode control signal SM is i No. instruct whether or not to activate the function module, previously provided for each product to which the substrate bias control circuit of the present invention use signals, the chip 'rice one enable signal CE, Roh Wa one' down signal ^ PD, sleep 'mode control signal SM, or any of the signals that have the said function may be used.

Next, the operation of the substrate bias control circuit shown in FIG. 1 will be described with reference to Tai Ming Guchiya one Bok in FIG. By chip 'Ineburu signal CE is set to the high level, the functional modules of a semiconductor integrated circuit device is set to the operation mode, the an inverted signal CE (bar) is set to the mouth first level. Therefore, PMO SQ 1 8 of the first signal voltage level conversion circuit (block A 1) is turned on, PMC SQ 22 since the potential of the line V 2 is changed to + 2 V is also turned on, the potential of the line V 4 is also changed to + 2 V. And NMO SQ 2 5, via the PM_〇 SQ 1 8, Q 22 in the ON state as described above, the potential rises of La fin V 6, the potential of Rain V 6 soil 0 V- Vth (Vth: MO Upon reaching the threshold voltage) of SQ 25, NMO SQ 2 5 are turned off.

The potential of the line V 6 soil 0 V- Vth: is reached (Vth the threshold voltage of NMO SQ 25), NMO SQ 1 9 is turned on, the potential of the line V 5 is changed to a 2 V . When the potential of the line V 5 is changed to one 2 V, NMOSQ 2 1 is turned off, because the NMO SQ 23 is turned on, electric position of the line V3 is changed to one 2 V.

Further, since the chip 'rice one enable signal CE is set to a high level, P MO SQ 1 6 are turned off, the potential of the line V 1 is ± 0 V + Vth (Vth: the PM 0 SQ 20 to change the 閩 Iifl ti pressure), PMO SQ 2◦ are turned off. Furthermore, PMO SQ 24 constituting conductive position from the output terminal of the first ^ No. 'pressure level converting circuit (Block A 1), i.e., the potential of the line V6 is, the first buffer logic circuit (block A 2) consisting NMOSQ 27 Inha Isseki is input to each of the gate electrodes of the circuit and. Here, the first buffer logic circuit (block A 2), the first signal voltage level conversion circuit (block A 1) and a Intafe Ichisu circuit with P Ueru the definitive all functional modules overall Chidzubu the charging and discharging of the driving circuit is performed to the P Ueru. Thus, the load capacitance is large Do because of the drive current, to so that to perform the reduced form waveform shaping the channel width of the first stage Inbata circuit, the charge and discharge time by increasing a channel width of the next-stage Inbata circuit it is desirable to be shorter.

Then, PMO SQ 24 is turned off, NMO SQ 27 from Rukoto set to the ON state, the potential of the line V 7 is changed to a 2 V. The output signal of the inverter Isseki circuit, i.e., the potential of the line V 7 is by being inputted to each of the gate Bok electrodes PMO SQ 2 6 and NM_〇 SQ 29 Tona Ru Inba Isseki circuit, the PMO SQ 26 is turned on, the NI OSQ 29 is turned off. In this way, the potential of the voltage Vpw = ± 0 V is applied to P Ueru of NMO S formed on the functional module of the semiconductor integrated circuit device.

When the potential of V pw = ± 0 V to P Ueru of NMO S formed on the functional module of the semiconductor integrated circuit device is applied functions, for example, FIG. 1 9 (a), which is shown in FIG. 19 (b) Te NM_〇 SQ 1 odor constituting the Inbata circuit INV 1 in the module, the ground source electrode voltage Vss 1 (± 0 V), so that the voltage Vpw to the back gate electrode (Sat 0 V) ​​is applied. Therefore, Roh, Kkugeto and source electrodes are at the same potential, the state N 1 (threshold voltage = about +0. 3 V) shown in FIG. 32 (a), state N 2 (threshold electric on = about + . 0. 5 V), to indicate the same characteristics as any state N 3 (threshold voltage = about +0 7V) No Chi, the threshold voltage is low and the drain - source - is to scan current flows more that. This illustrates another of the logic circuits constituting the functional modular Yule in the semiconductor integrated circuit device, a latch circuit, the same characteristics for the circuit of the multiplier or the like.

Next, by chip 'rice one enable signal CE is set to low level, 璣能 module semiconductors current 楨回 MichiSo 匿内 is set to the standby mode.

Then, as shown in FIGS. 1 and 2, it PMO SQ 1 6 of the first signal voltage level conversion circuit (plot click A 1) is turned on, the potential of the line V 1 is changed to +2 V from PM_〇 SQ 20 is also turned on, the potential of the line V 3 also changes to + 2 V.

For the potential of the line V 5, the PMO SQ 23, the potential via the PM 0 SQ 1 6, Q 20 is the above-mentioned on-state! : Raising the potential of the line V 5 is ± 0 V- V th: NMOSQ 23 when it reaches (Vth NMO SQ threshold voltage of 23) are turned off. Then, it positions soil 0 V- Vth of the line V 5: by reaching (Vth NM 0 threshold voltage of SQ 23), NMO SQ 2 1 is turned on, changes the potential of the line V6 is one 2 V to. When the potential of the line V 6 is changed to one 2 V, NM 0 SQ 1 9 is turned off, since the NMOSQ 2 5 is turned on, the potential of the line V 4 is - changes 2 V .

Further, since the inverted signal CE of the chip 'Ineburu signal CE (bar) is set to the high level, PMO SQ 1 8 are turned off, the potential of the line V 2 Judges ◦ V + Vth (Vth: PMO to change the threshold voltage) of SQ 22, PMO SQ 2 2 are turned off.

Inba potential of Sunawa Chi line V 6 of the output terminal of the first signal voltage level conversion circuit (block A 1) is made of PM OSQ 24 and NMOSQ 27 constituting the first buffer logic circuit (block A2) by being input to each of the gate one gate electrode of Ichita circuit, the PM_〇 SQ 24 is turned on, since the NMOS Q 2 7 is turned off, the potential of the line V 7 is the soil 0 V Change.

By the potential of the line V 7 is input to each of the gate one gate electrode of the inverter circuit consisting of PMOS Q 2 6 and NMO SQ 29, it PMO SQ 26 is turned off, the NMO SQ 29 are turned on from the potential of the voltage Vpw 2 V is applied to P Ueru of NMO S formed in function modular Yule in the semiconductor integrated circuit device. The semiconductor integrated circuit P Ueru the voltage of NMO S formed in the function module in the apparatus Vpw = - when the potential of 2 V is applied, for example, FIG. 1 9 (a), is shown in Figure 1 9 (b) in that functional modules, inverters Ichita circuit I NV 1 Oite the NMO SQ 1 constituting a ground source 菴極 voltage Vss 1 (± 0V), the voltage Vpw to the back gate electrode (- 2 V) is applied that. Therefore, the potential of the back gate electrode becomes a lower potential than the potential of the source electrode, the state N 3 was shifted only NA shown in FIG. 32 ^ a) (threshold voltage = about + 0. 7 V), NB only Schiff DOO state N 4 (. threshold voltage = about +0 9 V), NC only shift state N 5 - changes Izu Re of the states of the (threshold voltage of about + 1. IV). Therefore, the threshold voltage of the MO S transistor is high, 且 one off current is very small. This shows the ^ other logic circuits constituting the functional modules of the conductor integrated circuit device, La 'Sochi circuit, similar characteristics also circuits of the multiplier or the like.

Therefore, the operation mode for the back gate one Bok and source electrodes of the N MO S constituting the function module in the semiconductor integrated circuit device is set to the same potential, NMO S is the threshold voltage is low. Then, in the operation mode by controlling the potential of the back gate electrode of said NMO S, further, is to drain-source current flows more, both when the sweep rate Tutsi control of MO S transistor constituting the function module can be speeded Drive it is possible to improve the capability.

Say yes, the standby mode, the potential of the back gate electrode of the N MO S constituting the functional modules of a semiconductor integrated circuit device, to be a low potential than the potential of the source electrode and the monitor, the threshold voltage is high. Then, in the standby mode by controlling the potential of the back gate electrode of said NMO S, further, because the off current is very small, can be made very small standby current capability module.

Above As mentioned, the substrate bias control circuit in the first embodiment, it possible to realize the both sides of the power consumption in the standby mode and speed up the operation mode, and board bias control circuit in the first signal voltage level converting circuit constituting the (proc a 1), the power supply current constantly flowing through path can be eliminated between, switched from operation mode to standby mode and the standby mode one de the operating mode standby current after can be made very small.

Further, the substrate bias control circuit of the first embodiment, the mode of the substrate bias control circuit to allow the rapid charging and discharging of the function module, the standby mode from the operation mode, to some have the operation mode from the standby mode one de change can be performed at high speed. Further, although in FIG. 1 has been described for example in which the first buffer theory 埤回 path (block A 2) at inverter Isseki two, without having to be limited to this, the desired number of inverter Ichita it can be further configured. Although in FIG. 1 described first buffer logic circuit (block A 2) as I Ntafe one scan portion of said first signal voltage level converting circuit and the functional module, to apply the substrate bias control circuit products the specification, may not be provided if there is no particular need to consider the spin one de in the mode change as described above, before Symbol first buffer logic circuit (block a 2). The first bus Ffa logic circuit (block A 2) may be configured inverter circuit, NAND circuit and other logic circuits of the NOR circuits, and the like.

The substrate bias control circuit in the first embodiment, stress of the high voltage is designed to not be applied to the MOS transistors constituting the circuit. That is, an operation voltage is 3 V, the gate first source 3.3 are designed such that the voltage of V is applied, is further margin voltage between 1 0% ±. Thus, between gate one toe source, between gate one Todorein, since voltage is formed to be less than respectively 3. 6 V between Getueru, the gate oxide films of the MOS transistors constituting the substrate bias control circuit in particular It can be formed without increasing the thickness. Accordingly, since the substrate bias control circuit of this embodiment can form all the MOS transistors in the gate oxide film of the same thickness, it is possible to form at easy process, long gate oxide film of the MO S transistor it is possible to improve the reliability, the reliability of semiconductors integrated circuit device can also be improved, and can correspond to thinning of the gate oxide film corresponding to the high integration.

Furthermore, ¾ plate bias control circuit of the first embodiment, the first signal voltage level conversion circuit (Burodzuku A 1) is, PMO SQ 1 6, Q 1 8, Q 20, Q 22 and the N Ueru the same area formed in, may power the power supply voltage of the second embodiment described the N Ueru later Vdd 2 (eg if + 4V). Therefore, the described the PMO SQ 30, Q 32, Q 34, Q 36 and 2 constituting the second signal voltage level conversion circuit of the second embodiment (Burodzuku B 1) after the ethics circuit (Block B 2) it is possible to form the same N Ueru region and PM_〇 SQ 42 constituting configured to PMO SQ 38, Q 40 or the second inverter evening circuit of the fourth embodiment (the block B 3), reduced Reiauto area to it can be. Say yes, can in particular by the forming each independent P Ueru area NMO SQ 23, Q 25 of the first signal voltage level conversion circuit (block A 1) connexion, the potential of the back gate electrode is 剐御, the back since the gate electrode and the source electrode are at the same potential, the threshold voltage is low, and is adapted to drain-zone Ichisu current flows more, the first signal voltage level conversion circuit (block a 1) can be a high-speed operation together, it is possible to improve the driving capability.

Substrate bias control circuit for NM_〇 S according to the first embodiment, a semiconductor integrated circuit device external from the power supply voltage Vddl (e.g. + 2V), and a ground voltage Vssl (e.g. ± 0V) Apart newly NM_〇 S and Although P Weru ground voltage for Vss2 (eg, single 2 V) is being supplied, it constitutes Chiya one di 'pump circuit based on a ring oscillator in the semiconductor integrated circuit device in place, also generating a negative potential it can. However, this case is unstable voltage supply, compared to the substrate bias control circuit shown in FIG. 1, inferior in power consumption.

Further, by using the substrate bias control circuit, the bus variability of the threshold voltage of the semiconductor integrated circuit device can be self-correcting. As described above, the threshold value voltage of the MOS transistor is about 1 0% error on production arises, to a problem that a low voltage in recent years the power supply voltage, the charge 'pump, the leakage current detection circuit, and the using the substrate Baiasu control circuit of embodiment, by controlling the connected power line and the back gate electrode in operation, it is possible to compensate for the threshold ¾ pressure.

<Second Embodiment>

3 shows, the substrate Baiasu control circuit for PMO S according to the second embodiment of the present invention is shown, Thailand Minguchiya one Bok diagram showing signal waveforms of respective units in FIG. 4 is shown.

Substrate bias system circuit shown in Figure 3, that consists the second issue the voltage level converting circuit and (block B 1) second buffer logic (block B 2). Then, ^ power from conductor integrated circuit device external '® pressure Vdd 1 = + 2 V, and a ground voltage Vssl = ± 0V, newly PMO S of N in Ueru for example, the power supply voltage Vdd 2 = + 4 V is supplied that. , The operation mode, and tjl Toggles standby mode, for example, the supply voltage V dd 1 = ten 2 V and the ground voltage V ss 1 = chip Ron珲 width is defined by the ± 0 V 'i ne one table No. C E, sleeves 'mode control signal S Micromax, power' performed Te cowpea to any one of the down signal [rho D. . Power down signal PD, the sleeve - mode - de control signal SM is a signal that instructs whether or not the function module to Akutibu, prearranged signal for each product to which the substrate bias control circuit of ¾ bright the use, can be used ι SL chip Ineburu signal CE, a power down signal PD, Sri Ichipu mode control signal SM, or any of the signal having the function.

Next, the operation of the substrate bias control circuit shown in FIG. 3 will be described with reference to tie Mi Nguchiya Bok shown in FIG.

By chip. Ineburu ^ No. CE is set to the high level, the functional modules of the semiconductor current product circuit device is set to the operation mode. Then, NMO SQ 33 of the second signal 鼋 pressure level converting circuit (Block B 1) which is turned on, the NMO SQ 37 also turned on since the potential of Rai down V 1 is changed To 0 V , the potential of the line V 3 also changes to the Judges 0 V.

Then, a PMO SQ 34, via the NMO SQ 33, Q 37 is in the ON state as described above, the potential of the line V 5 decreases, the potential of the line V 5 is + 2 V + Vth (Vth: PMO SQ by reaching the threshold voltage) of 34, it is a PMO SQ 34 Gao off state. Potential of the line V 5 is + 2 V + Vth: by reaching (Vth the threshold voltage of the PMO SQ 34), PMO SQ 32 is turned on, the potential of the line V 6 is changed to +4 V. Before ^! By the potential of the line V 6 is changed to + 4 V, PMOS Q 30 is turned off, the potential of the PM 0 SQ 36 line V 4 from the fact that is turned on tens of 4 V changes.

Further, since the inverted signal CE of the chip 'rice one enable signal CE (bar) is set to the low level, NMO SQ 3 5 are turned off, the potential of the line V 2 + 2 V- Vth ( Vth: to change the threshold voltage) of NMO SQ 39, NMO SQ 3 9 are turned off.

The electric position of the output terminal of said second signal voltage level conversion circuit (Block B 1), i.e., the potential of the line V 5 is a PMO SQ 38 constituting the second buffer logic circuitry (Block B 2) It is input to each gate 鼋極 of ​​Inbata circuit consisting of NMO S Q4 1. Here, T¾ Symbol second buffer logic (block B 2) is inter one Fuesu circuit with N Ueru that put on the second signal voltage level conversion circuit (Block B 1) and all functions module, line the charging and discharging of the driving circuit noose against Chidzubu entire N Ueru. Accordingly, because the load capacitance of the driving current is increased, by causing the formed small waveform shaping the channel width of the first-stage Inba Ichita circuit Unishi, charging by increasing a channel width of the next Inbata circuit discharge it is desirable to shorten the time.

Then, PMO SQ 38 is turned on, NM_〇 SQ 4 1 from being in the off state, the potential of the line V 7 is changed to + 4 V. The potential of the output signal, i.e. the potential of the line V 7 is by being inputted to each of the gate one gate electrode of Inba Isseki circuit consisting PMO SQ 40 and NMO SQ43, PMO SQ 40 is turned off, NMO SQ 43 is It is turned on. Therefore, the potential of the voltage Vnw = + 2 V is applied to the N Ueru of PMO S was made form the functional modules of the semiconductor integrated circuit device.

When the semiconductor integrated circuit N Ueru the voltage of the PMO S formed in the function module in the apparatus Vnw = + 2 V potential touches applied, for example, shown in FIG. 1 9 (a), FIG. 1 9 (b) in PMO SQ 2 constituting the Inbata circuit INV 1 in the functional module, zo Ichisu electrode to the supply voltage Vdd 1 (+ 2 V), the voltage to the back gate electrode V n (+ 2 V) is applied. Therefore, the back gate electrode and the source electrode are at the same potential, the state P 1 shown in FIG. 32 (b) (threshold voltage = about - 0. 3V), the state P 2 (the threshold voltage - about a 0. 5 V ), the state P 3 (the threshold voltage approximately two - to show the same characteristics as any state of 0. 7V), the threshold Kame圧 low in absolute value, one drain 'source current number in absolute value It flows. This illustrates another of the logic circuits constituting the functional modules of the conductor integrated circuit device, a latch circuit, the same characteristics for the circuit of the multiplier or the like.

Next, as shown in FIGS. 3 and 4, by the chip rice one enable signal CE is set to Loule bell function module of the semiconductor integrated circuit device is set to the standby mode, Ei SL It is set to the inverted signal CE (bar) Gaha Ireberu chip 'Ineburu signal CE. Therefore, NM_〇 SQ 35 of the second issue the voltage level converting circuit (block beta 1) is turned on, the potential of the line V 2 are NMOS Q 39 also turned on because it varies ± 0 V, the line potential of V 4 is also changed to ± 0 V. A PMO SQ 36 the potential of the line V 6, reduces the potential through the Ν Μ 0 SQ 35, Q 39 of the O emissions state described above, the potential of Rain V 6 is + 2 V + Vth (Vth: PM OSQ by reaching the threshold voltage) of 36, PM_〇 SQ 36 is the is turned off Rain potential of V 6 is + 2 V + Vth (Vth: by reaches the threshold voltage of the PMO SQ 36), PMO SQ 30 is is turned on, the potential of the line V 5 is changed to +4 V. By ^ position of the line V 5 is changed to + 4 V, PMOS Q 32 is turned off, since the PMO SQ 34 is turned on, the potential of the line V 3 is changed to + 4 V.

Further, the Chidzupu 'for rice one enable signal CE is set to the mouth first level, N MO SQ 33 are turned off, the potential of the line V 1 + 2 V- Vth (Vth: NM OS Q 37 to change the threshold voltage), NMO Q 37 are turned off. The potential of the output terminal of the second signal voltage level conversion circuit (Block B 1), the potential of the ie line V 5 is, PMO SQ 38 and NMOS constituting the second buffer logic circuitry (Block B 2) by being input to each of the gate one Bok electrode Inbata circuit consisting of Q4 1, PMO SQ 38 is turned off, the potential of the line V 7 since the NMOS Q4 1 is turned on is changed to + 2 V .

Potential of the output signal voltage or line V 7 is by being inputted to the gate electrode of each of Inba Ichita circuit consisting PMO SQ 40 and NMO SQ 43, PMOS Q40 is turned on, NMO SQ 43 is turned off that. Therefore, the potential of the voltage Vnw = + 4 V is applied to the PM 0 S N-Ueru formed functional module of the semiconductor current product circuit instrumentation 匱内.

When the potential of the N Ueru the voltage Vnw = + 4 V of PMO S formed on the functional module of the semiconductor integrated circuit device is applied, for example, shown in FIG. 1 9 (a), FIG. 1 9 (b) is, in PMO SQ 2 constituting the Inbata circuit INV 1 in the functional modules, the power supply voltage Vdd 1 (+ 2 V) to the source electrode, the voltage V n (+ 4 V) is applied to the back gate electrode. Therefore, the potential of the back gate electrode becomes a potential higher than the potential of the source electrode, the state P 3 was shifted only PA shown in FIG. 32 (b) (閲値; pressure - about - 0. 7V), PB only the state P 4 were shifted (threshold ¾ pressure = about a 0. 9V), in order to change only the state P 5 was shifted (threshold voltage = about a 1. IV) if Re noise conditions PC, threshold is high voltage in absolute value, and the off current is very small in absolute value. This illustrates another logic circuit for configuring the functional modules of a semiconductor integrated circuit device, a latch circuit, the same characteristics for the circuit of the multiplier or the like.

Thus, since the operation mode to the back gate Ichito electrode and the source electrode of the P MO S constituting the function module in the semiconductor integrated circuit device is set to the same potential, PMO S is the threshold voltage is low in absolute value, and drain-source current is to flow much in the absolute value. Further, by controlling the potential of the back gate electrode of the PMO S, the Suitsuchingu control of MO S transistor constituting the function module at the time of operation modes is possible speed, it can be improved drive performance.

Further, in the standby mode, the potential of the back gate electrode of the P MO S constituting the functional modules of a semiconductor integrated circuit device, than the potential of the source electrode is a high potential, the threshold value voltage is high in absolute value, and off current is very small in absolute value. By controlling the potential of the back gate electrode of the PMO S, standby current function Mojiyu Le standby mode one soil can be made very small. As described above, the substrate bias control circuit of the 2 ¾ 施例, together can be realized both sides of the power consumption of the high-speed and standby mode of operation modes, constituting the substrate bias control circuit Oite to the second signal voltage level conversion circuit (block B 1) which, since the current constantly flowing through 絰路 to the power Q is not present, a later and ^ machine mode is switched from the operation mode to the standby mode one de the scan evening Mumbai current after switching the operation mode can be made very small.

Further, the substrate bias control circuit of the second embodiment, and enables high-speed charging and discharging of the substrate bias control circuit to function module, the standby mode from the operation mode, a certain have mode changes to operating mode from the standby mode it can be performed at a high speed. Say yes, without being limited to the force which was placing himself on example of forming the second buffer logic circuitry (Block B 2) at invar evening two in FIG. 3, more structure to the desired number of inverters be able to. Say yes, although in FIG. 3 described second buffer logic circuitry (Block B 2) as Intafe one scan portion of the second f voltage level converting circuit and the functional module, to apply the substrate bias control circuit products the specification, may not be provided if there is no particular need to consider the spin one de in the mode change as described above, before Symbol second buffer logic (block B 2). The second bus Uz off § logic circuit (block B 2) may be configured inverter evening circuit, NAND circuit and other logic circuits of the NOR circuits, and the like.

The substrate bias control circuit of the second embodiment, stress of the high voltage is designed to not be applied to the MOS transistors constituting the circuit. That is, an operation voltage is 3 V, gate and between one Tososu 3. 3 V voltage is designed to be applied, the more margin voltage is the ± 1 0%. Thus, gate one WINCH between first source, gate one drain, since the voltage is formed to be less than respectively 3. 6 V between Getueru, gate one bets of each MOS transistor constituting the substrate bias control 叵路the oxide film can be formed without particularly thick. Therefore, it is possible to form lever to the substrate bias control circuit of the present embodiment, the MOS transistor functional modules on the chip constituting the MOS transistor and a peripheral circuit to be configured at the same thickness of the gate Bok oxide film since, it is possible to form at easy process, it is possible to improve the long-term reliability of the gate oxide film of the MOS transistor, it can also be improved reliability of the semiconductor integrated circuit device, and, highly integrated It can cope with thinning of the gate oxide film corresponding to.

Further, the second signal voltage level conversion circuit, NMO SQ 33, Q 35, Q 37, and Q 39 is formed in the P Ueru the same region, grounding voltage of the first embodiment of this N Ueru described above Vss2 (e.g. - 2 V) by connecting to, N MO SQ 19 constituting the first signal voltage level conversion circuit of the first embodiment (proc a 1), Q 2 1, Q 23, Q 25 and the PMO SQ 3 1 which constitutes the first buffer logic circuit first Inba Isseki circuit of the third embodiment to be described (proc a 2) constituting the NMO SQ 2 7, Q 29 or later (plotted click a 3) and because can be formed in the same P Weru region, it is possible to reduce the layout area. Further, by forming the particular N Ueru region each independently a PMO SQ 34, Q 36 in the second signal voltage level converting circuit (Block B 1), a back gate electrode and the source electrode be the same potential since it, together with the threshold voltage in absolute value can be lowered, and now the drain-source current flows more in absolute value, the second signal voltage level conversion circuit (plot click B 1) which can operate at high speed, the drive capability it is possible to improve. Substrate bias control circuit for PMO S according to the second embodiment, apart from the semiconductor integrated circuit device power 氅圧 Vddl (e.g. + 2V) from the outside and the ground voltage Vssl (e.g. ± 0V), the newly PMO S N supply voltage Vdd2 to the friendly Ueru (e.g. + 4V) but has been supplied, instead based on the ring oscillator to a semiconductor integrated circuit device Chiya - di 'constitute a pump circuit, it may generate a positive potential. However, this case is unstable electrodeposition pressure supply, compared to the substrate bias control circuit shown in FIG. 3, inferior in power consumption.

Further, by using the substrate bias control circuit, the bus variability of the threshold voltage of the semiconductor integrated circuit device can be self-correcting. As described above, the threshold value voltage of the MO S transistor is about 1 0% error on production arises, to a problem that the low voltage of the recent supply pressure, the charge 'pump, the leakage current detection circuit, and using the substrate Baiasu control circuit of the present embodiment, by controlling the power supply wire connected to the back gate Bok electrode during operation, it is possible to compensate for the threshold voltage. <Third embodiment>

5 shows, the substrate bias control circuit for NMO S according to a third embodiment of the present invention is shown. Substrate bias control circuit of this embodiment, between the first signal voltage level conversion circuit shown in FIG. 1 (block A 1) and the first buffer logic (proc A 2), the first buffer logic circuit long Ji Yaneru length than PMO S constituting the (block A2), a small channel width, high among the threshold voltages any method first for waveform shaping which is configured with a PMO S formed by Inba Isseki circuit (plotted click a 3) is in the added structure. The circuit operation in the substrate bias control circuits of the third embodiment, are shown in timing chart of signal waveforms in FIG. 6, the circuit operation for the substrate bias control circuit the same parts as those of the first embodiment denoted by the same references numerals, repeated descriptions for operational effects and the corresponding contents described in the first embodiment will be omitted. Incidentally, since the first Lee Nba Ichita circuit (block A3) add the output terminal of the first signal voltage level conversion circuit (Bro click A 1) is the inverted signal of the potential of the line V 6 It is connected change to the line V 5.

Substrate Baiasu control S path of the third embodiment are those which attained further reduce the power consumption of the base plate bias control 冋路 of NM 0 for S described in the first embodiment. That is, the substrate bias control circuit shown in FIG. 1, the high potential line V 5 is the potential of the output terminal of the first signal voltage level conversion circuit (block A 1) is ± 0 V- Vth (Vth: MO since the threshold voltage) of SQ 23, Roh Ffa PMO SQ 24 constituting the logical 冋路 (block a 2) is not a perfect oFF state. Here, the first buffer logic circuit (block A 2), the first signal voltage level conversion circuit (block A 1) and a Intafe Ichisu circuit with P Ueru in all functional modules, the entire chip the charging and discharging of the driving circuit to be made to the P Ueru.従Tsu Te, the load capacitance of the driving current becomes large, so as to perform the reduced form waveform shaping the channel width of the first-stage inverter circuit, the charge and by increasing form Chiyane le width of the next stage Inba Isseki circuit so that the discharge time is shortened.

However, in the substrate bias control circuit of the present embodiment, the first inverter Ichita circuit for waveform shaping to minimize the leakage current flowing from the ground wiring layer Vssl the ground wiring layer Vss 2 (block A3) It has become an additional configuration. That is, the potential of the output signal from the first signal voltage level conversion circuit (Block A 1), Chi words, the potential of the line V 5 is also thereby decreased threshold amount of NMO S, in the range of 2 V voltage first Inbata path for waveform shaping for a full amplitude (block a 3), was formed between a first voltage level converting circuit (block a 1) a first buffer logic circuit (block a 2) it is intended. P MO S constituting the first Lee Nba Ichita circuit (block A 3) is, P MO S longer channel ¾ constituting the first buffer logic circuit (block A 2), a small channel width, high | ¾ leakage current due to the use of PM_〇 S formed by any method of the values ​​voltages that very small.

Further, the channel length of the PMO S, and changing the channel width, along with can easily be changed by the mask design, 'the PMO S of King, Channel in a semiconductor process' high threshold dose S: ​​no need to change the like. That is, shown a back gate electrode of the P MO SQ 2 6 constituting the first buffer logic circuit (block A 2), higher than the source potential of the PMO SQ 26, the power supply voltage Vddl (+ 2 V) or 3 by connecting to a power supply voltage Vdd2 to (+4 V), it is possible to easily increase the threshold voltage.

Furthermore, the substrate Baimasu control circuit of the third embodiment, mode from the substrate bias control circuit to allow the rapid charging and discharging of the function module, the standby mode from the operation mode, there have the on the operation mode from the standby mode one de it can be carried out one de rapidly changing. Further, although in FIG. 5 described for example in which the first buffer logic circuit (block A2) at inverter Isseki two, it is not limited thereto, and more inverter Isseki desired number it can be configured. Further, although in FIG. 5 and described as fin evening Fue scan section between the functional modules of the first signal voltage level conversion circuit of the first buffer logic circuit (block A 2), applying the substrate bias control circuit the product specifications, may not be provided if there is no particular need to consider the speed at mode one de change as described above, before Symbol first buffer logic (block A2). The first bus Ffa logic circuit (block A2) can also be configured inverter circuit, N the AND circuit, the other logic circuit of the NOR circuits, and the like. The substrate bias control circuit of the third embodiment, stress of the high voltage is designed to not be applied to the MO S transistors constituting the circuit. That is, an operating voltage is 3V, are designed so that a voltage of 3. 3 V between the gate 'source is applied, further margin voltage is the ± 1 0%. Therefore, the gate.-Source, gate-drain, the voltage is formed to be less than respective 3. 6 V between gate 'Ueru, the gate oxide of each M_〇 S transistors constituting the substrate bias control circuit the membrane can be formed without particularly thick. Therefore, according to the substrate bias control circuit of the present embodiment, the on-chip to form a MO S transistor constituting the MO S transistor and peripheral circuit constituting the function module at the same thickness of the gate one gate oxide film since it is, it is possible to form at easy process, MO S can improve the long-term reliability of the gate Bok oxide film of the transistor, it can also be improved reliability of the semiconductor integrated circuit device, and it may correspond to 溥膜 of the gate oxide film corresponding to Takashu Sekika.

Substrate bias control circuit for NMO S according to the third embodiment, a semiconductor integrated circuit device supply voltage Vddl (e.g. + 2V) from the outside, and P of the ground voltage Vss l (e.g. ± 0V) separately newly NMO S and Although ground for Weru voltage Vss2 (eg, single 2 V) is being supplied, constitute Chiya one di 'pump circuit based on a ring oscillator in the semiconductor integrated circuit device in place, it is also possible to generate a negative potential . However, this case is unstable voltage supply, compared to the substrate bias control circuit shown in FIG. 5, inferior in power consumption.

Further, by using the substrate bias control circuit, the bus variability of the threshold voltage of the semiconductor integrated circuit device can be self-correcting. As described above, the threshold value voltage of the MOS transistor is about 1 0% error on production arises, to a problem that a low voltage in recent years the power supply voltage, the charge pump, the leakage current detection circuit, and the using the substrate Baiasu control circuit of embodiment, bar during operation, by controlling the power supply wire connected to the Sokuge Bok electrode, it is possible to compensate the threshold Kame圧.

Ku fourth embodiment>

7, the substrate bias control circuit PM 0 for S according to the fourth embodiment of the present invention is shown. Substrate bias control circuit of this embodiment, during the second signal voltage level conversion circuit (pro click B 1) and the second buffer logic (proc B 2) shown in FIG. 3, the second buffer the logic circuit (block B 2) long Chi Yaneru length than NMO S constituting the small channel width, the second waveform shaping constructed using the NMO S formed by any method of the high threshold voltage of Inba Ichita circuit (plotted click B 3) is in the added structure.

The circuit operation in the substrate bias control circuit of the fourth embodiment, are shown in timing chart of signal waveforms in FIG. 8, the circuit operation is the substrate Baia scan control circuit and the same parts of the second embodiment denoted by the same reference numerals, for the operation and effect corresponding to the content and it described in the second embodiment descriptions thereof will not be repeated. Incidentally, by adding the second inverter Ichita circuit (Bro carbonochloridate B 3), the output terminal of the second signal voltage level conversion circuit (Block B 1) is the potential of the line V [delta] in the second embodiment is connected changes to the potential of the line V 6 is an inverted signal.

Substrate bias control circuit of the fourth embodiment are those which attained further reduction in power consumption of the substrate bias control circuit for a PMOS described in the second embodiment. That is, the substrate bias control circuit of FIG. 3, the second signal voltage level conversion circuit (block beta 1) low potential run-V 5 is the potential of the output terminal of + 2 V + Vth (Vth: PM OS Q since 34 is the threshold voltage) of, NMO SQ 4 1 constituting a buffer logic circuit does not become completely oFF state. Here, the second buffer logic (pro click B 2), the second signal voltage level conversion circuit (Block B 1) and a fin evening Fuesu circuit N Ueru in all functional modules, the charging and discharging of the driving circuit to be made to the entire chip N © E Le. Accordingly, since the load capacitance is large, so as to perform the reduced form waveform shaping the channel width of the first-stage Inba Ichita circuit, between charging and discharging 鼋時 by increasing a channel width of the next Inba Ichita circuit to short Kunar so.

However, the substrate bias control circuit of the fourth embodiment, by adding the second Inba Ichitakai path for waveform shaping to suppress the leakage current flowing from the power supply line Vdd2 to the power distribution line Vddl minimize (block B 3) and it has a configuration. That is, the potential of the output signal from the second signal voltage level converting circuit (Block B 1), i.e., the potential of the line V 6 also results in decreased threshold amount of PM_〇 SQ 36, the range of the voltage of 2 V NMO S is longer channel length than NMOS constituting the second buffer logic circuitry (block B 2), small channels constituting the second inverter evening circuit for waveform shaping for causing the full amplitude (block B 3) width, are used NMO S formed Ri by the method of any of high threshold voltage. Therefore, the leakage current is very small. Further, the channel length of NMO S, and changing the channel width, NMO S along with can easily be changed by the mask design, a high threshold voltage is not necessary to change the Channel 'dose like in a semiconductor process. That is, a back gate electrode of the NMO SQ 45 constituting the second inverter evening circuit (block B 3), lower than the source potential of MMOSQ45, ground voltage indicated in the ground voltage Vssl (± 0V) or ¾ 1 Vss2 - by connecting to (2 V), can be easily increased threshold 鼋圧.

Further, the substrate bias control circuit of the fourth embodiment, the ½ plate bias control circuit to allow the rapid charging and discharging of the function module, the standby mode from the operation mode, there have the on the operation mode from the standby mode one de the mode one de change can be performed at high speed. Further, although in FIG. 7 described for example of forming the second buffer logic circuitry (Block B 2) at two inverters Isseki, without being limited thereto, the desired number of inverter Ichita it is possible to further configuration. ¾, the ^ 7 has been described second buffer logic circuitry (Block B 2) as Intafe one scan portion of the second signal voltage level converting circuit and the functional module, to apply the substrate bias control circuit products the specification, may not be provided if there is no particular need to consider the spin one de in the mode change as described above, before Symbol second buffer logic (block B 2). The second bus Dzufa logic circuit (block B 2) may be configured inverter circuit, NAND circuit and other logic circuits of the NOR circuits, and the like.

The substrate bias control circuit of the fourth embodiment, stress of the high voltage is designed to not be applied to the MOS transistors constituting the circuit. That is, an operating voltage is 3V, are designed so that a voltage of 3. 3 V between the gate 'source is applied, further the Ma one gin voltage is the ± 1 0%. Therefore, the gate 'between the source, between the gate WINCH-drain, gate' because the voltage is formed to be less than respective 3. 6 V between Ueru, the gate of each MO S transistor constituting the substrate Baiasu control circuit the oxide film can be formed without particularly thick. Accordingly, since the substrate bias control circuit of this embodiment can form all MO S transistor at the same thickness of the gate oxide film, it is possible to form in simple manufacturing process, MO S transistor the gate Bok oxide film can be improved long-term reliability of the can is improved reliability of the semiconductor integrated circuit device. And it may correspond to the thickness of the gate oxide film corresponding to the high concentration Sekika.

Substrate bias control circuit for PMO S according to the fourth embodiment, apart from the semiconductor integrated circuit device external from the power supply voltage Vddl (e.g. + 2 V) and the ground voltage Vssl (e.g. ± 0 V), the newly PMO S supply voltage Vdd2 to the N Ueru for (e.g. + 4V) but has been supplied, instead based on the ring oscillator to a semiconductor integrated circuit device Chiya - constitute a di-pump circuit may generate £ conductive. However, this case is unstable electrodeposition pressure supply, compared to the substrate bias control circuit shown in FIG. 7, inferior in power consumption.

X, using the substrate bias control circuit, the bus variability of the threshold voltage of the semiconductor integrated circuit device can be self-correcting. As described above, the threshold value voltage of the MOS transistor is about 1 0% error on production arises, to a problem that a low voltage in recent years the power supply voltage, the charge 'pump, the leakage current detection circuit, and the using the substrate Baiasu control circuit of embodiment, by controlling the connected power line and the back gate electrode in operation, it is possible to compensate for 閟値 voltage.

Ku fifth embodiment>

The Figure 9 substrate bias control circuit for NMO S according to a fifth embodiment of the present invention is shown. Substrate bias control circuit of this embodiment, each PMO SQ 24, the back gate electrode of Q 26 constituting the first buffer logic circuit (block A 2), a ground voltage Vssl (e.g. ± a source potential of the PMOS It has become connected to each other to 0V). Incidentally, the circuit operation in the substrate bias control circuit in the fifth embodiment, shown in the timing chart of FIG. 1 0 signal waveforms, circuit operation for the substrate bias control circuit the same parts as those of the first embodiment are the same denoted by reference numerals, repeated descriptions for operational effects and the corresponding contents described in the first embodiment that is omitted.

Substrate bias control circuit of the fifth embodiment, the first buffer logic circuit in the substrate Baiasu control circuit for NMO S described in the first embodiment: improved (P ch Q 24, Q 2 6) of the driving capability is not those which attained faster. That is, the substrate bias control circuit shown in FIG. 9, each PMOSQ 24, the back gate electrode of Q 26 constituting the first buffer logic circuit (Bro click A 2), Ru source potential der each PM_〇 S ground voltage Vssl (e.g. ± 0V;. those connected to and by the back Kugeto and source electrodes are at the same potential, and without the substrate bias effect, the threshold voltage of the PMO S absolute value is low, it is and which drain-source current is constructed as flows more in absolute value.

P Ueru capacity of large functional modules which are formed in a semiconductor integrated 问路 the apparatus, since the heavy load capacitance of several hundreds p F, in order to control the P Ueru potential for high speed, M 0 of the high driving capability S transistor is required. The first buffer logic circuit

To connect the back gate potential of each PMO S constituting the (block A 2) to the source one ground potential and a common ground voltage Vssl of each PMO S (e.g. ± 0V) is, PM0SQ 2 4, N for Q 26 Ueru region but is required, which is in accordance with the capacity of the P Ueru region functional modules, the first buffer logic circuit when the substrate by 7 scan effect is present

And layout area of ​​each PMO S constituting the (block A 2), the circuit configuration Ru is determined by correlation with increased layout ¾ product due to the provision of a dedicated N Ueru area.

<Sixth embodiment>

FIG 1 1, the substrate bias control circuit for PMO S according to a sixth embodiment of the present invention is shown. Substrate bias control circuit of this embodiment, a back gate electrode of the second buffer logic (block B 2) each NMO SQ 4 1 constituting the, Q 43 shown in FIG. 3, the source potential of each NMO S those which become connected to each to a supply voltage Vdd 1 (e.g. + 2V). Incidentally, the circuit operation of definitive substrate bias control circuit of the sixth embodiment, shown in timing chart of FIG 2 of the signal waveforms, circuit operation for the substrate Baiasu control circuit the same parts in FIG. 3 are the same denoted by reference numerals, and a description thereof will be omitted.

Substrate bias control circuit of the sixth embodiment, the second buffer logic circuits in the substrate bias control circuit for PMO S described in the second embodiment: the (Nc h Q 4 1, Q 4 3) of the drivability improving those which attained faster. That is, each NMO SQ ^ l of the second buffer logic (block B 2) of the substrate bias control circuit Ru shown in FIG. 1 2 to configure, a back gate electrode of Q 43, the source electric position of the NMO S are intended to be connected to a supply voltage Vddl (e.g. + 2V) it is. Then, by bus Kkuge Ichito electrode and lease electrodes are at the same potential, and without the substrate bias effect, is lower the threshold voltage of the NM 0 S, constructed and As the drain-source current is the flow number it is intended.

N Ueru capacity of large functional modules which are formed in a semiconductor integrated circuit device hundreds p for the more K load capacity F, in order to control the N Weru potential at high speed, M_〇 S high drivability transistor is required. The second buffer logic circuit

To connect the back gate potential of the NMO S constituting the (block B 2) to the source potential and the common power supply voltage Vddl d Retsue if + 2V) of the NMO S is, NM0S Q4

1, P Ueru area for Q 43 is required forces;, which according to the capacity of N Ueru region of the functional module, the second buffer logic circuit when the substrate bias effect is present

And layout area of ​​each NMO S constituting the (block B 2), to decision circuitry in correlation with increased layout area due to the provision of a dedicated P Weru area.

Ku seventh embodiment>

13, the substrate bias control circuit for NMO S according to the seventh embodiment of the present invention is shown. Substrate bias control circuit of this embodiment, each PMO SQ 24, Q 2 6 back gate electrode of which constitutes the as in the fifth embodiment the first buffer logic circuit of the third embodiment (Bro click A 2) , those that become connected to each to the ground voltage Vss 1 which is the source potential of each PMO S (for example ± 0V). Incidentally, the circuit operation in the board bus Iasu control circuit of the seventh embodiment, shown in timing chart of signal waveforms in FIG. 14, the circuit operation for the substrate bias control circuit the same parts as those of the first embodiment As described bear the same reference numerals will be omitted.

Substrate bias control circuit of the seventh embodiment, the first buffer logic circuit in board bus Iasu control circuit for NMO S described in Figure 5: Fast improves (P ch Q 24, Q 26) driving capability of it is those aimed at the reduction. That is, a back gate electrode of the first bus' couch logic circuits each PMO SQ 24 constituting the (block A2), Q 26 in the substrate bias control circuit shown in FIG. 1 3, Ru source potential der each PMO S it is intended to be connected to the ground voltage Vssl (e.g. ± 0V). The back gate - by the Bok and source electrodes are at the same potential, and without the substrate bias effect, the threshold voltage of the PMO S is low in absolute value, and as the drain-source current flows more in absolute value it is intended to be constructed. This, P Ueru volumes of large functional modules made form in a semiconductor integrated circuit device, since the heavy load capacitance of several hundreds p F, in order to control the P-well ^ position at a high speed, high drive M_〇 S Trang register of ability is because it is necessary.

However, the first signal ¾ voltage level converting circuit (block A 1) and the first buffer logic (block A2) first inverter Ichita circuit for waveform shaping which is provided between the (pro click A3) the back gate electrode of the PMO SQ 28 is connected to the power supply voltage Vddl (e.g. + 2 V) or the supply voltage Vdd 2 (eg + 4V) shown in FIG. 3, the ground voltage from the grounding voltage Vssl (e.g. ± 0V) Vss2 ( for example Li flows to one 2 V) - it is better to minimize the leakage current.

Further, to connect the back gate potential of the PMOS constituting the first buffer logic circuit (block A 2) to the source potential and the common ground voltage Vss 1 (e.g. Sat 0 V) ​​of each PMO S is, PMOSQ 24 , N Ueru area for Q 26 is required. This according to the load capacity of the P Ueru region functional modules, the first and Reia © preparative area of ​​each PMOS constituting the buffer logic circuitry (Block A 2), N Ueru area of ​​use when the substrate bias effect is present circuit configuration is determined by the correlation between the increase in Reiau preparative area due to the provision of the.

<Eighth embodiment>

The 1 5, the substrate bias control circuit for PMO S according to the eighth embodiment of the present invention is shown. Substrate bias control circuit of this embodiment, the sixth embodiment similarly to the second buffer logic (block B 2) each NM0 SQ 4 1 constitute the, Q 4 3 of the back gate one Bok electrode of the fourth embodiment force;, those that become connected to each to Vdd 1 (e.g. + 2V) which is the source potential of each NMO S. Incidentally, the circuit operation in the substrate bias control circuit of the eighth embodiment, shown in Thailand Minguchiya one preparative view of signal waveforms of FIG. 1 6, substrate Baiasu control circuit the same parts of the circuit operation is the second embodiment As described bear the same reference numerals for the omitted.

Substrate Baiasu control circuit of the eighth embodiment, the second buffer logic circuits in the substrate bias control circuit for PM 0 S described in the fourth embodiment: the drive capacity of (N ch Q4 1, Q 4 3) improving those which attained faster. That is, the substrate bias control circuit of this embodiment, the back gate of the second buffer logic (block B 2) each NMO SQ 4 1 to 樨成 a, Q 43 in the substrate bias control circuit shown in FIG. 7 - DOO electrode, is shall be connected to Vddl (e.g. + 2V) which is the source potential of each NMO S. Then, depending on that Roh Kkugeto and source electrodes are at the same potential, and without the substrate bias effect, is lower the threshold voltage of NMO S, and in which drain 'source current is constructed as flows more is there. This, N Ueru capacity of large functional modules which are formed in a semiconductor integrated circuit device hundreds since the p F or more heavy load capacity, in order to control the N Ueru potential at a high speed, high drive capability MOS transistor is because it is necessary.

However, the second signal voltage level conversion circuit (Block B 1) and the second buffer logic (block B 2) a second inverter Isseki circuit for waveform shaping which is provided between (pro click B 3) the back gate Ichito electrode of NMO SQ 45, the ground voltage indicated ground voltage Vssl (e.g. ± 0V), or in FIG. 1 Vss2 (e.g. - 2 V) is connected to a power supply voltage from the power supply voltage Vdd 2 (eg + 4V) Vdd 1 (e.g. + 2V) is better to minimize the leakage current flowing. Further, connecting the back gate Bok potential of each NM_〇 S constituting the second bus' couch logic circuit (block B 2) to the power supply voltage Vdd 1 of the source potential and the common of the NMO S (e.g. + 2 V) the, it is necessary to P Ueru area for NMO SQ 4 1, Q 43. However, this is in accordance with the load capacity of the N Ueru region of the functional module, and the layout area of ​​each NM_〇 S constituting the second buffer logic (block B 2) when the substrate bias effect is present, only the P circuitry in correlation with increased layout area due to the provision of the Ueru area is Ru is determined.

Having thus described the variations of the substrate bias control circuit, to wait, these circuits are not limited to being used as a substrate bias control circuit, For example other, it can be applied to a flash memory or the like, in this case can that you use as a level shifter as Inta one Fuesu different portions each other in voltage level, such as input and output circuits.

Next, the control Ueru potential by the substrate bias control circuit, by way of example for wiring Reiau Bok of MO S transistor is described which constitutes the functional module.

Ku ninth embodiment>

Next, a description will be given Reiau preparative function proc mass evening slice type semiconductor integrated circuit device in which a semiconductor integrated circuit device formed by the master slice method having a substrate bias control circuit according to an embodiment of the present invention.

Figure 1 8 is a ninth embodiment of the present invention! ! A Waru wiring layout diagram, FIG. 1 9 (a), and Bok wiring Reiau basic Seruhi Lee Nba Ichita circuit I NV 1 mass evening slice type semiconductor integrated circuit device shown in FIG. 1 9 (b) it is intended.

Shinporu Invar evening circuit I NV 1 is shown in FIG. 19 (a), in which the output signal X for the input signal A is output at inverted logic. A circuit configuration as shown in the illustrated this inverter circuit INV 1 in the circuit diagram of a transistor level diagram 1 9 (b). In FIG 1 9 (b), an input terminal to which an input signal A is inputted, is connected in common to the gate one bets terminal PM 0 SQ 2 of gate one Bok terminal and NMO SQ 1, the source terminal of PM_〇 SQ 2 There the power supply wiring layer Vddl, a back gate terminal are respectively connected via the N Ueru the power supply wiring layers Vdd 2. Similarly, NMO SQ 1 of the source terminal is grounded wiring layer Vss l, the ground wiring layer Vss2 through the back gate terminal P Ueru, each being electrically connected, the PMOS Q 2 drain terminal and the NMOSQ 1 and a drain pin, has become connected to each other at the output terminal of the output signal X is output. When wiring Reiau to Bok on one basic cell of the basic cell groups in which a plurality placing this Inbata circuit I NV 1 in a matrix, the wiring Reia © preparative shown in Figure 18.

Although transistors evening configuration of a basic cell shown in FIG. 18 is a company all sorts, where the gate electrode G 1, 03 and the gate electrode 01, G 3 gate - channel width is smaller than the gate electrode G5, the source 'drain electrode SD 1, SD 3, consisting of SD 5 and SD7 NM 0 SQ 1, the gate electrode G2 and G4, source and drain electrodes SD 2, SD 4 and PMOSQ2 a basic unit consisting of SD 6 Metropolitan (two PMO S + 2 wiring Reiauto using pieces of NMO S + 1 sub · NMO S) to the basic cell.

Figure 19 (a) on the basic cell, to constitute inverter evening circuit I NV 1 of (b), the a wiring layout shown in Figure 18. That is, the ground wiring layer V ss 1 is formed by the first metal wiring layer which is extended in the channel length direction of the MO S Bok transistors. Through the connection hole, the ground wiring layer Vssl, source electrodes SD3 of NMOSQ 1, and a source that is not used. Drain electrode SD 1 is it it electrically contacts.

Then, Ueru electrode B 1 represents extends in the channel width direction of the MO S transistor evening, the Ueru electrode B 1 and the first metal wiring layer M 13, and the second metal wiring layer of the upper layer than the first metal interconnect layer ground wiring layer Vss2 formed Te and the first metal wiring layer M 13 are electrically connected through it it connection holes H 1 and the connection hole C 1. Further, power wiring layer Vddl is formed by the first metal wiring layer which is extended in the channel length direction of the MO S transistor, the ¾ source wiring layer Vddl's PMO SQ 2 through a connection hole source - scan electrode SD 4 c also are each connected to the source-drain electrode SD 2 where and are not used, Ueru electrode B2 is extended in the channel width direction of the MOS transistor. Before SL Ueru electrode B 2 and the first metal interconnection layer Ml 4, and, 鼋源 wiring layer Vdd2 formed in the second metal interconnect layer and the first metal wiring layer M 14 is, connection hole H 2 and the connection hole They are each connected via a C 2.

Further, the inverter circuit I NV 1 input signal / M or to control, is applied to the first metal wiring layer M 1 1, the gate one gate electrode G4 of the gate electrode G 3 of NMO SQ 1 PMOS Q2, connection holes more be respectively electrically connected to the first metal ¾ line layer M 1 1 through the input signal a is applied to the gate Bok electrode G 3 and G 4. - How, the output signal X of which are output to the first metal wiring layer M 1 2, inverter - the evening output of I NV 1, the drain ¾ electrode SD 5 of NMO SQ 1, the PMO SQ 2 drain electrode SD 6 via a connecting hole, they are respectively connected to the first metal wiring layer M 1 2. Therefore, the NMO SQ 1 and PMO drain of each of the SQ 2 electrode SD 5, SD 6 is electrically commonly connected output signal X are formed.

The power wiring layer Vdd2 formed in the second metal interconnect layer, the ground wiring layer Vss2 is Ueru electrodes B 1 of NMOSQ 1 and PMO SQ 2, B 2 h wiring grid GX 1, placed on the GX 5 is, the wiring grid GX 2, GX 3, GX 4 power supply wiring layer V dd 2 which on is formed in the second metal interconnect layer, the placement and routing prohibited area of ​​the ground wiring layer V ss 2. Further, the power supply wiring layer Vdd 2, connection hole C 1 that connects the ground K line layer Vss2 to Ueru electrode of NMO SQ 1 and PMO SQ 2, C 2, H l, H 2 and the first metal wiring layer M 1 3, M l 4 is a wiring rule, formed by the first metal wiring layer a power supply wiring layer Vddl, between the ground wiring layer Vss 1 wiring grid GN 5, GN 6, GN 7 and wiring grayed rate de GP 1, a on GP 2, GP 3, is and disposed on the wiring grid GX 1 or GX 5.

Additionally, or according 'to the wiring rules, NMO SQ 1 and PMO SQ 2 of Ueru electrodes B l, connection hole C 2 is directly connected to the B 2 is one of the potential is formed by the first metal wiring layer a on adjacent Guritsu de GP 3 of the power supply wiring layer Vddl supply and and placed on the wiring grid GX 1. Connection hole C 1 further provides a on adjacent glycidyl tree de GN 5 of the ground wiring layer V ss 1 to supply the other potential is and disposed on the wiring grid GX 5.

These wiring rule is intended to ensure the interconnection grid GX 2, GX 3, functions by other second metals wiring layer on GX4 circuit internal signal wire or placement and routing area such functions proc interconnection networks There, similarly wiring grid GN 1, GN 2, GN 3 and the wiring grid GP 5, GP 6, GP 7 also function circuit internal signal lines by other first metal interconnect layer, or a functional proc between the signal wires and the like ensuring the placement and routing area in which also the in. By ensuring the placement and routing area, to ensure different PM0 SQ 2, new power wiring region for controlling the back gate electrode of the New Micromax 0 SQ 1 and the potential of the power supply wiring and ground wiring, to efficiently interconnect Reiauto it can be. Further, the arrangement of the connecting holes C 1 and C 2 are connected directly to Ueru electrode of NMO SQ 1 and PMO SQ 2 is formed by the first metal wiring layer which is extended in the channel length direction of the MO S transistor evening power wiring layers Vddl, the ground wiring layer Vss 1, the central portion relative MO S Tran Soo evening channel width or the wiring Guritsu de place and route closer to the center portion, applying a potential to the source electrode central portion of the MO S transistor by to Rukoto so, the effect of stabilizing the source potential of the MO S transistor evening. This means, contactor Tohoru on the relationship between the wiring Bidzuchi, 1 because Chikarasho can only be taken to avoid bias wiring 抵钪 in the power supply wiring layer Vddl and the ground wiring layer Vss 1, the channel width contactor Tohoru place on a close wire grid in the center portion or the central portion, it is possible to make uniform the distance between the contactor Tohoru and respective power wiring, it is possible to form a uniform resistance.

That is, M_〇 S configuration of the connection hole C 1 and C 2 are directly connected to Ueru electrode of the transistor also, MO S is a wiring grid close to the center portion or the central portion with respect to the channel width of the transistor power supply wiring layer Vdd 1 and which is adjacent grayed rate de ground wiring layer Vss 1, by placing on the GP 3 or GN 5 on the wiring Guritsu de GX 1 or GX 5, it is possible to stabilize the Ueru potential of MO S transistor .

Incidentally, the NMO SQ 1 and Ueru electrode B 1 of PMO SQ 2, B 2, connection hole C 1, C 2, HI, through the H 2, the first metal wiring layer M 1 3, M l 4 and power layer Vdd 2, instead of the method for each electrically connecting the ground wiring layer Vss2, the is more formed on the second metal wiring layer 鼋源 wiring layers Vdd 2, directly from the ground wiring layer V ss 2 NM 0 SQ 1 and Ru can be connected via a connecting hole to Ueru electrodes B 1, B 2 of the PMO SQ 2.

In the present embodiment, for one M OS is contactor Tohoru, since the provided one makes it possible to prevent latch-up.

In the present embodiment, by taking the basic cell that constitutes the inverter circuit it has been described their wiring Reiauto, Oite a plurality of basic cells formed on the chip, on the basic cells in each basic cell power supply wiring layer Vdd 2, it is possible to select whether or not to form a ground wiring layer Vss 2. The power supply wiring layers Vdd 2, in unnecessary basic cell functions of the ground wiring layer Vss 2, the power supply wiring layers Vdd 2, a second metal wiring layer formed as the ground wiring layer Vss 2, the power supply wiring layer Vddl, It can also be used as an auxiliary power source of the ground wiring layer V ss 1.

Ku first 0 Example>

Figure 20 is a wiring layout diagram of a first 0 embodiment of the present invention, the basic of FIG 2 1 (a), the master-slice type semiconductor integrated circuit device N the AND circuit shown in FIG. 2 1 (b) it is obtained by wiring layout on the cell. In FIG. 20, denoted by the same reference member overlapping the configuration, and FIG 8.

Figure 2 1 (a) has been shown symbols N the AND circuit, in which an output signal X with respect to the product of the input signal A and the input signal B is output at inverted logic. When indicating this NAND circuits in the circuit diagram of a transistor level the circuit configuration as shown in FIG. 2 1 (b). In FIG. 2 1 (b), the other input No. A is one input terminal to which the input is connected in common to gate terminals of the NM 0 SQ 3 of PM◦ SQ 4, the input signal B is input the input terminals are commonly connected to a gate one bets terminal of the gate terminal and NMO SQ 5 of PMOSQ 6.

Further, the PMO SQ 4, a source terminal connected to the power supply wiring Q 6 Vddl, a back gate terminal are respectively connected to the power supply wiring layer Vdd2 via the N Ueru. The source terminal of NMOS Q 5 is connected to the ground wiring layer Vss 1, the back gate bets terminal of NMO SQ 3, Q 5 are respectively connected to the ground wiring layer V ss 2 via the P Ueru.

Furthermore, along with NMO SQ 3 and Q 5 are connected in series, the drain terminal of the drain terminal and NMO SQ 3 of PMOSQ 4, Q 6 is, at the output pin of the output signal X is output, they are connected in common and it has a configuration.

When wiring Reiauto on one basic cell of N the AND circuits plurality located base cell groups Ma Bok Rikusu shape and become wiring Reiau Bok as shown in 320. Although transistors evening configuration of a basic cell shown in FIG. 20 is a company all sorts, in the same way as the basic cell shown in FIG. 1 8, the gate electrode G 7, G 9 and the gate electrode G 7, G 9 by remote channel width is smaller gate electrode G 1 1, source 'drain electrode SD 9, SD 1 1, SD 1 3 and the NMO SQ 3, Q 5 consisting of SD 1 5, gate one preparative 鼋極 G 6 及 beauty G 8, source and drain electrodes SD 8, SD 1 0 and PMOS Q 4, Q 6 basic unit (two PM0 S + two NM0S + 1 sub-NM_〇 S) to the basic cell comprising SD 12 using the wiring layout.

Figure 2 1 (a) on the basic cell, constituting an N the AND circuit shown in FIG. 2 1 (b) Then, the wiring layout shown in Figure 20. That is, the ground wiring layer Vssl is formed by first metal wiring layer which is extended in the channel length direction of the MO S transistor. Through the connection hole, the ground wiring layer Vss 1 is electrically connected to the source electrode SD 1 3 of NMO S 3.

Then, formed in Ueru electrode B 3 is extended in the channel width direction of the MO S transistor, the Ueru electrode B 1 and the first metal wiring layer 1 5, second metals interconnection layer of the upper layer than the first metal interconnect layer a ground wiring layer Vss2 and the first metal wiring layer M 1 5 being is connected thereto its been through a connection hole H 1 and the connection hole C 1.

The power supply wiring layers Vdd 1 is M_〇 S formed by the first metal wiring layer which is extended in the channel length direction of a transistor, ¾ himself power supply wiring layer Vdd 1 source electrode SD of PM 0 SQ 5 through a connection hole They are respectively connected to 8 and SD 1 2.

Then, Ueru electrode B 4 is extended in the channel width direction of the MO S transistor, the previous SL Ueru electrode B 4 first metal wiring layer M 1 7, a power supply wiring layer Vdd2 formed in the second metal interconnect layer first a first metal wiring layer M 1 7 are respectively connected via a connecting hole H 2 and the connection hole C 2.

Furthermore, the input signal A for controlling the N the AND circuit, is applied to the first metal wiring layer M 1 5, the gate electrode G 8 of the gate electrode G 9 and PMO SQ 4 of NMO SQ 3 is, through a connection hole are each electrically connected to the first metal wiring layer M 1 5. Furthermore, the input signal B is applied to the first metal wiring layer M 1 6, NMO SQ gate electrode G 6 of the gate electrode G 7 and PMO SQ 6 of 5, a first metal wiring layer M 1 through a connection hole each is electrically connected to the 6. In this manner, the input signal A is applied to the gate electrode G 8, G 9, wherein the input signal B is applied to the gate electrode G 6, G 7.

On the other hand, the output signal X of which are output to the first metal wiring layer M 1 9, at the output of NAN D circuit N the AND, the drain electrode SD 9 of NMO SQ 5, the drain of PM 0 SQ 6 electrode SD 1 0 via a connecting hole, are each connected to the first metal wiring layer M 1 9. Therefore, the NMO SQ 5 and PMO SQ respective drain electrodes SD 9 of 6, SD 10 are electrically connected in common output signal X are formed.

Power supply wiring layer Vdd2 formed in the second metal interconnect layer, the ground wiring layer Vss2 is, N MO SQ 3, Q 5 and PMOS Q4, Ueru electrode B 3 of Q 5, B 4 on the wiring grid GX 1 , placed and routed on GX 5, a wiring grid GX 2, GX 3, GX4 power supply wiring layer Vdd 2 that the upper is formed in the second metal interconnect layer, place-forbidden region of the ground wiring layer Vss 2 to. Further, the power supply wiring layer Vdd 2, NMO SQ 3 a ground wiring layer Vss2, Q 5 and PMOS Q4, connection hole C 1 that connects to Ueru electrode of Q 6, C 2, H 1, H 2 and the first metal interconnect layer M 1 8, M 1 9 is a wiring rule, the power source wiring layer is formed by the first metal wiring layer Vddl, wiring between the ground wiring layer Vss 1 Guritsu de GN 5, GN 6, GN 7 and on the wiring grid a on de GP 1, GP 2, GP 3, is and disposed on the wiring grid GX 1 or GX 5. Furthermore, according to the wiring rules, NMO SQ 5 and PMO SQ 4 of Ueru electrode B 3, connected directly connected to B 4 hole C l, C 2, one formed by the first metal wiring layer a on adjacent grid GP 3 of the power supply wiring layer Vddl supplying a potential, which and disposed on the wiring grid GX 1 or GX 5. Furthermore, an on adjacent Guritsu de GN 5 of the ground wiring layer V ss 1 supplies the other potential, which and disposed on the wiring grid GX 1 or GX 5.

These wiring rules, wiring grid GX 2, GX 3, GX 4 above: to ensure the placement and routing area such as the functional circuit internal signal lines by other second metals wiring layer, or the functional blocks between the signal lines is intended to likewise wiring grid GN 1, GN 2, GN 3 and the wiring grid GP 5, GP 6, GP 7 also function circuit internal signal lines by other first metal wiring layer, or between the functional proc it's also to ensure the placement and routing area such as the signal lines. By ensuring the placement and routing area, to ensure different PMO SQ 4, Q 6, NMO SQ 3, new power supply wiring area of ​​each back gate electrode for controlling the Q 5 is the potential of the power supply wiring and ground wiring, effectively it is possible to wiring layout. Further, the arrangement of the NMO SQ 3, Q 5 and PMO SQ 4, contact is directly connected to Ueru electrode B 3, B4 of Q 6 铳孔 C 1 and C 2, extending in the channel rectangular direction of the MO S transistor is the first power supply wiring layer Vddl is formed by a metal wiring layer and the ground wiring layer Vssl was, the wiring Guritsu de place and route closer to the center portion or the central portion, the channel width of the MOS transistor, the source of the MOS transistor by applying a potential to the electrode central portion component has an effect of stabilizing the source potential of the MOS transistor.

Similarly, the arrangement of the connecting holes C 1 and C 2 are connected directly to Ueru electrode of MO S Bok transistors also is the close interconnection grid to the central portion or central portion relative MO S transistor evening channel width a power supply wiring layer Vddl and neighbor grid of the ground wiring layer Vss 1, by placing on the GP 3 or GN 5 on the wiring grid GX 1 or GX 5, to stabilize the Ueru potential of the MOS transistor. That is, contactor Tohoru on the relationship between the wiring pitch, 1 Chikarasho only be in the can, such Ino take, in order to avoid the bias of the wiring resistance in the power supply wiring layer Vddl and the ground wiring layer Vss 1, wherein the channel width contactor Tohoru center have close to a portion or the central portion is disposed on the wiring Guritsu de, can be made uniform distance between the contactor Tohoru and respective power wiring, it is possible to ¾ formed an even resistance.

Incidentally, NMOS, Q 3, Q 5 and PM_〇_SQ4, the Ueru electrode B 3, B4 of Q 5, the connection hole C 1, C 2, HI, through the H 2, the first metal wiring layer M 18, M 19 and power wiring layers Vdd 2, a method for each electrically connecting the ground wiring layer Vss2, the formed by the second metal wiring layer power supply wiring layer V dd 2, directly from the ground wiring layer V ss 2 NM 0 SQ 3, may Q5 and PMOSQ4, be connected by connecting via the Ueru electrode B 3, B 4 to the connection holes of Q 6.

In the present embodiment, for one element contactor Tohoru, since the provided one makes it possible to prevent latch-up.

In the present embodiment, by taking the basic cells constituting the inverter evening circuit has been described their wiring Reiau Bok, Oite a plurality of basic cells formed on the chip, the basic cells in each basic cell power supply wiring layer Vdd2 above, it is possible to select whether or not to form a ground wiring layer Vss 2. The power supply wiring layers Vdd 2, in unnecessary basic cell functions of the ground wiring layer Vss2, the power supply wiring layer Vdd 2, a second metal wiring layer formed as the ground wiring layer Vss 2, as currently used power wiring layer Vddl, can also be used as an auxiliary power source of the ground wiring layer Vssl. Ku first Example 1>

Figure 22 is a wiring Reiau Bok diagram according to the first embodiment of the present invention, FIG. 23 (a), FIG. 23 (b) master slice N OR circuit shown in semiconductor integrated circuit on the primary cell in the device it is obtained by wiring layout to. In Figure 22, Figure 18, Figure 20 and the configuration, denoted by the same reference numerals overlapping members.

NOR in FIG 23 (a) it is limited to showing symbols of the NOR circuit, in which an output signal X with respect to the sum of the input signal A and the input signal B is output at inverted logic. When indicating this NOR circuit in the circuit diagram of a transistor level the circuit configuration as shown in FIG. 23 (b). In FIG. 23 (b), the one input terminal to which an input signal A is inputted, is connected in common to the gate one bets terminal of gate one Bok terminal and NMO SQ 9 of PMO SQ 8, the input signal B is input the other input terminal Ryo that - are commonly connected to gate one bets terminal of the gate pin and NMO SQ 7 of PMOSQ 1 0.

Further, connected to the source terminal connected to the power supply wiring layer Vddl of PMO SQ 8, together with the back-gate terminal of the PMO SQ8 and Q 10 are respectively connected to the power supply wiring layers Vdd 2 through N Ueru, NMO SQ 7 and Q 9 the source terminal are respectively connected to the ground wiring layer Vss 1, the back gate terminal Ru are respectively connected to the ground wiring layer Vss2 through the P Ueru.

Further with PMO SQ 8 and Q 1 0 are connected in series, are connected to the drain terminal of PMOSQ 1 0, the output terminal of NM 0 SQ 7 and drain terminals and the output signal X of Q 9 is output configuration and summer was (: there.

When wiring Reiauto on one basic cell Le plurality located base cell group the NOR circuit between Bok Rikusu shape, the wiring Reiau Bok as shown in Figure 22. The transistor configuration of the basic cell shown in FIG. 22 is a company all sorts, in the same way as the basic cell shown in FIG. 1 8, the gate electrode G 1 3, G 1 5, and the gate electrode G 1 3, G 1 gate one gate electrode G 1 7 channel width is less than 5, the source 'drain electrode SD 1 7, SD 1 9, consisting of SD 2 1 and SD 23 Metropolitan NMOSQ 7, Q 9, gate electrodes G 10 and G 1 2, the source 'drain electrode SD 14, SD 1 6 and made of SD 18 Metropolitan PMO SQ 8, Q 1 0 a basic unit (two PM 0 S + two NM 0 S + 1 sub · NM wiring Reiau to Bok using the basic cell to 〇 S). Figure 23 on the basic cell (a), when composing the NOR circuit NOR shown in FIG. 23 (b), the wiring layout shown in Figure 22. That is, the ground wiring layer V ss 1 is formed by a first metal wiring layer which is extended in the channel length direction of the MO S transistor evening, through a connection hole, the ground wiring layer Vssl, to-the NMOS Q 7, Q 9 source electrode SD 1 7 and SD 2 1 are electrically connected.

Then, Ueru electrode B 5 is extended in the channel width direction of the MO S transistor evening, the Ueru electrode B 5 and the first metal wiring layer M 23, the second metal wiring layer of the upper layer than the first metal wiring layer M 23 a ground wiring layer Vss 2 formed by a first metal wiring layer M 23 are each electrically connected through the connection hole H 1 and the connection hole C 1. The power supply wiring layer Vddl is formed by the first metal wiring layer which is extended in the channel length direction of the MO S transistor, serial power supply wiring layer Vdd 1 is connected to a source electrode SD 18 of PMO SQ 8 through a connection hole that.

Then, Ueru electrode B 6 is extended in the channel width direction of the MO S transistor, the Ueru electrode B 6 and the first metal wiring layer M 24, and the second metal interconnection power supply wiring layer Ru are formed in layer Vdd2 first and the metal wiring layer M 24, which are each connected via its connection hole H 2 and the connection hole C 2.

Furthermore, the input signal A for controlling the NOR circuit is applied to the first metal wiring layer M20, gate one gate electrode G 1 2 of the gate electrode G 1 5 and PMO SQ 8 of NMO S 9 is, via a connecting hole by each being electrically connected to the first metal wiring layer M 20, the input signal a is applied to the gate Ichito electrode G 1 5 and G 1 2. Then, the input signal B is applied to the first metal wiring layer M 2 1, NMO S gate electrode G 1 3 7 and PMOSQ 1 first metal wiring layer gate electrode G 10 via the connection holes of 0 M 2 by each being electrically be connected to 1, the input signal B is applied to the gate electrode G 1 3 and G 10.

On the other hand, the output signal X but is intended to be output to the first metal wiring layer M22, at the output of the NOR circuit NOR, and drain electrode SD 1 9 of NM_〇 SQ 9, the drain electrode SD of PMO SQ 1 0 14 through the connection hole, are each connected to the first metal wiring layer M 22. Therefore NM0S Q 7, Q 9 and PM0SQ 8, each of the drain fin electrode SD 1 9 of Q 10, SD 14 is conductive ¾ commonly connected to the output signal X are formed. The power wiring layer Vdd 2 is formed in the second metal interconnect layer, the ground wiring layer V ss 2 are, NM 0 SQ 7, <39 and? - 03 <28, Q 1 Ueru electrode B 5, B wire grid GX 1 on 6 of 0, is placed and routed on to the GX 5, wiring grid GX 2, GX 3, GX 4 on the second metal wiring power supply wiring layer Vdd 2 is formed in the layer, the placement and routing prohibited area of ​​the ground wiring layer Vss 2.

Moreover, the power wiring layer Vdd 2, connecting holes C 1 that connects the ground wiring layer Vss2 to Ueru electrode B 5, B 6 of NMO SQ 7, 09 and 1 ^ 0 SQ 8, Q 10, C 2, H 1, H 2, and the first metal wiring layer M 23, 24 is, by the wiring rules, the power supply wiring layer is formed by the first metal wiring layer Vddl, wiring between the ground wiring layer Vss 1 Guritsu de GN 5, GN 6, GN 7 and even on the wiring grit GP 1, GP 2, GP 3, is and disposed on the wiring grid GX 1 or GX 5.

Furthermore, according to the wiring rules, NMO SQ 7, Q 9 and PMO SQ 8, Q 1 Ueru electrode B 5, connected are connected directly to B 6 hole C 1, C 2 0, the first metal wiring a neighboring grid GP 3 of the power supply wiring layer Vddl supplies one potential is formed by a layer, which and disposed on the wiring grid GX 1 or GX 5. Furthermore, an on adjacent Guritsu de GN 5 of the ground wiring layer Vss 1 supplies the other potential, which and disposed on the wiring grid GX 1 or GX 5 arsenide.

These wiring rules, wiring grid GX 2, GX 3, GX 4 - To ensure placement and routing area such as the functional circuit internal signal lines by other second metals wiring layer, or the functional blocks between the signal lines , and the same wiring grid GN 1, GN 2, GN 3 and the wiring grid GP 5, GP 6, GP 7 also function circuit internal signal lines by other first metal interconnect layer, or a functional proc between signals intended ensuring the placement and routing area of ​​the wiring or the like as well to the. By ensuring the placement and routing area, to ensure a new power supply wiring region for controlling the back gate electrodes of different PMO SQ 8, Q 1 0, NMOS Q 7, Q 9 and the potential of the power supply wiring and ground wiring, efficiency it is possible to improve the wiring layout. . Also, the arrangement of the NMO SQ 7, Q 9 and PMO SQ 8, ^ El electrode B 5, connecting holes C 1 are directly connected to the B 6 of Q 10, and C 2, the channel length direction of the MO S transistor the extended first metallic interconnection power supply wiring layer is formed by layer Vddl and the ground wiring layer Vssl, central portion or place wire near the wiring Guridzu de the central portion, the channel width of the MO S transistor, MO S by applying a potential to the source electrode in mind portion of the transistor, the effect of stabilizing the source potential of the MO S transistor. That is, contactor Tohoru on the relationship between the wiring pitch, 1 because Chikarasho can only be taken in order to avoid bias in the wiring resistance that put the power supply wiring layer Vddl and the ground wiring layer Vss 1 wiring layer, said channel contactor Tohoru wiring grease close to the center partial or central portion of the width, placed on Seo de, can be made uniform distance between the contactor Tohoru and respective power wiring, it is possible to form a uniform resistance. Arrangement of the connection hole C 1 及 beauty C 2 to this and is also connected directly to Ueru electrode of MO S transistor also is the close interconnection grid to the central portion or centered portion to the channel width of the MO S Bok transistor it is an adjacent grid power supply wiring layers Vddl and the ground wiring layer Vssl, by placing the GP 3 or GN 5 on the wiring glyceraldehyde Tsu de GX 1 or GX 5, to stabilize the Ueru potential of the MOS transistor.

Incidentally, NMO SQ 7, Q 9, and Ueru electrode B 5, B 6 of PMOSQ 8, Q 1 0, the connection hole C 1, C 2, HI, through the H 2, the first metal wiring layer M 23, M24 及 beauty power supply wiring layer Vdd 2, a method for each electrically connecting the ground wiring layer Vss2, the formed by the second metals wiring layer power supply wiring layer Vdd 2, directly from the ground wiring layer Vss2 N MO SQ 7, Q but it may be connected by connecting through a connecting hole 9 and Ueru electrodes E 5, B 6 of PMOS Q 8, Q 1 0.

In the present embodiment, for one element contactor hole, since the provided one makes it possible to prevent latch-up.

In the present embodiment, by taking the basic cell that constitutes the inverter circuit has been described As a wiring layout, Oite a plurality of basic cells formed on the chip, on the basic cells in each basic cell power supply wiring layer Vdd 2, it is possible to select whether or not to form a ground wiring layer Vss 2. The power supply wiring layers Vdd 2, in unnecessary basic cell functions of the ground wiring layer Vss2, the power supply wiring layer Vdd 2, a second metal wiring layer formed as the ground wiring layer Vss 2, as currently used power wiring layer Vddl, can also be used as a power source for an auxiliary ground wiring layer Vss 1. Ku the first and second embodiments>

Functional module in a semiconductor integrated circuit device of the present invention are those having a variety of functions, for example, a logic circuit, ROM, RAM, MP Ji can be configured by the semiconductor integrated circuit device such as a standard cell. Again, by providing a substrate bias control circuit on a chip, and controls the back gate electrode by the external power supply, using a substrate bias effect, controls the operation of the MO S transistor, functions with high performance as described above It realizes the block. In the present embodiment, the functions Proc of the onset Ming semiconductor integrated circuit device, a semiconductor integrated circuit device as applied to RAM circuit will be described.

Figure 24 is a wiring Reiau preparative diagram according to the first and second embodiments of the present invention, the RAM circuit shown in FIG. 25 (random access memory) on the basic cell functions proc master slice type semiconductor integrated circuit instrumentation 置内it is obtained by wiring Reiau door. And have you in FIG. 24, 18, 20, 22 and the configuration, the same members denoted by an code. Figure 25 is shows the RAM circuit formed by connecting one source ■ drain electrodes Rye busses, NMOS trans mission to sweep rate Tutsi control between line busses and the memory cell by Lai preparative signal W - gate Q l 1, Inba Isseki circuit constituting the NMOS transmission gate Q 1 1 connect one source 'drain electrode, the memory cell by the inversion signal XW Rye preparative signals W and rye preparative signal W. It includes transmitters cushion gate consisting PMO SQ 1 2 and NMO SQ 13 to sweep rate Tutsi control between INV 2, INV 3. Further, the RAM circuit amplifies the signal in a note Riseru, 'and Inbata circuit I NV4 to drive the bus, lead. Source path' Li one de connect one drain electrode, Li one by the read signal R to sweep rate Tutsi control between de paths and memory cell NMO S transmitters cushion 'is intended to include a gate Q 1 5.

If you wire Reiauto the RAM circuit by using two basic cell Le in cell group in which a plurality arranged in a matrix, the wiring layout shown in Figure 24. Although transistors evening configuration of a basic cell shown in FIG. 24 is a company all sorts, the basic unit of the same as the basic cell shown in FIG. 1 8 (two PMO S + two NMO S + 1 sub. NMO and it has a S). When configuring the RAM circuit shown in Figure 25 on the basic cell, the wiring layout shown in Figure 24.

That is, Ueru electrode B 7 of NMO S in R AM circuit is extended in the channel width direction of the MO S transistor, the Ueru electrode B 7 and the first metal wiring layer M25, a second metal layer above the first metal interconnect layer a ground wiring layer Vss 2 formed by the wiring layers and the first gold 厲配 line layer M 2 5 are electrically connected through it it connection holes H 1 and the connection hole C 1. Then, Ueru electrode B 8 of PMO S in the RAM circuit is extended in the channel width direction of the MO S transistor evening, the Ueru electrode B 8 and the first metal wiring layer M 26, an upper layer than the first metal interconnect layer a power supply wiring layer Vdd2 formed in the second metal interconnect layer and the first metal wiring layer M 2 6 is electrically connected through it it connection holes H 2 and SeMMitsuruana C 2. Accordingly, trans Mitsu Chillon 'gate Q 1 1 constituting the RAM circuit shown in FIG. 25, 1 5 and inverters Ichita circuit I NV 2~: [NMO S back gate electrode of the NV 4 to the ground wiring layer Vss 2 connected, PMO S back gate Ichito electrode has a connected configuration to the power supply wiring layers Vdd 2.

Power supply wiring layer Vdd 2 supplied by the second metal wiring layer, the wiring grid GX 1 on Ueru electrode B 7, B 8 of NM_〇 S and PMO S of the ground wiring layer Vss 2 during RAM circuit, GX 5 arranged wires on the wiring grid GX 2, GX 3, 0 say yes 4 and 0 say yes 6, GX 7, GX 8 on the second metal interconnection power supply wiring layer is formed by layer Vdd 2, ground wiring layer Vss 2, the placement and routing prohibited area.

Moreover, the power wiring layer Vdd 2, connecting holes C 1 that connects the ground wiring layer Vss2 to Ueru electrode B 7, B 8 of NMO S and PM_〇 S in the RAM circuit, C 2, H 1, H 2 and the first metal interconnection layer M25, M26 is the wiring rule, the power source wiring layers Vdd 1 being subjected fed by the first metal wiring layer, between the ground wiring layer Vss 1 wiring grid GN 5, GN 6, GN 7 and on the interconnection a on grid GP 1, GP 2, GP 3, is and disposed on the wiring Guritsu de GX 1 or GX 5. Furthermore, according to the wiring rules, NMO S and PM_〇 Ueru electrode B 7, B 8 directly connected thereto connected pores CI, C 2 of S in R AM circuit is formed by the first metal wiring layer are arranged as much as possible to adjacent wiring glyceraldehyde 'on source de the power source wiring layers Vdd 1 or ground wiring layer Vss 1 supplies the other ¾ position, supplies one of the potential Te. These wiring rules, wiring grid GX 2, GX 3, 0 4 and 0 6, GX 7, function by another second metal wiring layer on the GX 8 circuit internal signal wiring or a functional pro, Seok between the signal lines, for example read Lai preparative control signal shown in FIG. 24 R, W, is to ensure the placement and routing area of ​​XW like. In the same way the wiring grid GN 1, GN 2, GN 3 and wiring Guritsu de GP 5, GP 6, GP 7 also function by other first surplus genus wiring layer circuit internal signal wiring or functional Proc interconnection networks, e.g. it is intended to ensure the line busses and placement and routing area such as a read bus shown in Figure 24. Therefore, PMO S in different RAM circuit and the potential of the power supply wiring layer and the ground wiring layer, to ensure a new power supply wiring region for controlling the back gate electrode of the NMO S, efficient wiring layout for it is possible.

Further, the arrangement of the connecting holes C 1 and C 2 are connected directly to Ueru electrode of NMO S and PMO S, the power supply wiring layer is more formed on the first metal wiring layer which is extended in the channel length direction of the MO S transistor Vddl and the ground wiring layer Vss 1, wiring grid to place and route closer to the center portion or the central portion is W the channel width of the MO S transistor, by applying a potential to the source electrode central portion of the MO S transistor, M the source potential of the OS transistor there is an effect of stabilizing. That is, contactor walk Lumpur on the relationship between the wiring pitch, 1 because Chikarasho can only be taken in order to avoid bias in the wiring resistance of the power supply wiring layer V ddl and ground wiring layer Vss 1, wherein the channel contactor bets Hall was placed near the wiring grid on the center portion or the central portion of the width, it is possible to make uniform the distance between the contactor Tohoru and 夬 's power supply wiring, it is possible to form a evenly resistance.

This and also the arrangement of the connecting holes C 1 及 beauty C 2 which is directly connected to Ueru electrode of MO S Bok transistors Similarly, wiring grid close to the center portion be properly central portion with respect to the channel width of the utmost MO S transistor by disposing, it is possible to stabilize the © El potential of MO S transistor. Note that Ueru electrode of NMO S and PM_〇 S in R AM circuit, connecting holes CI, C 2, HI, through the H 2, the first metal wiring layer M 25, M 26 and the power supply wiring layer Vdd 2, ground how each electrically connecting the wiring layer Vss 2, the formed by the second metal wiring layer power supply wiring layer Vdd 2, directly from the ground wiring layer V ss2, Ueru of NMO S and PM 0 S in R AM circuit but it may be connected by connection through the connection hole to the electrode.

In the present embodiment, for one element contactor Tohoru, since the provided one makes it possible to prevent latch-up.

In the present embodiment, by taking the basic cells constituting the inverter 问路 has been described their wiring Reiauto, Oite a plurality of basic cells formed on the chip, the basic cells in each basic cell power supply wiring layer Vdd2, it is possible to select whether or not to form a ground wiring layer Vss2. The power supply wiring layers Vdd 2, in unnecessary basic cell functions of the ground wiring layer Vss2, the power supply wiring layer Vdd 2, a second metal wiring layer formed as the ground wiring layer Vss2, power supply, such as is currently used wiring layer Vddl, can also be used as an auxiliary power source of the ground wiring layer Vssl.

<First Embodiment 3>

Next, an application example relates to a substrate bias control circuit and the functional modular Yule in the semiconductor integrated circuit device of the present invention and power supply to the functional module of a power supply formed by the substrate bias control circuit, the first 3-1 4 embodiment It is described in the example. Configuration of these substrate bias control circuit uses both the substrate bias control circuit for NM_〇 S and for PMO S, for all functional modules in a semiconductor integrated circuit, which optimally controls the power and speed dynamically it is.

Figure 26 is a block diagram of the substrate bias control circuit according to the first third embodiment of the present invention, and MO S transistor evening sectional structure constituting the functional module 27 is shown. The semiconductor integrated circuit device of this embodiment, using both the substrate Baiasu control circuit for NMO S and for PMO S of the first to eighth embodiments described above, for all the functional modules of the semiconductor current product circuit device, the power and speed is to optimal control dynamically. That is, in the case of operation modes, is operated by utilizing the MO S preparative Rungis evening characteristic of the high-driven, during the standby mode, by being configured such that the M OS transistor characteristics of low power consumption it is an feature. In the substrate bias control circuit, as described in the first to 1 2 Example 1 based power Vddl and supplied to a portion of the first metal wiring layer (power supply wiring layer Vddl and the ground wiring layer Vss 1) a same potential or different potentials and Vssl, and is supplied to the second metal wiring layer (power supply wiring layer Vdd2 and the ground wiring layer Vss2), in which 2 system power supply Vdd2 及 beauty Vss 2 is formed. That is, at a substrate bias control circuit, 2 system ¾ source Vss2 to P Ueru of NM_〇 S in all functions module is supplied, in which two system power supply Vdd2 is supplied to the N Ueru of PMO S. Then, 2 system power Vss2 formed at a substrate Baiasu control circuit for NMO S not only are subjected supply all the functional modules is also supplied to the substrate bias control circuit for PMO S. Similarly, 2-related power supply Vdd2 formed at a substrate bias control circuit for PMO S is not only applied to full function module, it is also supplied to the substrate Baiasu control circuit for NMO S.

The following describes the power supply to the functional module from the substrate bias control circuit of FIG. 26 (a).

Substrate bias control circuit of this embodiment, the chip. Rice one enable signal CE input from the external device is input signal voltage level conversion circuitry LV 0 N in the substrate bias control circuit for NM_〇 S, the first first buffer logic circuit connected to the first signal voltage level conversion circuit LV 0 N or the first buffer logic circuit and the first waveform shaping Inbata circuit L 0 G 0 2 system power by N Vdd 2 and Vss2, in which the potential of the control.

Here, the signal voltage level converting circuit LV0 corresponds to the block A 1 and block B 1 of the first to eighth embodiments, although not particularly described separately in the figure, the substrate bias control for the NMOS and PMO S as those with both the first and second signal voltage level converting circuits respectively provided in the circuit, described in the first 3-14 embodiment. In the bright Saisho in, for the first signal voltage level conversion circuit in the substrate bias control circuit for NMO S, denoted by the N shown as "LV 0 N", in the case of a PMOS, the denoted by the P ": show as LVO Pj.

Furthermore, the first buffer logic circuits or the first buffer logic circuit and the first inverter Ichita circuit LOG O waveform shaping, the block A 2 of the first to eighth embodiments, the block B 2 and the block A 3 corresponds to the block B 3, in particular but not listed separately in the drawings, the NMO S and for PMO is it to the substrate bias control circuit for S first and second signal levels are therewith provided conversion It is connected to the circuit, respectively the first and second buffer logic circuits provided or the first, second buffer logic circuits and the first, with both the second waveform shaping Inba Isseki circuit It is described in the 13 to 1 4 example as things.

In the in the specification, the substrate bias control circuit for NMO S, for the first buffer logic circuits or the first buffer logic circuit and the first waveform shaping Inba capacitor circuit, denoted by the N shown as "L_〇_G 0N", in the case of a PMO S shows as denoted by the P "log0 Pj.

Chip. By Ineburu signal CE is set to the high level, the semiconductor integrated circuits device is set to the activated mode, the chip 'Ineburu signal CE is input to the signal voltage level conversion circuit LV 0 N for NM_〇_S , its output signal is manpower in the first buffer logic (or the first buffer logic circuit and the first waveform shaping Inba data) LOGO N. By ¾ Symbol LOG ON, the voltage Vpw is formed to control the potential of the P Ueru a back gate electrode of the NM 0 S which is formed on the entire functional module of a semiconductor integrated circuit device, is input to function module . Further, the voltage Vpw controlling a potential of said P Ueru (power supply voltage Vdd 2) is connected via a P © E Le, it is entered in the second signal voltage level conversion circuit LV 0 P for PMO S.

At the same time the Chibbu-Ineburu signal CE is input to the second signal voltage level conversion circuit LV 0 P for PMO S, the output signal, a second buffer logic (or the second buffer logic and orthopedic second waveform Inba Isseki circuit) is inputted to the L0 GO P. Then, the by LOG OP, voltage Vnw controlling the potential of the N Ueru a back gate Bok electrode PMO S which is formed on the entire functional module halves integrated circuit device is formed, is input to the function module. Further, the voltage Vnw controlling the potential of the N Ueru (ground voltage Vss2) via the N Ueru, is also input to the first signal voltage level conversion circuit LV 0 N for NMO S. That is, the 1-system power supply Vddl the N Ueru of PMO S (e.g. 3V) and the same potential Vdd 2 (3 V) is applied, the P Ueru of NMO S 1 system power supply Vss 1 (for example, 0V) the Vss 2 (0 V) is applied potentials.

Thus, M_〇 S when the source electrode and the back gate voltage of the same potential to one Bok electrode of the transistor is applied, the sub-Threading Scholl de characteristics of MO S transistor in FIG. 32 (a), FIG. 32 (b) condition P 1 and N 1 becomes as shown, the threshold voltage of the MO S transistor in this state is low in absolute value, the drain current is large characteristic and ing.

On the other hand, when the chip 'rice one enable signal CE is mouth first level, a semiconductor integrated circuit device is set to the standby mode, first, the second signal voltage level conversion circuit, the first, second logic circuit or first, second logic circuit and the first, the second waveform shaping inverters one capacitor circuit performs i No. formed as described above, voltage Vnw controlling the potential of the N Ueru, the potential of the P Ueru control to voltage Vpw is formed. The voltage Vnw controlling the potential of the N © E Le, voltage Vpw controlling the potential of the P Ueru is input to respective function modules, NM_〇 S and for the substrate bias control circuit for PM_〇 S It is human power to.

That is, the the N Ueru of PMO S 1 system power supply Vdd 1 (e.g. 3V) 2 system power high-voltage level than Vdd 2 (e.g. 5 V) is applied, the system 1 to the NMOS of the P Ueru supply Vss l (e.g., 0V) 2 system power supply Vss 2 of a low potential (eg, single 2 V) is applied than.

Thus, the voltage of the high potential is applied to the back gate Ichito electrode to the source electrode of the PMO S, the voltage of the low potential is marked addition to the back gate one Bok electrode to the source electrode of the NMO S, M 〇 sub Threading Scholl de characteristics of S transistor, FIG. 32 (a), 3 2 state P 2 shown in (b), P 3 and N 2, N 3, and the threshold voltage of the MO S transistor Te this state odor There high in absolute value, the off current is very small characteristics.

Therefore, in the case of a semiconductor integrated circuit device or operation mode, it becomes MO S tiger Njisuta characteristic of the high-driven, the semiconductor integrated circuit device in the opposite case the standby mode, the MOS transistor characteristics arsenate of low power consumption.

Further, FIG. 26 (b) chip rice one enable signal CE and the semiconductor integrated circuit generated in the device the sleeve-mode control signal SM or power down signal PD is input to the selector click evening first circuit SEL 0, husband output signal from the selector first circuit SEL 0 are the respective signal voltage level conversion circuit LV. 1 to 3 and Ba Uz off § logic (or server Uz file logic and waveform shaping Inba Ichita circuit) LOG 1 ~ 3 s Therefore to be entered, but to switch each of the functional modules of a semiconductor integrated circuit device to the operation mode and the standby mode. Then, the control of the PMO S and NMOS back gate electrodes, the voltage Vnwl~3, 'a ¾ pressure Vpw. 1 to 3 is supplied to Ueru each functional module, as described above, shall be made for each functional module it is.

In this case, it is possible to control the back gate Ichito electrode of PMO S and NMO S for each functional module, MO S transistor structure of the semiconductor integrated circuit device, shown in FIG. 27 (a) or FIG. 27 (b) made to be.

MOS transistor structure in the functional modules shown in FIG. 27 (a) is a triple Ueru structure to separation from the substrate of the semiconductor integrated circuit device both N Ueru of P Ueru and PMO S of NM 〇 S that. For example, if the substrate SU B 1 of the semiconductor integrated circuit device is a P substrate, in order to separate the P Weru PWE L 1 to form the NMO S from the substrate SU B 1, Bari' de layer VA formed by N is It is formed so as to surround the P Ueru PWE L 1. Furthermore, this T Bari' de layer VA is the N Ueru NWEL 1 are formed separately so as to not become common potential and N Ueru different functional blocks. Conversely, although not shown, if the substrate SUB 1 of the semiconductor integrated circuit device is a substrate N- is order to separate the N Ueru NWE L 1 that PMO S is formed from the substrate SUB 1, the P Bari' de layer VA is formed so as to surround the N Weru NWE L 1. Further, second P Bari' de layer VA is formed separately so as to not become P © E Le a common potential of the different functions proc is a P Ueru PWE L 1.

MO S transistor structure in the functional modules shown in FIG. 27 (b) likewise the triple Ueru structure to separate both N Ueru of P Ueru and PMO S of NMO S from the substrate of the semiconductor integrated circuit device It is. For example, if the board S UB 2 of the semiconductor integrated circuit device is a P- substrate in order to separate the P Weru P WE L 2 forming a NMO S from board S UB 2, N Ueru NWE L 2 is P Weru PWE L 2 depth rather are formed from and are separated so as to surround the P Ueru PWE L 2. Further, the N Ueru NW EL 2 are formed separately so as that do not N Ueru other different functions proc a common potential. Conversely, although not shown, since the substrate SUB 2 of the semiconductor integrated circuit device in the case of N substrate, separating the N Ueru NWE L 2 which PM_〇 S is formed from the substrate SUB 2, P Ueru P WE L 2 There are deeper than N Ueru NWE L 2, it is separated so as to surround the front Symbol N Ueru NWE L 2. Further, the P Ueru PWE L 2 is formed separately so as to not a P Ueru other different functional blocks to a common potential.

As mentioned above, according to the semiconductor integrated circuit device of this embodiment, to ensure different PMO S, a new power supply wiring area of ​​each back gate Ichito electrode control of NMO S is the potential of the power supply wiring and ground wiring efficiently with facilitating the Reiau Bok design of the power supply and signal wiring by providing a wiring Reiau Bok wiring rules, it has the effect of realizing high speed and low power consumption in the standby during operation at the same time .

Ku first 4 embodiment>

Figure 28 is a block diagram of the substrate bias control circuit according to a fourteenth embodiment of the present invention, and the cross-sectional structure of the MO S transistor constituting the function module is shown. The semiconductor integrated circuit device of this embodiment, by using either the substrate bias control circuit for NMO S and for PMO S according to the first to eighth embodiments described above, all the features of the semiconductor current product circuit device module: whether Re this formed NM 0 S or PM 0 S noise and power consumption and speed as to optimally control dynamically. Ie, in the case of operation modes are operated by utilizing the MO S transistor characteristic of the high-driven, the only one of the low power consumption type of the PMO S or NMO S when in the standby mode MO it is characterized in that it has configured to be S transistor t property.

In the substrate bias control circuit, as described in the first to twelfth embodiment, the system 1 is supplied to a portion of the first metal wiring layer (power supply wiring layer Vddl and the ground wiring layer Vss 1) Power Vddl and Vss 1 the same potential or a different potential, and is supplied to the second metal wiring layer (power supply wiring layer Vdd2 or ground wiring layer Vss2), one of which is formed of the two-system power supply V dd2 or Vss2 it is intended. That is, at a substrate by § scan control circuit, in all functional modules, NMO 2 system power supply Vss 2 to P Ueru of S, or one in which two system power Vdd2 is supplied to the N Ueru of PMO S (and, If 2 system power Vss2 is formed at a substrate bias control circuit for NMOS, the 2 system power Vss2 is not only applied to full functional module, also supplied to the substrate bias control circuit for PMO S that. Similarly, when the 2-system power supply Vdd2 is formed at a substrate Baia scan control circuit for PMO S, the 2 system power supply Vdd 2 is not only applied to full function module, for NMO S It is also supplied to the substrate Baiasu control circuit.

The following describes the power supply to the functional module from the substrate bias control circuit of FIG. 28 (a).

In this embodiment, the substrate bias control circuit that form only two system power supply Vdd2 supplied to N Ueru of PM_〇 S will be described by way of example.

Substrate bias control circuit of this embodiment, the chip rice one enable signal CE input from the external device is input to the second signal voltage level converting circuit LV 4 P in the substrate bias control circuit for PM_〇 S , the second signal voltage level conversion circuit LV 4 second buffer logic circuit or the second buffer logic circuit and the second waveform shaping Inba Ichita circuit connected with the P LOG 4 P by 2 system power supply Vdd 2 potential of is intended to be control.

By chip 'Ineburu signal CE is set to the high level, the semiconductor integrated circuits device is set to the operation mode, the chip Ineburu signal CE is input to the second signal voltage level conversion circuit LV4 P for PMO S , its output signal is input to the second buffer logic (or the second buffer logic circuit and the second waveform shaping fin Ba Ichita circuit) L0G4 P. Then, by the L0G4 P, the voltage Vnw formed to control the potential of the N Ueru back gate is one Bok electrode of PMO S which is formed on the entire 璣能 modules in a semiconductor integrated circuit, it is entered into the function module. Further, the voltage Vpw (power supply voltage Vdd 2) for controlling the potential of the P Ueru via P © E Le, is also input to the first signal voltage level conversion circuit LV 4 N for NMOS i.e., for PMO S because of the use of only the substrate bias controlling circuit, both the N Ueru of PMO S 1 system power supply Vdd 1 (e.g. 3V) and 2 system power supply Vdd 2 of the same potential (3 V) is applied, P of NMO S Ueru same 1 system power Vssl (e.g. 0 V) ​​is applied to the source electrode of NMO S. Thus, if the voltage of the source electrode and the back gate electrode same potential MO S transistor is applied, the sub-Threading Scholl de characteristics of MO S transistor is shown in FIG. 32 (a), FIG. 32 (b) condition P 1 and the state N 1, and the threshold voltage of the MO S transistor Te this state smell is low in absolute value, the drain current becomes large properties.

On the other hand, when the chip 'rice one enable signal CE is mouth first level, a semiconductor integrated circuit device is set to the standby mode, the second issue the voltage level conversion circuit for PMO S, the second buffer logic circuit or the second buffer logic circuit and the second waveform shaping inverter - a capacitor circuit performs a signal formed as described above, the voltage to control the potential of the N Ueru Viiw (power supply voltage Vdd 2) through the N Ueru, each function is input to the module, is inputted to the substrate bias control circuit for PM_〇 S.

That is, N Ueru of PMO S with Vdd2 high photoelectric position than 1 system power supply Vddl (e.g. 3V) (e.g. 5V) is applied, the P Ueru of NMO S aforementioned 1 system power Vssl (0 V) There is applied.

Thus, when the voltage of the high potential to the source electrode of the PMO S is applied to the back gate Ichito electrode, the sub-Threading Scholl de characteristics of PM_〇 S, the state P 2 or P is shown in FIG. 32 (a) 3 becomes, in this state, but Sabusuretsusho field characteristics of NM OS does not change, high in only the absolute value the threshold voltage of the PMOS transistor, O off current is very small characteristics.

Therefore, if the semiconductor integrated circuit device is in operation mode, high-driven becomes MOS tiger Njisuta characteristics, if the semiconductor integrated circuit device in the opposite standby mode, PM_〇 S only MO S transistor of low power consumption the characteristic.

Further, FIG. 28 (b), similarly to FIG. 26 (b), the sleeve mode one de control signal generated by the chip 'rice one enable signal CE and the semiconductor integrated circuit device SM or power • down signal PD is input to the selector first circuit SE L 1, the selector first circuit output signal from the SEL 1 is the signal voltage level conversion circuit LV 5 to 7 and the buffer logic (logic circuit and a waveform shaping Lee members evening circuit) LOG5~7 in by being respectively input, it is intended to switch each of the functional modules of a semiconductor integrated circuit device during mode operation mode and standby. Then, as in FIG. 28 (b) FIG. 28 (a), the semiconductor integrated circuit device, and a system power supply Vddl and Vssl, 2 system is the same potential or different potentials this 1 system power supply Vddl supply Vdd 2 There has been provided with a substrate Heyer scan control circuit to be formed. Again, the control of the back gate potential of PM_〇 S, voltage Vnwl~3, supplies a voltage Vpwl~ 3 to Ueru each functional module, as described before mentioned, and performs each function module.

As described above, in the present embodiment it has been described by way of example and have control Nitsu potential of N Ueru for controlling the back gate potential of the PMO S using substrate bias control circuit for PMO S instead control the NMOS back gate potential using substrate Baiasu control circuit for NMO S, i.e. it is also possible to control the potential of the P Ueru. Further, in this case also it is possible to obtain the same effect as the case of applying the present invention to the PMOS substrate bias control circuit described above.

In this case, the control of the back gate electrode of the PMO S, as described above, it is possible to control each function module, MO S Trang register structure of a semiconductor integrated circuit device, shown in FIG. 28 (c) made to be.

Figure MOS transistor structure in the functional modules shown in 28 (c), the required triple Ueru structure for separation from the substrate of the semiconductor integrated circuit device both N Ueru of NM 0 S of P Ueru and PMO S no. For example, if the substrate SUB 3 of the semiconductor integrated circuit device is a P- substrate, since Ueru the back gate Bok electrode is controlled such only N Ueru IS 5 to PM 0 S is formed, the semiconductor shown in FIG. 28 (c) in integrated circuit device, it is not necessary to separate both the P Ueru PWEL3 and N Ueru NWEL 3 from the substrate of the semiconductor integrated circuit device.

Conversely, in the semiconductor integrated circuit device shown in FIG. 28 (c), if the substrate SUB 3 is a substrate, the 1-system power supply Vddl and Vss 1, at the same potential or different potentials this 1 system power supply Vss 1 by having a substrate bias control circuit with 2 system power Vss2 is formed, Ueru the back gate one Bok electrode is controlled is only P Ueru PWE L 3 which NMO S is formed. Therefore, it is not necessary to separate both the P Ueru As shown in FIG. 28 (c) P WE L 3 and N Ueru NWE L 3 from the substrate of the semiconductor integrated circuit device.

As described above, according to the semiconductor integrated circuit device of this embodiment, different P MO S is the potential of the power supply wiring and the grounding wiring, either a new power supply wiring of the back gate one Bok electrode control of NMO S while by limiting to either without changing the MO S transistor structure, having effect of realizing high speed and standby to reduce power consumption during operation at the same time.

Further, either controls the back gate of both NMO S · PM_〇 S, - Kata MO S DOO or controlling the back gate one Bok of transistor of the design phase, selecting the shift had the specifications of products it is also possible. For example, if you control the back gate of PM_〇 S only, it is possible to lower the manufacturing cost. Further, in the design phase, the specification of the product, select only the function modules requiring the back gate control, only to form a Ueru before Symbol function module, the NMO S · PMOS both or one of the MOS transistors it is also possible to control the Bakkuke Ichito.

Ku the first 5 embodiment>

Figure 29 is a power supply wiring ray Out of the semiconductor integrated circuit device according to the first 5 embodiment of the present invention is shown.

The FIG. 29 (a), the in the ninth to 1 second embodiments described above, is extended in the channel length direction of the MO S transistor to be supplied to a plurality of elementary cells placed in a matrix, the first metal 1 system power supply wiring Vddl and Vss 1 formed by a wiring layer, M 0 S 2 system power is extended in the channel width direction than the first metal interconnect layer is formed by the second metal wiring layer of the upper layer of the transistor power wiring lines Vdd 2 and Vss 2 Les Iau Bok is shown.

On the other hand, in FIG. 29 (b) 1-based auxiliary power Vddl for a system power supply wiring Vdd 1, Vss 1,, Vss 1 ', 2 system power supply wiring Vdd 2, Vss 2 against 2 based auxiliary power supply Vdd 2, It has been shown what Vss2 'is wiring layout.

The 1-based auxiliary power wiring Vdd 1 ', Vss 1' is extended in the channel width direction of the MO S transistor, which is formed by the second metal wiring layer, similar to the 2 system power supply wiring Vdd 2 and Vss 2 the one in which is arranged the wiring on the wiring grid on Ueru electrode of MO S transistor.

Also, 2-based auxiliary power wiring Vdd 2,, Vss 2, is extended in the direction of the channel length M 0 S transistors are shall be formed by the third metal wiring layer of the upper layer than the second metal wiring layer, the 3 is intended to be wired on the placement grid that are not used in the signal lines by a metal wiring layer.

The 1-based auxiliary power wiring and 2 system power supply wiring is to prevent against 1 system and 2 systems of potential is supplied from the outside, the semiconductor integrated circuit device, in particular a voltage drop in the center.

<Sixteenth embodiment and the seventeenth embodiment>

FIG 30, the method of forming the MO S transistor in the semiconductor integrated circuit device according to a sixteenth embodiment and the seventeenth embodiment of the present invention is shown. Using one two rectangular or any of the 13 to 14 actual 施例 NMO S board Baiasu control circuit and the PMO S substrate bias control circuit of the foregoing, the functional module configured in a semiconductor integrated circuit device If optimum control power consumption and speed dynamically, especially in the semiconductor integrated circuit device and, particularly to a semiconductor integrated circuit device which emphasizes the power consumption of functional modules importance to speed up the function module, formed of MOS transistors it is desirable to divide the way clear.

The semiconductor integrated circuit device shown in FIG. 30 (a) a semiconductor body integrated circuit device of the thirteenth embodiment of the present invention, a semiconductor integrated circuits devices importance to speed up the particular functional module.

For example, a functional module forming region constituting a predetermined function module, semiconductor input and output signals of the function module, configured with an external device centers face to output circuit forming region (peripheral circuit region) I 0 integrated circuit devices, and sensitive input circuitry, M0S Bok Rungis evening threshold voltage output circuit Ru is formed in a forming region in which the output circuit and the like of the high driving capability are formed, noise reduction, low-power aspect from than functional modules forming region MO, is formed threshold voltage at a first threshold voltage Vthl higher in absolute value (for example ± 0. 7V).

Then, MO S transistor evening threshold voltage of which is formed on the functional module formation regions MO with emphasis on speed, the first threshold voltage Vthl the MO S Trang Soo evening formed in input-output circuit forming region I 0 ( for example ± 0. 7V) than, be formed at a lower absolute value second threshold voltage Vth2 (for example, ± 0. 3V). When the functional module MO is set in the standby state, the functional module formation regions MO the formed MO S transistor evening of the back gate electrode is the potential control, than the second threshold voltage Vth2 (for example, ± 0. 3V) is also set to the third threshold voltage Vth3 higher in absolute value (for example, the same ± 0. 7V with a first threshold voltage).

The semiconductor integrated circuit device shown in FIG. 30 (b) are semiconductors integrated circuit device of the fourteenth embodiment of the present invention, a semiconductor integrated circuit device which emphasizes the power consumption of particular functional module. For example, a functional module formation regions MO constituting a predetermined function module, the input and output signals of the function module, the external device and the interferon - a semiconductor integrated circuit device constituted by the scan input and output circuit region I 0 is sensitive input circuit and the threshold voltage of the MOS transistor which is made form the input-output circuit region I 0 output circuit and the like of the high driving capability are formed, noise countermeasures, the threshold voltage from the viewpoint of low power consumption absolute They are formed at a high a value first threshold voltage Vthl (e.g. ± 0. 7V).

Further, similarly, the threshold voltage of the MOS transistor formed on the functional module formation regions MO which emphasizes the power consumption is also a first threshold voltage of the MO S transistor formed on input-output circuit region I 0 Vthl (e.g. ± 0. 7V) and formed in the same manner, the functional module is back gate Ichito electrode evening MO S transistor formed on the functional module forming region M 0 and is set to the standby state is the potential control, first threshold voltage Vthl (e.g. ± 0. 7V) is set to a higher second threshold voltage V th2 (e.g. ± 1. IV) in absolute value than.

As described above, the semiconductor integrated circuit device of the present invention, the threshold voltage by controlling the substrate bias control circuit to control the Ueru potential of MO S transistor at low power consumption, realizing products of various specifications but that are likely to be, as the functional modules, for example, can be applied SRAM, the digital system of the integrated circuit such as a gate array.

Claims

Asked of range
In 1. The semiconductor integrated circuit device having a first conductivity type transistor, the function modules and a transistor of a second conductivity type,
Control signal to the gate electrode is applied are controlled on / off, and a source electrode is first first conductivity type transient scan evening connected to the second power supply voltage higher than the first power source and,
A gate electrode is controlled by an inverted signal of said control signal, wherein the first first-conductivity type transistor exclusively on / off controlled, and a second source electrode connected to said second power supply a transistor of the first conductivity type,
Wherein the source electrode than the first power supply is connected to a third power supply on the low potential, on the basis on the operation of the transistor of operation and the first first conductivity type of the second transistor of the first conductivity type / a first second conductivity type Bok transistor off in accordance with control source electrode connected to the third power, the first conductive operation and the second of said first transistor of the first conductivity type a second second conductivity type transistor on / off controlled based on the operation of the transistor,
Interposed are connected in series between said first first-conductivity type transistor first second conductivity type transistor, the gate Bok electrode connected to the first power supply both the source a third first conductivity type having electrodes connected to the drain electrode of the transistor of the first first conductivity type transistor,
Interposed are connected in series between said first first-conductivity type transistor first second conductivity type transistor, the gate electrode coupled to the first power supply both the source electrode There is connected to the drain electrode of the transistor of the first second conductivity type, a third second conductivity type transistor of which the drain electrode is connected to the drain electrode of the transistor of the third first conductivity type,
Interposed are connected in series between said second first-conductivity type transistor and the second second-conductivity type transistor, the gate electrode coupled to the first power supply both the source electrode There a fourth first conductivity type transistor that is connected to the drain electrode of the transistor of the second first conductivity type,
Interposed are connected in series between the evening Bok Rungis said second first-conductivity-type transistor and the second second conductivity type, the gate one gate electrode is connected to said first power supply both source Ichisu electrode connected to the drain electrode of Bok Rungis evening of the second second conductivity type, a drain electrode of said fourth first-conductivity-type transistor fourth that is a connected drain electrodes of first signal conducting if including a transistor of a second conductivity type: a level conversion circuits,
Buffers the output signal of the first signal voltage level conversion circuit, comprising a, a first logic circuit that controls the back gate electrode of Bok transistor of a first conductivity type constituting the function module It includes a substrate bias control circuit,
In the first signal voltage level converting circuit, wherein the first second conductivity type Trang register drain electrode and the third of the second conductivity type transistor source electrodes of, the second second conductivity type is connected to the gate Bok electrode of the transistor, the second second-conductivity-type transistor drain electrode and the fourth of the second conductivity type transistor source electrodes of, gate of the transistor of the first second conductivity type one Bok electrode is connected, the first second-conductivity-type transistor and the second second-conductivity type semiconductor integrated times the flip-flop is formed by the feedback Le part comprising Te transistor
In 2. Claim 1,
The substrate bias control circuit, said first, second, third, and transistor of the fourth first conductivity type is formed in Ueru region of the second conductivity type in the same region, Ueru region of the second conductivity type Ueru electrode connected to the fourth power of the second power source or the second power source by remote high potential in the first, second, third, and fourth second conductivity type transistor the semiconductor integrated circuit having but formed in Ueru region of the first conductivity type in the same region, the first signal voltage level conversion circuitry which is Ueru electrode connected to 5 Symbol third power Xiao of the first conductivity type apparatus.
3. In claim 1 or 2, wherein the substrate Baiasu control circuit, said first and second transistors of the second conductivity type is formed in the first Ueru region of the first conductivity type of the same region, the first 1 Ueru electrode of the first conductivity type Ueru region is connected to the third power source, the third second conductivity type transistor is formed in Ueru region of the second first conductivity type, the second is Ueru electrode of the first conductivity type is connected to the source electrode of Bok Rungis evening of the third second conductivity type, the fourth second-conductivity-type transistor of Ueru region of the third first conductivity type made form the semiconductor integrated with said third of said first signal voltage level conversion circuit Ueru electrode connected to the source electrode of the transistor of the fourth second conductivity type in the Ueru region of the first conductivity type circuit device.
4. In any one of claims 1 to 3,
Said first signal voltage level conversion circuit of the third and fourth of the second conductivity type us Njisuta, at least one of the channel length, a transistor of said first and second second conductivity type it is obtained is shorter than the channel length, the third 及 beauty at least one of the channel width of the fourth second-conductivity-type transistor of said first and second second conductivity type of the channel widths of the transistors be those which are larger than, and at least the third and fourth second conductivity type transistor of - square threshold voltage of, said first and second second conductivity type Bok Rungis evening either satisfy semiconductors integrated circuit device of that one which is formed lower by the threshold voltage by remote absolute value.
5. In any one of claims 1 to 4,
In the first signal voltage level converting circuit, the first source electrode and the front Stories second second conductivity type of the second conductivity type Trang Soo evening second conductivity type transistor and the drain electrode and the third of a first output terminal or the fourth second conductivity between the second second conductivity type Trang Soo evening drain electrode of said first signal voltage level converter circuit and is connected the gate electrode of the transistor a second output terminal of the source electrode and the first signal voltage level converting circuit and a gate electrode connected before Symbol transistor of the first second conductivity type transistor type, the said first power supply third semiconductor integrated circuits logical amplitude power source is connected to an input terminal of said first logic circuit defined
In 6. Claim 5,
The substrate bias control circuit, in the first power supply and the third power supply, the output signal of the first logic circuit logic amplitude is defined is, the first signal voltage level converting circuit and the first rather than the area where the logic circuits are formed, is connected to Ueru region of the first conductivity type other functional modules forming region, the back gate Bok electrode of the transistor of the second conductivity type constituting the function module is the potential control The semiconductor integrated circuit device.
In 7. Claim 5,
The substrate Baiasu control circuit, in the third power supply and f SL first power source, the first of the first conductivity type constituting the logic circuit transistor evening Bas Kkuge Ichito electrodes logic amplitude is defined but a semiconductor integrated circuit device which is connected to the fourth power of the higher potential than the second turtle source or the second power supply.
In 8. Claim 5,
The substrate bias control circuit, the first power supply and the third power source, the first Bok Rungis of the first conductivity type constituting the logic circuit of the evening bus Kkuge Ichito electrodes logic amplitude is defined but a semiconductor integrated circuit device which is connected to the first power supply is a source electrode of the same potential of the transistor of the first conductivity type.
In 9. Claim 5,
The substrate bias control circuit has a first inverting logic circuits for waveform shaping, a first for the waveform shaping to the first output terminal or the second output terminal of said first signal voltage level conversion circuit human power terminal of the inverting logic circuit is connected to the first is connected to the output terminal to the input terminal of the logic circuit, the logic amplitude is stipulated the first power supply and in the third power source, and the second large listening channel length than transistor of the first conductivity type constituting the logic circuit 1, a small channel width and a high threshold voltage first conductivity type Bok Rungis waveform including evening formed by any of the conditions of the the semiconductor integrated circuit device having a first inverting logic circuits for shaping.
In 1 0. The semiconductor integrated circuit device having a first conductive type transistor, the function modules and a transistor of a second conductivity type,
Gate one gate electrode to control signal is applied on / off is controlled, and a transistor of the first second conductivity type source electrode connected to the first power supply,
A gate electrode is controlled by an inverted signal of the control signal from the first second conductivity type transistors exclusively on / off controlled, and second the lease electrode connected to said first power supply a second conductivity type transistor,
A source electrode connected to a fourth power supply, the first to the second ON / OFF based on the operation of the operation and the first second-conductivity-type transistor of the second conductivity type Bok transistor is controlled a transistor of the first conductivity type,
Zosu electrode connected to said fourth power supply, a second third of the first operation and the second second conductivity type on / off based on the operation of the transistor of the second conductivity type transistor is controlled a first conductivity type transistor,
Ri connected in series interposed, said the gate one gate electrode the first high-potential der than the power supply between the first second conductivity type transistor and the first first-conductivity type transistor, one said is connected to a second power supply potential lower than the fourth power supply, the third second conductivity type having a source electrode connected to the drain electrode of the transistor of the first transistor of the second conductivity type When,
Wherein interposed are connected in series between the first second conductivity type transistors evening and the first first-conductivity type transistor, the co-when a gate electrode coupled to the second power supply source electrode connected to the drain electrode of the transistor of the first first conductivity type, and a third first conductivity type which has a drain electrode connected to the drain of the third second-conductivity-type transistor of the transistor,
Said second interposed are connected in series between the second conductivity type transistors evening and the second first-conductivity type transistor, the co-when a gate electrode coupled to the second power supply source a fourth second conductivity type transistor that is connected to the drain electrode of the electrode of the second transistor of the second conductivity type,
Said second interposed are connected in series between the second conductivity type transistor and the second first-conductivity type transistor, the co-when a gate electrode coupled to the second power supply, a source electrode There is connected to the drain electrode of the transistor of the second first conductivity type, the fourth first conductivity type which has a drain electrode connected to the drain Kamekyoku transistor of the fourth second conductivity type transistors evening a second signal voltage level conversion circuit including bets,
It buffers the output signal of the second signal voltage level conversion circuit, comprising a second logic circuit that controls the back gate electrode of the second conductivity type transistor constituting the function module substrate It includes a bias control circuit,
In the second signal voltage level converting circuit, wherein the first first conductivity type Trang register the third drain electrode of the first conductivity type of the source electrode of the transistor is of the second first conductivity type It is connected to the gate electrode of the transistor, the second transistor drain electrode and the fourth first conductivity type of Bok Rungis evening source electrode of the first first conductivity type transistor of the first conductivity type gate one is connected to the gate electrode, before Symbol semiconductor integrated circuit device which flip-flop is formed by the first transistor of the first conductivity type and the second consisting in a first conductivity type transistor Fi one-back loop.
In 1 1. Claim 1 0,
The substrate bias control circuit, said first, second, third, and fourth of the first conductivity type transistor is formed in Ueru region of the second conductivity type in the same region, Ueru of the second conductivity type connected Ueru electrode to the fourth power in the region, the first, second, third, and fourth second conductivity type transistor is formed in the first conductivity type © El region of the same area, the the semiconductor integrated circuit device having a third said second signal voltage level converter circuit connected to the power supply of a potential lower than the power supply Ueru electrode said first power source or the first in the Ueru region of the first conductivity type .
1 2. In claim 1 0 or 1 1, wherein the substrate bias control circuit is formed in the first and first Ueru region of the second conductivity type second Bok Rungis evening the same region of the first conductivity type is the first of the second conductivity type Ueru electrode Ueru region of which is connected to the fourth power, the third first conductivity type transistor is formed in Ueru region of the second conductivity type , wherein the second second conductivity type Ueru electrode Ueru regions of connected to the transistor evening source electrode of the third first conductivity type, said fourth transistor of the first conductivity type is a third second is formed on the conductive © E Le region of the third of the the El electrode Ueru region of the second conductivity type is connected to the transistor evening source electrode of said fourth first conductivity type of the second signal voltage the semiconductor integrated circuit device having a level conversion circuit.
In 1 3. Claim 1 0-1 2,
Said second signal voltage level conversion circuit, said one of the third and fourth of the first conductivity type tiger Njisuta, at least one of the channel length, said first and second first-conductivity type channel transistor it is obtained is shorter than the length, at least one of the channel width of the third 及 beauty of the fourth first conductivity type Toranjisuku is than the first and second channel widths of the first conductivity type transistor it is also one that is larger, and at least the third and fourth first-conductivity-type transistor of - square threshold voltage of the threshold voltage of the transistor of the first and second first conductivity type either satisfy semiconductors integrated circuit device of that remote and is formed lower in absolute value.
In 1 4. Claim 1 0-1 2,
In the second signal voltage level converting circuit, wherein the first first conductivity type Trang Soo evening Dorein electrode and the third first conductivity type Bok Rungis evening source electrode and the front Stories second of the first wherein a gate electrode of the conductivity type of the transistor is the first output terminal or the second drain electrode of the first conductivity type Bok run register the connected second signal voltage level conversion circuit 4 of the a second output terminal of the source electrode and the front Symbol first said first conductivity type transistors evening gate electrode is connected to the second signal voltage level conversion circuit of first conductivity type transistor, the fourth power source and the semiconductor integrated circuits device the second logic amplitude in the power supply is connected to an input terminal of said second logic circuits being defined.
In 1 [delta]. Claims 1 to 4,
The substrate bias control circuit, in the fourth power supply and the second power supply, the output signal of the second logic circuit logic amplitude is defined is, the second signal voltage level converting circuit and the second is the SeMMitsuru to Ueru region of other functional modules forming area second conductivity type rather than the area where the logic circuit is formed, the back gate one WINCH electrode of the transistor of the first conductivity type constituting the function module potential the semiconductor integrated circuit device to be controlled.
In 1 6., 1 Motomeko 1 4,
The substrate bias control circuit, in the fourth power supply and the second power supply, said second conductivity type transistors evening Bas Kkuge Ichito electrodes constituting the second logic circuit logic amplitude is defined in , the first power source or than the first power semiconductor integrated circuit device in absolute value and is connected to the third power of the low-voltage level.
In 1 7. Claims 1 to 4,
The substrate bias control circuit, in the fourth power supply and the second power supply, bus Kkuge Ichito electrode of the second conductivity type of the transistors constituting said second logic circuit logic amplitude is defined, the the semiconductor integrated circuit device which is connected to said second power source is a source electrode at the same potential of the second conductivity type transistor.
In 1 8. Claims 1 to 4,
The first output terminal or the input terminal to the second output terminal of the second signal voltage level conversion circuit is connected, the output terminal to the input terminal of the second logic circuit is connected, and the fourth power supply one of the conditions of the logic amplitude in the second power supply is defined, and the second second-conductivity-type large channel length than transistor included in the logic circuits, small Chiyane Le widths and higher threshold voltage the semiconductor integrated circuit device having a second inverting logic circuit for waveform shaping by the second conductivity type Bok transistor formed by (
In 1 9. Claim 1 or 1 0,
Said first logic circuit or the second logic circuit, and a small logic circuit having a driving capability which is formed on the input side, semiconductor and large logic circuit driving capability ing is formed by connecting an integrated circuit device .
In 2 0. Any of claims 1 to 1 8,
The semiconductor integrated circuit device is formed on the second conductivity type on the substrate, wherein the first signal voltage level conversion circuit, said first logic circuit, or the first signal voltage level conversion circuitry, said first logic circuit, by the first inverted logic circuit, the first signal voltage level converting circuit, the first logic circuit or said first signal voltage level converting circuit, the first logic circuit, said first semiconductor only one inverted back gate electrode of the second conductivity type transistor formed in the first conductivity type Ueru region is another functional modules forming region rather than the region in which the logic circuit is formed is the potential control integrated circuit device.
In 2 1. Any of claims 1 to 1 8,
The semiconductor integrated circuit instrumentation is formed on the first conductivity type on the substrate, the second signal voltage level conversion circuit, the second ¾ physical circuit or said second signal voltage level converting circuit, the second logic circuit, by the second inverting logic circuit, the second signal voltage level conversion circuit, the second logic circuit or said second signal voltage Reperu conversion circuit, the second logic circuit, the second reversing a semiconductor integrated only the back gate electrode of the transistor of the first conductive 鼋型 formed on the second conductive type Ueru region is another functional module formation regions is the potential control rather than the area where the logic circuit is formed of circuit device.
In the semiconductor integrated circuit device having a 2 2. Functional modules forming region constituting a predetermined function module, a peripheral circuit including input and output circuit forming region with external devices interface input and output signals of the function modules,
Threshold voltage of the evening transistor provided in the peripheral circuit formation region is formed in the first threshold voltage, the threshold voltage of the transistor provided in the functional module formation regions is provided in the peripheral circuit formation region transistor is formed by evening of the first threshold voltage by remote low in absolute value a second threshold voltage, by the functional module is set in the standby state, the functional module forming region transistor are provided evening the back gate potential of Ichito electrode is controlled, the semiconductor integrated circuit device which is set to the high third threshold voltage in absolute value than the second threshold voltage.
2 3. And functional modules forming region constituting a predetermined function module, in the semiconductor integrated circuit device having a peripheral circuit including input and output circuit forming region with external devices I centers face the input and output signals of the function modules, wherein threshold voltage of the transistor provided function modules region and the output circuit formation region is formed in the first threshold voltage, by the functional module is set in the standby state, provided the function module forming region was the potential of the back gate Bok electrode of the transistor is controlled, the first semiconductors integrated circuit device is set to a higher second threshold voltage in absolute value than the threshold voltage.
2 4. A first conductivity type transistor, comprising a basic cell that will be formed by second conductivity type transistors, a plurality of the basic arranged in Matrix focal to configure the predetermined function circuit by wiring change a functional module arranged by cell group, and a peripheral circuit including a pre-Symbol basic cell external device and output cell group the input and output signal to fin evening one face disposed on the periphery of the configured function modules by group in the semiconductor integrated circuit device having,
Power supplied to the plurality of basic cell groups are those supplied by the first metal wiring layer and the first metal wiring layer and the second metal wiring layer of the upper layer than,
In said first and said second conductivity type transistors evening before Symbol first metal wiring layer which is extended in the channel length direction, and said second power source, a first low-potential than the second power supply and a power is supplied to the cell group,
In said first and said second conductivity type transistors evening before Symbol second metal wiring layer which is extended in the direction of the channel width of the fourth power of the second power supply and the same potential or a high potential, said first the semiconductor integrated circuit device to supply a third power supply 1 of the power source and the same potential or a low potential to the cell group.
In 2 5. Claims 2 to 4,
The formed by the first and the second conductivity type prior Symbol second metal wiring layer which is extended in the direction of the channel width of the transistor, the third power and the fourth power supply and the power supply wiring you supply the semiconductor integrated circuit device which is placed and routed on the first and the wiring grid of channel width direction of the second conductivity type transistor and Ueru on the electrode.
In 2 6. Claims 2 to 4, or 2 5,
The second and the fourth feeding power to Ueru electrodes of the second conductivity type transistor of the first conductivity type by the metal wiring layer, the connection hole or via the connecting hole and the first metal wiring layer line, We, the third feeding power to the first conductivity type Ueru electrode of the second conductivity type transistor according to the second metal wiring layer, the connection hole, or through a connection hole and a front Symbol first metal interconnect layer the semiconductor integrated circuit device performed Te.
In 2 7. Claims 2 to 4,
Wherein the connection hole transistor of the first and the second conductivity type is connected to Ueru electrode formed, the wired and connected to the basic cell, the first wiring and the second power supply while being disposed between the power line, the the first and the second conductivity type on the wiring grid which is adjacent to the channel width direction of the transistor, said a Ueru electrode of the first conductivity type Bok transistor It is arranged connection hole for connecting to the first power line, the first and on the wiring grid which is adjacent to the channel width direction of the transistor of the second conductivity type, the transistor of the second conductivity type the semiconductor integrated circuit device connecting holes are arranged for the Ueru electrodes connected to said second power line.
In 2 8. Any of claims 2 to 4 to 2 7,
The semiconductor integrated circuit device is formed on a first conductivity type on the substrate, said first and second power supplies are first extended in the first and the channel length direction of the second conductivity type transistor formed by being supplied with a metal wiring layer, and the fourth the second metal wiring layer only power wiring for supplying the power source is extended in the direction of the channel width of the transistor of the first and the second conductivity type It is, or,
The semiconductor integrated circuit device is formed on the second conductivity type on the substrate, said first and second power supplies have been extended to the first and the front Bok Rungis evening in the channel length direction of the second conductivity type is supplied at the first metal wiring layer, and the third and the second metal wiring layer only power wiring for supplying the power source is extended in the direction of the channel width of the transistor of the first and the second conductivity type is formed by,
Ueru of a second conductivity type Ueru or transistors of the first conductivity type of a first conductivity type and the second conductivity type Bok transistor is formed is formed is separated from the substrate of the semiconductor integrated circuit device ^ conductor integrated circuit device.
2 9. The first conductive type transistor and the basic cell composed of a transistor of a second conductivity type ingredients fig, a plurality of the basic cells that are placed in Matrix form constituting a predetermined function circuit by wiring change semiconductor integrated with a function module configured by the group, and a peripheral circuit including input and output cell group Inta one face the placed in an external device input and output signals to the periphery of the basic cell Le functional module arranged by groups in the circuit device,
Power supplied to the plurality of basic cell groups, a first power supply of the second power supply and said second lower potential than the power supply, the first and Chiyane Le length direction of the second conductivity type transistor supplied by the first metal wiring layer which is extended into, and the fourth power supply voltage higher than the second power supply and the same potential or said second power supply, Ku if the first power supply and the same potential is the a third power supply potential lower than the first power source, a first auxiliary power supply for assisting the first power source, and a second auxiliary power supply for assisting the second power source, the first and the second together are extended in transistors evening in the channel width direction of the conductivity type than the first metal interconnect layer is provided in the second metal interconnect layer of the upper layer, and a third auxiliary power to further assist the third power source, the the fourth auxiliary power and the tea transistor of said first and said second conductivity type to assist a fourth power supply Le length is extended in the direction, and the semiconductor integrated circuit device which is supplied by the third metal wiring layer of the by second metal wiring layer remote upper layer.
In 3 0. Claim 2 9,
It said fourth power supply, the third power source, the first auxiliary power supply, the second auxiliary power supply, the second metal which is extended in the first and the channel width direction of Bok Rungis evening of the second conductivity type the supplied to cell group by the power supply line and the auxiliary power wiring formed in the wiring layer, the power wiring of the first and the wiring grid and Ueru electrodes on Ji Yaneru width direction of the transistor of the second conductivity ¾ the semiconductor integrated circuit disposed wired
In 3 1. Claim 2 9,
It said first and said first auxiliary 鼋源 and the second auxiliary power is supplied by the second conductivity type Bok Rungis evening the second metal wiring layer is extended in the channel width direction was made form of, through the connection hole, with the first power supply and said second power source is connected to the first metal wiring layer to be supplied to said first and transistor evening in the channel length direction of the second conductivity type It said third auxiliary power source and the fourth auxiliary power is supplied by the extended third metal interconnection layer via a contact hole, the third power and the fourth power of supplied the the semiconductor integrated circuit device which is connected to the second metal wiring layer.
In 3 2. Claim 2 9 to 3 1,
The semiconductor integrated circuit device is formed on a first conductivity type on the substrate, said first and second power supplies are first which is extended in the channel length direction of the i-th and the second conductivity type transistor It is supplied at the metal wiring layer, and said fourth power supply, the first auxiliary power supply, the only the second auxiliary power is extended to the channel width direction of the transistor of the first and the second conductivity type is supplied at the second metal wiring layer is further supplied by the only the fourth auxiliary 鼋 source, a third metal interconnection layer extending in the first and the channel length direction of said second conductivity type transistors, or ,
The semiconductor integrated circuit device is formed on the second conductivity type on the substrate, the said first and second power supplies have been extended to the first and transistor evening in the channel length direction of the second conductivity type It is supplied at the first metal interconnection layer, and the third power source, the first auxiliary power supply, only the second auxiliary power is extended to the first and Chi Yaneru width direction of the second conductivity type transistor supplied by the second metal wiring layer,
Furthermore, the semiconductor integrated circuit instrumentation supplied by the third auxiliary power only the third metal wiring layer which is extended to switch Yaneru length direction of the transistors of the first and the second conductivity type
In 3 3. Claim 2 5 to 3 2,
Said first and said third power supply and the fourth power source supplied by the second conductivity type transistors before Symbol second metal wiring layer which is extended in the channel width direction of or prior Symbol second metal wiring the supplied with a layer third power and the fourth power supply, supplied by the third metal wiring layer which is extended in the channel length direction of a one said first and said second conductivity type Bok transistor said third auxiliary power supply, the fourth auxiliary power supply potential by the sleep mode one de control signal formed by the chip-Ineburu signal, or an external device or a semiconductor integrated circuit device section which is input from the external device There semiconductor integrated circuit device to be controlled.
In 3 4. ^ Either Motomeko 2 5 to 3 3,
Said first and said third power supply and the fourth power source supplied by the second conductivity type prior Symbol second metal wiring layer which is extended in the direction of the channel width of the transistor, or pre-Symbol first and said said third auxiliary power that is supplied by the third metal wiring layer which is extended in the channel length direction of the transistor of the second conductivity type, said fourth auxiliary power source, the functional modules of the semi-conductor integrated circuit device each power supply wiring or the auxiliary power supply wiring is separated into each, and the chip ♦ Ineburu signal input from the external device, or the sleep mode control signal formed within an external device or a semiconductor integrated circuit device to the selector first circuit the semiconductor integrated circuit device to be input.
PCT/JP1997/000608 1996-02-29 1997-02-28 Semiconductor integrated circuit device WO1997032399A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP4359796 1996-02-29
JP8/43597 1996-02-29
JP8/69638 1996-03-26
JP6963896 1996-03-26

Publications (1)

Publication Number Publication Date
WO1997032399A1 true true WO1997032399A1 (en) 1997-09-04

Family

ID=26383394

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1997/000608 WO1997032399A1 (en) 1996-02-29 1997-02-28 Semiconductor integrated circuit device

Country Status (1)

Country Link
WO (1) WO1997032399A1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6310492B1 (en) 1999-05-06 2001-10-30 Matsushita Electric Industrial Co., Ltd. CMOS semiconductor integrated circuit
EP1152534A1 (en) * 2000-05-02 2001-11-07 Sharp Kabushiki Kaisha Integrated CMOS semiconductor circuit
WO2002009321A1 (en) * 2000-07-20 2002-01-31 Infineon Technologies Ag Integrated switching circuit with reference current supply
JP2010103739A (en) * 2008-10-23 2010-05-06 Seiko Epson Corp Differential amplifier circuit, high-speed serial interface circuit, integrated circuit device and electronic apparatus
US8040172B2 (en) 2008-12-23 2011-10-18 Stmicroelectronics Design And Application S.R.O. Logic level converter
WO2013157206A1 (en) * 2012-04-17 2013-10-24 株式会社デンソー Semiconductor integrated circuit

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62123823A (en) * 1985-11-22 1987-06-05 Nec Corp Semiconductor integrated circuit
JPS6364337A (en) * 1986-09-05 1988-03-22 Hitachi Ltd Semiconductor integrated circuit device
JPS63107140A (en) * 1986-10-24 1988-05-12 Hitachi Ltd Semiconductor integrated circuit device
JPS63202053A (en) * 1987-02-18 1988-08-22 Hitachi Ltd Semiconductor integrated circuit device
JPH02177345A (en) * 1988-12-27 1990-07-10 Hitachi Ltd Semiconductor integrated circuit device
JPH02268018A (en) * 1989-03-07 1990-11-01 Integrated Device Technol Inc Ttl-cmos level translator
JPH0382152A (en) * 1989-08-25 1991-04-08 Nec Corp Mos type semiconductor integrated circuit
JPH05275661A (en) * 1992-03-30 1993-10-22 Nec Corp Semiconductor device
JPH0689574A (en) * 1992-03-30 1994-03-29 Mitsubishi Electric Corp Semiconductor device
JPH0774616A (en) * 1993-07-06 1995-03-17 Seiko Epson Corp Signal voltage level converting circuit and output buffer circuit
JPH07142605A (en) * 1993-11-22 1995-06-02 Fujitsu Ltd Semiconductor device and manufacturing method thereof
JPH08204140A (en) * 1995-01-27 1996-08-09 Nec Corp Silicon-on-insulator semiconductor device and bias voltage generating circuit
JPH09116416A (en) * 1995-10-18 1997-05-02 Hitachi Ltd Input/output buffer circuit

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62123823A (en) * 1985-11-22 1987-06-05 Nec Corp Semiconductor integrated circuit
JPS6364337A (en) * 1986-09-05 1988-03-22 Hitachi Ltd Semiconductor integrated circuit device
JPS63107140A (en) * 1986-10-24 1988-05-12 Hitachi Ltd Semiconductor integrated circuit device
JPS63202053A (en) * 1987-02-18 1988-08-22 Hitachi Ltd Semiconductor integrated circuit device
JPH02177345A (en) * 1988-12-27 1990-07-10 Hitachi Ltd Semiconductor integrated circuit device
JPH02268018A (en) * 1989-03-07 1990-11-01 Integrated Device Technol Inc Ttl-cmos level translator
JPH0382152A (en) * 1989-08-25 1991-04-08 Nec Corp Mos type semiconductor integrated circuit
JPH05275661A (en) * 1992-03-30 1993-10-22 Nec Corp Semiconductor device
JPH0689574A (en) * 1992-03-30 1994-03-29 Mitsubishi Electric Corp Semiconductor device
JPH0774616A (en) * 1993-07-06 1995-03-17 Seiko Epson Corp Signal voltage level converting circuit and output buffer circuit
JPH07142605A (en) * 1993-11-22 1995-06-02 Fujitsu Ltd Semiconductor device and manufacturing method thereof
JPH08204140A (en) * 1995-01-27 1996-08-09 Nec Corp Silicon-on-insulator semiconductor device and bias voltage generating circuit
JPH09116416A (en) * 1995-10-18 1997-05-02 Hitachi Ltd Input/output buffer circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6310492B1 (en) 1999-05-06 2001-10-30 Matsushita Electric Industrial Co., Ltd. CMOS semiconductor integrated circuit
EP1152534A1 (en) * 2000-05-02 2001-11-07 Sharp Kabushiki Kaisha Integrated CMOS semiconductor circuit
US6630717B2 (en) 2000-05-02 2003-10-07 Sharp Kabushiki Kaisha CMOS semiconductor circuit with reverse bias applied for reduced power consumption
WO2002009321A1 (en) * 2000-07-20 2002-01-31 Infineon Technologies Ag Integrated switching circuit with reference current supply
JP2010103739A (en) * 2008-10-23 2010-05-06 Seiko Epson Corp Differential amplifier circuit, high-speed serial interface circuit, integrated circuit device and electronic apparatus
US8040172B2 (en) 2008-12-23 2011-10-18 Stmicroelectronics Design And Application S.R.O. Logic level converter
WO2013157206A1 (en) * 2012-04-17 2013-10-24 株式会社デンソー Semiconductor integrated circuit

Similar Documents

Publication Publication Date Title
US5151619A (en) Cmos off chip driver circuit
US7514766B2 (en) Semiconductor device
US6034563A (en) Semiconductor integrated circuit having reduced current leakage and high speed
US6605981B2 (en) Apparatus for biasing ultra-low voltage logic circuits
US6127857A (en) Output buffer or voltage hold for analog of multilevel processing
US5883423A (en) Decoupling capacitor for integrated circuit signal driver
US6603346B2 (en) Semiconductor booster circuit having cascaded MOS transistors
US6359501B2 (en) Charge-pumping circuits for a low-supply voltage
US6034397A (en) Silicon-on-insulator body- and dual gate-coupled diode for electrostatic discharge (ESD) applications
US5576570A (en) Semiconductor device having CMOS circuit
US6232793B1 (en) Switched backgate bias for FET
US7061299B2 (en) Bidirectional level shifter
US5892260A (en) SOI-type semiconductor device with variable threshold voltages
US6188247B1 (en) Method and apparatus for elimination of parasitic bipolar action in logic circuits for history removal under stack contention including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements
US5825601A (en) Power supply ESD protection circuit
US5905399A (en) CMOS integrated circuit regulator for reducing power supply noise
US5440249A (en) Voltage level translator circuit with cascoded output transistors
US6320414B1 (en) High-voltage level tolerant transistor circuit
US6287901B1 (en) Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors
US5302871A (en) Delay circuit
Sawada et al. An on-chip high-voltage generator circuit for EEPROMs with a power supply voltage below 2 V
US7224206B2 (en) Charge-pump with improved biasing of the body regions of the pass-transistors
US4122360A (en) Logic circuit using CMOS transistors
US20050264347A1 (en) Internal voltage generating circuit and semiconductor integrated circuit device
US7683668B1 (en) Level shifter

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR US