JP2007165618A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device having a body potential control function which can achieve high speed operation and suppression of standby power through relatively simple circuitry. <P>SOLUTION: In a circuit 1 for controlling the body potential of a PMOS transistor Q21 and an NMOS transistor Q22 in a control object logical circuit 6, a PMOS transistor Q1 has a source electrode connected with a power supply VDD, a drain electrode or a node N1 connected with the body terminal of the PMOS transistor Q21, and a gate electrode receiving an inversion standby signal bar STB; and an NMOS transistor Q2 has a grounded source electrode, a drain electrode or a node N2 connected with the body terminal of the NMOS transistor Q22, and a gate electrode receiving a standby signal STB. Between the nodes N1 and N2, a transfer gate TF1 is inserted receiving the inversion standby signal bar STB and the standby signal STB at the MOS gate and the PMOS gate. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a body potential control function of a MOS transistor with a logic circuit using the MOS transistor as a control target.

  The term “MOS” has been used in the past for metal / oxide / semiconductor laminated structures, and is taken from the acronym Metal-Oxide-Semiconductor. However, in particular, in a field effect transistor having a MOS structure (hereinafter, simply referred to as “MOS transistor”), materials for a gate insulating film and a gate electrode have been improved from the viewpoint of recent integration and improvement of a manufacturing process.

  For example, in a MOS transistor, polycrystalline silicon has been adopted instead of metal as a material for a gate electrode mainly from the viewpoint of forming a source / drain in a self-aligned manner. From the viewpoint of improving electrical characteristics, a material having a high dielectric constant is adopted as a material for the gate insulating film, but the material is not necessarily limited to an oxide.

  Therefore, the term “MOS” is not necessarily limited to the metal / oxide / semiconductor stacked structure, and is not presumed in this specification. That is, in view of common technical knowledge, the term “MOS” as used herein is not only an abbreviation derived from the word source, but also broadly includes a laminated structure of a conductor / insulator / semiconductor.

  FIG. 15 is a circuit diagram showing a configuration of a DTMOS (Dynamic Threshold Voltage MOS) circuit which is a conventional dynamic body potential control method. A DTMOS circuit is disclosed in Non-Patent Document 1, for example.

  As shown in the figure, a CMOS inverter is constituted by a PMOS transistor Q51 and an NMOS transistor Q52 provided in series between a power supply VDD and the ground. The gate electrode and body terminal of the PMOS transistor Q51 and the gate electrode and body terminal of the NMOS transistor Q52 are both electrically connected to the input terminal P1, and the drain of the PMOS transistor Q51 (the drain of the NMOS transistor Q52) becomes the output terminal P0.

  As described above, the body potential is controlled by the gate signal by connecting the gate electrodes and body terminals of the MOS transistors Q21 and Q22 in common with the DTMOS circuit. Therefore, since the body potential can be controlled in synchronization with the gate signal, a body potential that becomes a forward bias is applied to the body region (region sandwiched between the source region and the drain region) of the MOS transistor in the ON state. The speed is increased by lowering the threshold voltage Vth. On the other hand, the threshold voltage Vth of the MOS transistor in the off state is not applied with the body potential that becomes a forward bias, and therefore the threshold voltage Vth is not lowered. Therefore, the MOS transistor in the off state enables high-speed operation of the MOS transistor in the on state without increasing the leakage current.

  FIG. 16 is a circuit diagram showing the configuration of a VTCMOS (Variable Threshold Voltage CMOS) circuit that controls the body potential of the logic circuit using a charge pump circuit or the like. A VTCMOS circuit is disclosed in Non-Patent Document 2, for example.

  As shown in the figure, a CMOS inverter is constituted by a PMOS transistor Q51 and an NMOS transistor Q52 provided in series between a power supply VDD and the ground. The gate electrode of the PMOS transistor Q51 and the gate electrode of the NMOS transistor Q52 become the input terminal P1, and the drain of the PMOS transistor Q51 (the drain of the NMOS transistor Q52) becomes the output terminal P0.

  The body potentials of the PMOS transistor Q51 and the NMOS transistor Q52 are controlled by the control circuit 51. That is, the control circuit 51 applies the standby voltage VPS to the body terminal of the PMOS transistor Q51 and also applies the standby voltage VNS to the body terminal of the NMOS transistor Q52 in the standby state. The control circuit 51 applies the active voltage VPA to the body terminal of the PMOS transistor Q51 and applies the active voltage VNA to the body terminal of the NMOS transistor Q52 when in the operating state.

  The standby voltages VPS and VNS are voltages at which the PN junction of the PMOS transistor Q51 and the NMOS transistor Q52 is in a reverse bias state, and the active voltages VPA and VNA are voltages at which the PN junction of the PMOS transistor Q51 and the NMOS transistor Q52 are in a forward bias state. Respectively.

  As described above, the control circuit 51 of the VTCMOS circuit switches the MOS transistor to be controlled between the standby state and the operation state in units of blocks. That is, the control circuit 51 applies a standby voltage that is reversely biased to the body terminal in the standby state, thereby increasing the threshold voltage Vth of the MOS transistor to reduce the leakage current, and the body terminal is forward biased in the operating state. By applying the active voltage, the threshold voltage Vth is reduced, thereby realizing high speed.

  In order to operate the circuit at high speed, it is effective to reduce the threshold voltage Vth of the MOS transistor, but the leakage current increases exponentially as the threshold voltage Vth decreases. Since the leak current always flows regardless of the operation of the circuit, there is a problem that standby power increases in a circuit with a low threshold voltage Vth.

  In the DTMOS circuit and the VTCMOS circuit described above, the threshold voltage Vth can be lowered only in the operating state, so that the speed of the circuit can be increased without increasing standby power.

F. Assaderaghi, el al., "Dynamic threshold voltage MOSFET (DTMOS) for ultra-low volage opeation," 1994 IEDM, pp. 809-812, 1994. T. Kuroda, el al., "A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) scheme," IEEE Journal of Solid-State Circuit, vol. 31, no. 11, (pp.170-1779, Nov. 1996.)

  In the DTMOS circuit, since the gate electrode and the body terminal are connected, there is a problem that the load capacity increases. Further, when the power supply (voltage) VDD becomes 0.6V or more, a forward current flows through the PN junction between the body and the source. Therefore, in a circuit where the power supply Vdd is 0.6V or more, as shown in FIG. There arises a problem that an additional auxiliary transistor for limiting the voltage applied to the transistor is required.

  As shown in FIG. 17, a PMOS transistor Q35 and an NMOS transistor Q36 are provided as auxiliary transistors. The PMOS transistor Q35 is interposed between the body terminal of the PMOS transistor Q51 and the input terminal P1, and the gate electrode is grounded. On the other hand, the NMOS transistor Q36 is interposed between the body terminal of the NMOS transistor Q52 and the input terminal P1, and the gate electrode is connected to the power supply Vdd.

  Accordingly, if the threshold voltages of the PMOS transistor Q35 and the NMOS transistor Q36 are both Vth, the body potential of the NMOS transistor Q52 is biased to (Vdd−Vth) when “H” (VDD) is applied to the input terminal P1. By biasing the body potential of the PMOS transistor Q51 to Vth when “L” (GNDD) is applied to the input terminal P1, even if the power supply (voltage) VDD becomes 0.6V or more, it can be lower than 0.6V + Vth. For example, a forward current can be prevented from flowing through the PN junction between the body and the source.

  On the other hand, in the VTCMOS circuit, it is necessary to generate four kinds of voltages as the standby voltage and the active voltage for the PMOS transistor and the NMOS transistor. It is conceivable to provide a charge pump circuit as means for generating a plurality of types of voltages. The charge pump circuit has a relatively complicated circuit configuration, and it takes a time of μs order to generate a voltage for setting the body potential, and there is a problem that the area increases due to the addition of the circuit. .

  As another means for generating a plurality of types of voltages, a configuration in which four types of power supplies are prepared can be considered. In this case, voltage control is possible within several clocks, but there is a problem that an additional circuit such as a power supply unit is required.

  The present invention has been made in order to solve the above-described problems, and has a relatively simple circuit configuration that does not require a complicated additional circuit such as a charge pump circuit or a separate power source for body potential control, and is speeded up. An object of the present invention is to obtain a semiconductor device having a body potential control function capable of suppressing standby power.

  According to a first aspect of the present invention, there is provided a semiconductor memory device including a logic gate having at least one MOS transistor formed on a predetermined substrate and capable of individually setting a potential of a body region sandwiched between a source region and a drain region. And a control circuit that is formed on the predetermined substrate and that controls the potential of the body region of the at least one MOS transistor, the control circuit having a first power supply voltage at one end Is connected to the first power supply line, the other end is connected to the first node, and the other end is supplied with the second power supply voltage lower than the first power supply voltage. Second switching means connected to the second power supply line and having the other end connected to the second node, and the body region of the at least one MOS transistor is the second switching means. And a third switching means electrically connected to one of the first and second nodes and interposed between the first and second nodes, the control circuit waiting for the control target logic circuit The first and second switching means are set to an on state and the third switching means is set to an off state in a state, and the first and second nodes are electrically connected to the first and second power sources. A second control operation that executes a first control operation to be connected and sets the first and second switching means to an OFF state and the third switching means to an ON state when the control target logic circuit is in an operation state The at least one MOS transistor has a state in the PN junction portion between the source region and the body region in the state during the second control operation as compared with the state during the first control operation. Bias degree is high.

  The present invention according to claim 1 of the present invention relates to at least one MOS transistor in the logic circuit to be controlled, and the state during the first control operation performed in the standby state is compared with the state during the second control operation, Since the forward bias degree at the PN junction between the source region and the body region is low, the leakage current flowing through the at least one MOS transistor in the standby state can be effectively suppressed.

  On the other hand, since the forward bias degree in the PN junction is higher in the second control operation state performed in the operation state than in the first control operation state, the switching of the at least one MOS transistor in the operation state is performed. The operation can be speeded up.

  In addition, it does not require power supply for setting the body potential in the operating state, and can be realized with a relatively simple circuit configuration because it is configured only by the first and second power sources that are generally used. .

<Embodiment 1>
1 is a circuit diagram showing a circuit configuration of a semiconductor device having a charge recycle type dynamic body potential control function according to Embodiment 1 of the present invention.

  As shown in the figure, the semiconductor device of the first embodiment includes a control target logic circuit 6 and a control circuit 1 formed on an SOI substrate or a bulk substrate (both not shown in FIG. 1).

  The control target logic circuit 6 includes a PMOS transistor Q21 and an NMOS transistor Q22. The PMOS transistor Q21 and the NMOS transistor Q22 provided in series between the power supply VDD and the ground constitute a CMOS inverter. The gate electrode of the PMOS transistor Q21 and the gate electrode of the NMOS transistor Q22 are connected in common to serve as the input terminal P1, and the drain of the PMOS transistor Q21 (the drain of the NMOS transistor Q22) serves as the output terminal P0.

  The control circuit 1 includes a PMOS transistor Q1 (first switching means), an NMOS transistor Q2 (second switching means), and a transfer gate TF1 (third switching means). The PMOS transistor Q1 has a source electrode connected to a power supply VDD (more precisely, a first power supply line to which a power supply voltage Vdd described later) is supplied, and a drain electrode node N1 (first node) is the body of the PMOS transistor Q21. The inverted standby signal bar STB is received at the gate electrode.

  On the other hand, the source electrode of the NMOS transistor Q2 is grounded (more precisely, it is connected to a second power supply line to which a later-described GND level (<VDD) is supplied), and a node N2 (second node) as a drain electrode is connected. The NMOS transistor Q22 is connected to the body terminal and receives a standby signal STB at its gate electrode. A transfer gate TF1 is inserted between the nodes N1 and N2. The NMOS gate of the transfer gate TF1 receives the inverted standby signal bar STB and the PMOS gate receives the standby signal STB.

  FIG. 2 is a sectional view showing a sectional structure of the PMOS transistor Q21 and the NMOS transistor Q22. As shown in the figure, a buried insulating film 12 is formed on a semiconductor substrate 11, and an SOI layer 13 is formed on the buried insulating film 12. Therefore, the semiconductor substrate 11, the buried insulating film 12 and the SOI layer 13 constitute an SOI substrate.

  The isolation insulating film 20 that penetrates the SOI layer 13 separates the SOI layer 13 into a PMOS formation region 25 and an NMOS formation region 26. The PMOS formation region 25 includes a P-type PMOS source region 14s and an N-type PMOS body region 14b. And a P-type PMOS drain region 14d are selectively formed. A gate electrode 17 is formed on the PMOS body region 14b via the gate insulating film 16, and a power supply wiring 27 is provided in the PMOS source region 14s. A power supply VDD is connected to the power supply wiring 27.

  On the other hand, an N-type NMOS source region 15s, a P-type NMOS body region 15b, and an N-type NMOS drain region 15d are selectively formed in the NMOS formation region 26, respectively. A gate electrode 19 is formed on the NMOS body region 15b via the gate insulating film 18, a ground wiring 28 is provided in the NMOS source region 15s, and the ground wiring 28 is grounded. The PMOS drain region 14d and the NMOS drain region 15d are connected to the output terminal P0 through the wiring 29, and the gate electrode 17 and the gate electrode 19 are connected to the input terminal P1 through the wiring 30.

  FIG. 3 is a timing chart showing the body potential control operation of the semiconductor device of the first embodiment. In the figure, Vbp means the PMOS body potential Vbp of the PMOS transistor Q21, Vbn means the NMOS body potential of the NMOS transistor Q22, and GND means the ground level.

  Hereinafter, the body potential control operation of the semiconductor device of the first embodiment will be described with reference to FIG. The standby signal STB is set to “1” (Vdd) (inverted standby signal bar STB = “0” (GND)) in the standby period T1, which is the standby state corresponding to the inactive state of the control target logic circuit 6. Then, both the PMOS transistor Q1 and the NMOS transistor Q2, which are transistors for standby state, are turned on, the transfer gate TF1 (the NMOS gate and the PMOS gate thereof) is turned off, and the node N1 is electrically connected to the power supply VDD via the PMOS transistor Q1. The first control operation is performed in which the node N2 is grounded via the NMOS transistor Q2.

  As a result, the PMOS body potential Vbp of the PMOS transistor Q21 is set to the power supply voltage VDD, and the NMOS body potential Vbn of the NMOS transistor Q22 is set to the ground level. Therefore, the source region and body region of the PMOS transistor Q21 and NMOS transistor Q22, respectively. Since the threshold voltage Vth of each of the PMOS transistor Q21 and the NMOS transistor Q22 is set high by setting the PN junction between the first and second transistors to zero bias (lower forward bias degree), the control target logic circuit 6 is The leakage current in the standby state can be effectively suppressed.

  On the other hand, when the standby period T1 in the standby state shifts to the active period T2 in the operating state, the standby signal STB changes from “1” to “0”. Then, the PMOS transistor Q1 and the NMOS transistor Q2 are turned off, the transfer gate TF1 is turned on, the node N1 and the node N2 are electrically connected (short-circuited) via the transfer gate TF1, and the nodes N1, N2 Executes a second control operation that is in a floating state.

  As a result, the charges charged in the wiring and body region of the PMOS transistor Q21 move to the NMOS transistor Q22 side, so that the body potentials become equal and finally converge to the body potential Vbody. The body potential Vbody is a voltage value determined by the body capacitance and wiring capacitance of the PMOS transistor Q21 and NMOS transistor Q22, and is represented by the following equation (1).

  In equation (1), Cp means a PMOS parasitic capacitance, and Cn means an NMOS parasitic capacitance. The PMOS parasitic capacitance Cp mainly includes a PMOS body capacitance (PN junction capacitance between the body region of the PMOS transistor Q21 and the source region and the drain region) and a PMOS wiring capacitance (body terminal of the PMOS transistor Q21, node of the control circuit 1). Similarly, the NMOS parasitic capacitance Cn is mainly the NMOS body capacitance (between the body and the source due to the PN junction between the body region and the source region of the NMOS transistor Q21). Capacitance) and NMOS wiring capacitance (wiring capacitance existing between the body terminal of the NMOS transistor Q22 and the node N2 of the control circuit 1).

  Therefore, when the control target logic circuit 6 is in the activated state, the forward bias setting (setting with a high forward bias degree) is made between the body region and the source region of the PMOS transistor Q21, and the NMOS transistor Since the forward bias setting of (Vbody− “0” (GND)) is made between the body and source regions of Q22, the switching operation of the PMOS transistor Q21 and the NMOS transistor Q22 becomes faster, and the control target logic circuit 6 is speeded up. Can be realized.

  Subsequently, when the transition is made from the active period T2 to the standby period T3, the standby signal STB changes from “0” to “1”, and is set to a state similar to the standby period T1.

  As described above, in the semiconductor device of the first embodiment, the PMOS body potential Vbp is set to the power supply voltage VDD and the NMOS body potential Vbn is set to the ground level in the standby state by the body potential control function described above. By setting the PN junction (between the source region and the body region) to the zero bias state, the leakage current of the control target logic circuit 6 can be effectively suppressed, and each of the PMOS transistor Q21 and the NMOS transistor Q22 in the operating state. Since the forward bias is set for the PN junction, the control target logic circuit 6 can be speeded up.

  Furthermore, the body potential control of the first embodiment uses the charge stored in the PMOS parasitic capacitance Cp of the PMOS transistor Q21 in the standby state for bias setting of the PMOS transistor Q21 and the NMOS transistor Q22 in the operation state. Therefore, a separate power source for controlling the body potential is not required, and the circuit configuration can be simplified as much as it can be realized with only the commonly used power source VDD and two ground level power sources.

  FIG. 4 is an explanatory diagram schematically showing the internal state of the control target logic circuit 6 in the operating state. In the operating state, the PMOS body region 14b of the PMOS transistor Q21 and the NMOS body region 15b of the NMOS transistor Q22 are short-circuited by the electrical connection line L1 by the transfer gate TF1 (see FIG. 2). Thus, there is a DC path of the parasitic diodes D1 and D2 connected in series between the power source VDD and the ground.

  The parasitic diode D1 is a parasitic diode of the PMOS transistor Q21 by the PN junction region 21 (see FIG. 2) with the PMOS source region 14s and the PMOS body region 14b, and the parasitic diode D2 is a PN between the NMOS body region 15b and the NMOS source region 15s. It means a parasitic diode of the NMOS transistor Q22 by the junction region 22 (see FIG. 2).

  Therefore, since the forward voltage of the diode is about 0.6 V, the semiconductor device of the first embodiment does not flow through the DC path when the power supply VDD is 1.2 V or less. It becomes.

  In the operating state, the body terminals of the PMOS transistor Q21 and the NMOS transistor Q22 are in a floating state, so that the body potential Vbody varies slightly depending on the state and operation of the controlled logic circuit 6. However, if the forward voltage is VDon due to the presence of the parasitic diodes D1 and D2, the body potential Vbody falls within the range of the following equation (2) and does not vary greatly.

  FIG. 5 is a plan view showing a layout configuration of the semiconductor device according to the first embodiment, and FIG. Hereinafter, the layout structure of the semiconductor device of the first embodiment will be described with reference to FIG.

  As shown in these drawings, a buried insulating film 12 is formed on a semiconductor substrate 11, and an SOI layer 13 is formed on the buried insulating film 12. PMOS active regions 31 and 32 and NMOS active regions 33 and 34 are selectively formed in the SOI layer 13, and the active regions 31 to 34 are insulated and separated by an isolation insulating film.

  As shown in FIG. 5, a PMOS body potential wiring 43 and a VDD wiring 41 (first power supply line) are formed in parallel in the horizontal direction in the figure, and a GND wiring 42 (second power line) in the lower part in the figure. Power source line) and NMOS body potential wiring 44 are formed in parallel in the horizontal direction in the figure. The active regions 31 to 34 described above are formed between the VDD wiring 41 and the GND wiring 42.

  A PMOS active region 31 and an NMOS active region 33 are longitudinally cut in the drawing to provide a gate electrode 35, and a VDD portion extending from the VDD wiring 41 on the source region which is the PMOS active region 31 on the left side of the gate electrode 35 in the drawing. A wiring 41 a is formed, and the source region and the VDD partial wiring 41 a are electrically connected through the contact hole 38.

  On the other hand, a GND partial wiring 42 a extending from the GND wiring 42 is formed on the source region which is the NMOS active region 33 on the left side of the gate electrode 35 in the drawing, and the source region and the GND partial wiring 42 a define the contact hole 38. Electrically connected.

  Further, the gate electrode 35 is electrically connected to the wiring 45 through the via hole 39, and the NMOS active region on the right side of the gate electrode 35 in the drawing from the drain region which is the PMOS active region 31 on the right side of the gate electrode 35 in the drawing. A wiring 46 is formed over the drain region 33, and the wiring 46 is electrically connected to the drain regions of the PMOS active region 31 and the NMOS active region 33 through contact holes 38.

  The PMOS active region 32 and the NMOS active region 34 are longitudinally cut in the figure to form two gate electrodes 36 and 37, a standby signal STB is applied to the gate electrode 36, and an inverted standby signal bar STB is applied to the gate electrode 37. Applied.

  Further, an NMOS partial body potential wiring 44a extending from the NMOS body potential wiring 44 is formed on the drain region 32a, which is the PMOS active region 32 on the left side of the gate electrode 36 in the drawing, and the drain region 32a and the NMOS Partial body potential wiring 44 a is electrically connected through contact hole 38.

  A VDD partial wiring 41b extending from the VDD wiring 41 is formed on the source region 32c which is the PMOS active region 32 on the right side of the gate electrode 37 in the drawing, and the source region 32c and the VDD partial wiring 41b define the contact hole 38. Electrically connected.

  A GND partial wiring 42b extending from the GND wiring 42 is formed on the source region 34c which is the NMOS active region 34 on the left side of the gate electrode 36 in the drawing, and the source region 34c and the GND partial wiring 42b define the contact hole 38. Electrically connected.

  An NMOS partial body potential wiring 44b is formed extending from the NMOS body potential wiring 44 on the intermediate region 34b which is the NMOS active region 34 between the gate electrodes 36 and 37, and the intermediate region 34b and the NMOS partial body potential are formed. The wiring 44b is electrically connected through the contact hole 38.

  Then, from the PMOS body potential wiring 43, on the intermediate region 32b which is the PMOS active region 32 between the gate electrode 36 and the gate electrode 37, and on the drain region 34a which is the NMOS active region 34 on the right side of the gate electrode 37 in the drawing. A PMOS partial body potential wiring 43 a is formed to extend, and the intermediate region 32 b and the drain region 34 a are electrically connected to the PMOS partial body potential wiring 43 a through the contact hole 38.

  In such a configuration, the gate electrode 35 and the PMOS active region 31 constitute a PMOS transistor Q21, the gate electrode 35 and the NMOS active region 33 constitute an NMOS transistor Q22, and the gate electrode 37 and the PMOS active region 32 (intermediate region 32b). , Source region 32c) constitutes PMOS transistor Q1, and gate electrode 36 and NMOS active region 34 (intermediate region 34b, source region 34c) constitute NMOS transistor Q2, and gate electrode 36 and PMOS active region 32 (drain region 32a). , Intermediate region 32b) constitutes a PMOS gate of transfer gate TF1, and gate electrode 37 and NMOS active region 34 (drain region 34a, intermediate region 34b) constitute NM of transfer gate TF1. S gate is constructed.

  Referring to FIG. 6, PMOS transistor Q 21 has body contact region 24 below PMOS body potential wiring 43, and PMOS body potential wiring 43 and body contact region 24 are electrically connected via contact hole 38. Connected. The body contact region 24 is electrically connected to the PMOS body region 14b through the semiconductor region 13a below the partial isolation insulating film 23. Therefore, the PMOS transistor Q21 can set the potential of the PMOS body region 14b by the PMOS body potential wiring 43.

  Note that the body region of the NMOS transistor Q22 is electrically connected to the NMOS body potential wiring 44 via a body contact region (not shown) formed below the NMOS body potential wiring 44, similarly to the PMOS transistor Q21. Connected.

  As described above, the semiconductor device of the first embodiment can control the body potential of the MOS transistor formed on the SOI substrate including the semiconductor substrate 11, the buried insulating film 12, and the SOI layer 13. In the present embodiment, since the nodes N1 and N2 are in a floating state with a heavy load during the operation state, the history effect unique to the SOI substrate can be reduced.

  FIG. 7 is an explanatory diagram showing a case where a PMOS transistor Q41 corresponding to the PMOS transistor Q21 is formed on a bulk substrate. In addition, the said explanatory drawing is equivalent to the AA cross section of FIG. As shown in the figure, a body region 64 is provided in an upper layer portion of a P substrate 61, and an isolation region 62 and a body contact region 65 are provided in the same manner as the partial isolation insulating film 23 and the body contact region 24 in FIG.

  Therefore, PMOS body potential wiring 43 and body contact region 65 are electrically connected via contact hole 38, and body contact region 65 is electrically connected to body region 64 via semiconductor region 60 below isolation region 62. Connected. As a result, the PMOS transistor Q41 can set the potential of the body region 64 by the PMOS body potential wiring 43.

  FIG. 8 is an explanatory view showing the structure of an NMOS transistor Q42 corresponding to the NMOS transistor Q22 when formed on the P substrate 61. FIG.

  As shown in the figure, an N well region 66 is formed in the upper layer portion of the P substrate 61, a P well region 67 is formed in the upper layer portion of the N well region 66, and an N layer is selectively formed in the upper layer portion of the P well region 67. The source / drain regions 68 and 68 are formed, and the gate insulating film 69 and the gate electrode 70 are formed on the P well region 67 between the N source / drain regions 68 and 68, thereby forming the NMOS transistor Q42. Thus, by forming the NMOS transistor Q42 with a triple well structure, it is possible to set the body potential independent of other elements.

  As described above, the semiconductor device of the first embodiment can perform the potential control of the P well region 67, that is, the body potential control for the MOS transistor formed on the P substrate 61 which is a bulk substrate. In the case of an N substrate, the conductivity types are reversed.

<Embodiment 2>
FIG. 9 is a circuit diagram showing a circuit configuration of a semiconductor device having a charge reusing type dynamic body potential control function according to the second embodiment of the present invention.

  As shown in the figure, the semiconductor device of the second embodiment includes a control target logic circuit 6 and a control circuit 2. Since the internal configuration of the control target logic circuit 6 is the same as that of the first embodiment, description thereof is omitted.

  The control circuit 2 includes a PMOS transistor Q1, an NMOS transistor Q2, a PMOS transistor Q11, and NMOS transistors Q12 and Q13. In the PMOS transistor Q1, the source electrode is connected to the power supply VDD, the node N1 as the drain electrode is connected to the body terminal of the PMOS transistor Q21, and the inverted standby signal bar STB is received at the gate electrode.

  On the other hand, the source electrode of the NMOS transistor Q2 is grounded, the node N2 as the drain electrode is connected to the body terminal of the NMOS transistor Q22, and the gate electrode receives the standby signal STB.

  Between the nodes N1 and N2, a PMOS transistor Q11, an NMOS transistor Q13, and an NMOS transistor Q12 constituting a third switching means are inserted in series. That is, the source electrode of the PMOS transistor Q11 is connected to the node N1, the drain electrode of the NMOS transistor Q13 having a common gate and drain (diode connection) is connected to the drain electrode of the PMOS transistor Q11, and the drain electrode of the NMOS transistor Q12 is the NMOS transistor. Connected to the source electrode of Q13, the source electrode is connected to the node N2. The PMOS transistor Q11 receives a standby signal STB at its gate electrode, and the NMOS transistor Q12 receives an inverted standby signal bar STB at its gate electrode.

  FIG. 10 is a timing chart showing the body potential control operation of the semiconductor device of the second embodiment. In the figure, it is assumed that a leak current is generated in the NMOS transistor Q13 having a common gate and drain.

  Hereinafter, the body potential control operation of the semiconductor device of the second embodiment will be described with reference to FIG. The standby signal STB is set to “1” in the standby period T1, which is a standby state. Then, both the PMOS transistor Q1 and the NMOS transistor Q2 are turned on, the PMOS transistor Q11 and the NMOS transistor Q12, which are the first and second operation state transistors, are turned off, and the node N1 is connected to the power supply VDD via the PMOS transistor Q1. And the node N2 is grounded via the NMOS transistor Q2.

  As a result, the PMOS body potential Vbp of the PMOS transistor Q21 is set to the power supply voltage VDD, and the NMOS body potential Vbn of the NMOS transistor Q22 is set to the ground level, so that each of the PMOS transistor Q21 and the NMOS transistor Q22 (source region, body) Since the PN junction between the regions is set to zero bias and the threshold voltage Vth is set high, the control target logic circuit 6 can effectively suppress the leakage current in the standby state.

  On the other hand, when the standby period T1 in the standby state shifts to the active period T2 in the operating state, the standby signal STB changes from “1” to “0”. Then, the PMOS transistor Q1 and the NMOS transistor Q2 are turned off, the PMOS transistor Q11 and the NMOS transistor Q12 are turned on, and the node N1 and the node N2 are electrically connected via the PMOS transistor Q11, the NMOS transistor Q13, and the NMOS transistor Q12. At the same time, the nodes N1 and N2 are in a floating state.

  As a result, the charge charged in the wiring and body region of the PMOS transistor Q21 moves to the NMOS transistor Q22 side. At this time, since the common gate / drain NMOS transistor Q13 as potential difference setting means exists, a potential difference corresponding to the threshold voltage Vtn of the NMOS transistor Q13 is generated between the PMOS body potential Vbp and the NMOS body potential Vbn. The body potential Vbody1 in the operating state is obtained by the following equation (4).

  Therefore, in the operating state, the forward bias of the body region and the source region of the PMOS transistor Q21 is set to (Vbody1 + Vtn−Vdd) by the threshold voltage Vtn of the diode-connected NMOS transistor Q13 which is a potential difference setting means. Since the forward bias of Vbody1 is set between the body and the source region, the switching operation of the PMOS transistor Q21 and the NMOS transistor Q22 becomes faster, and the control target logic circuit 6 can be speeded up.

  Subsequently, when the transition is made from the active period T2 to the standby period T3, the standby signal STB changes from “0” to “1”, and is set to a state similar to the standby period T1.

  As described above, in the semiconductor device of the second embodiment, the PMOS body potential Vbp is set to the power supply voltage VDD and the NMOS body potential Vbn is grounded in the standby state by the above-described body potential control function as in the first embodiment. In order to set the level, the PN junction (between the source region and the body region) of each of the PMOS transistor Q21 and the NMOS transistor Q22 can be in a zero bias state, and the leakage current of the controlled logic circuit 6 can be effectively suppressed. In the operating state, the PN junctions of the PMOS transistor Q21 and the NMOS transistor Q22 are set to forward bias, so that the control target logic circuit 6 can be speeded up.

  Further, in the body potential control of the second embodiment, as in the first embodiment, the charges accumulated in the PMOS parasitic capacitance Cp of the PMOS transistor Q21 in the standby state are changed to the PMOS transistor Q21 and the NMOS transistor Q22 in the operation state. Since it is used for bias setting, the circuit configuration can be simplified because a separate power source for body potential control is unnecessary.

  FIG. 11 is an explanatory diagram schematically showing the internal state of the control target logic circuit 6 in the operating state. In the operation state, the PMOS transistor Q11 and the NMOS transistor Q12, which are the first and second operation state transistors, are turned on, so that the PMOS body region of the PMOS transistor Q21 and the NMOS body region of the NMOS transistor Q22 are NMOS. Since it is electrically connected via the transistor Q13, as shown in FIG. 11, there is a DC path of the parasitic diode D1, the NMOS transistor Q13, and the parasitic diode D2 between the power supply VDD and the ground.

  Therefore, since the forward voltage of the diode is about 0.6 V, the semiconductor device of the second embodiment has an effective circuit because no current flows through the DC path when the power supply VDD is 1.2 V + Vtn or less. It becomes. That is, the range of the effective power supply potential VDD can be expanded beyond that of the first embodiment.

  Here, when a leak current is generated in the NMOS transistor Q13 during the active period T2, the potential difference between the NMOS body potential Vbn and the PMOS body potential Vbp becomes smaller than the threshold voltage Vtn as shown in FIG. The potential rises from the potential Vbody1, and the PMOS body potential Vbp falls from the body potential Vbody2 (= Vbody1 + Vtn).

  However, since the parasitic diode D1 is turned on when the PMOS body potential Vbp reaches (Vdd−VDon), the PMOS body potential Vbp does not drop below (Vdd−VDon). On the other hand, when the NMOS body potential Vbn reaches VDon, the parasitic diode D2 is turned on, so that it does not rise above the NMOS body potential VDon.

  Thus, due to the presence of the parasitic diodes D1 and D2, the NMOS body potential Vbn and the PMOS body potential Vbp in the operating state are within the ranges of the following formulas (5) and (6) and do not vary greatly.

(Other aspects)
In the second embodiment, an example in which one NMOS transistor Q13 having a common gate / drain is inserted between the nodes N1 and N2, but an arbitrary number n of 2 or more may be provided in series.

  In this case, the relationship between the NMOS body potential Vbn and the PMOS body potential Vbp is expressed by the following equation (7), and the body potential Vbody1 of the NMOS transistor Q22 is ideally determined by the following equation (8). In equation (8), it is assumed that the threshold voltages of the NMOS transistors Q13-1 to Q13-n constituting the potential difference setting means are all the same threshold voltage Vtn.

  FIG. 12 is an explanatory diagram schematically showing the internal state of the control target logic circuit 6 in the operating state in the case where n gate / drain common MOS transistors are provided in series. As shown in the figure, a DC path of the parasitic diode D1, the NMOS transistors Q13-1 to Q13-n, and the parasitic diode D2 is formed. Therefore, the power supply VDD becomes effective when it is equal to or lower than (1.2 V + n · Vtn), and therefore the upper limit of the effective power supply VDD can be set larger than the configuration shown in FIG.

  Even when a leak current is generated in the NMOS transistors Q13-1 to Q13-n, the NMOS body potential Vbn and the PMOS body potential Vbp in the operating state are expressed by the following equation (9) due to the presence of the parasitic diodes D1 and D2. It can be contained within the range of equation (10).

  In the second embodiment, the PMOS transistor Q11 and the NMOS transistor Q12 are used to cut off between the nodes N1 and N2 in the operation state, and the first and second nodes in the standby state are reliably cut off. Yes.

  However, a configuration using only one of the PMOS transistor Q11 and the NMOS transistor Q12 is also conceivable. In the case of deleting one, in the configuration of FIG. 9, when the PMOS transistor Q11 is deleted, the drain / gate electrode of the NMOS transistor Q13 is directly connected to the node N1, thereby connecting the gate electrode of the NMOS transistor Q13 to the power supply Vdd in the standby state. It is desirable because it can be set stably.

  Further, a diode-connected PMOS transistor may be used in place of the NMOS transistor Q13.

<Others>
FIG. 13 is an explanatory view showing another aspect of the semiconductor device. In the first embodiment and the second embodiment, the control target logic circuit 6 is a logic circuit including only an inverter that is a logic gate of one unit. However, as illustrated in FIG. 7, the logic circuit includes a plurality of logic gates. The control target logic circuit block 7 may be a control target. In the example of FIG. 7, the control target logic circuit block 7 includes a NAND gate G1, an inverter G2, and a NOR gate G3.

  The gate width of each MOS transistor in the control circuit 1 (2) may be about several percent (5%) of the sum of the gate widths of all the MOS transistors constituting the control target logic circuit block 7. For example, in the case of the control circuit 1, the gate width of each of the PMOS transistor Q1 and the NMOS transistor Q2 is the gate width of all the MOS transistors constituting the NAND gate G1, the inverter G2, the NOR gate 3 and the like in the control target logic circuit block 7. It is set sufficiently smaller than the sum, and the former gate width is about several percent (5%) of the sum of the latter gate widths.

  FIG. 14 is a circuit diagram showing details of the internal configuration of the apparatus of FIG. As shown in the figure, the body potential of each of the NAND gate G1, the inverter G2, and the NOR gate G3 is controlled by the control circuit 1 shown in the first embodiment.

  The NAND gate G1 includes PMOS transistors Q23 and Q24 and NMOS transistors Q25 and Q26. The sources of the PMOS transistors Q23 and Q24 are connected to the power supply VDD, and the drains are connected in common at the node N11 (output unit). The NMOS transistors Q25 and Q26 are connected in series between the node N11 and the ground level, the input signal SA is received by the gate electrodes of the PMOS transistor Q23 and the NMOS transistor Q26, and the input signal SB is applied to the gate electrodes of the PMOS transistor Q24 and the NMOS transistor Q25. receive.

  The inverter G2 includes a PMOS transistor Q27 and an NMOS transistor Q28. The source of the PMOS transistor Q27 is connected to the power supply VDD, and the node N12 (output unit) which is the drain of the PMOS transistor Q27 is connected to the drain of the NMOS transistor Q28. The source of the NMOS transistor Q28 is grounded. The gate electrodes of the PMOS transistor Q27 and the NMOS transistor Q28 are commonly connected to the node N11.

  The NOR gate G3 is composed of PMOS transistors Q29 and Q30 and NMOS transistors Q31 and Q32. The PMOS transistors Q29 and Q30 are connected in series between the power supply VDD and the node N13 (output unit), and the gate electrode of the PMOS transistor Q29 is the node. The input signal SC is received at the gate electrode of the PMOS transistor Q30. NMOS transistors Q31 and Q32 are inserted in parallel between the node N13 and the ground level, the input signal SC is received by the gate electrode of the NMOS transistor Q31, and the gate electrode of the NMOS transistor Q32 is connected to the node N12.

  For such NAND gate G1, inverter G2 and NOR gate G3, node N1 of control circuit 1 is electrically connected to the body terminals of PMOS transistors Q23, Q24, Q27, Q29 and Q30, and node N2 is NMOS Electrically connected to the body terminals of transistors Q25, Q26, Q28, Q31 and Q32.

  As a result, the body potentials of the PMOS transistor and NMOS transistor constituting the NAND gate G1, the inverter G2, and the NOR gate G3 are controlled in the same manner as in the first embodiment. High-speed operation and low power consumption operation of the circuit block 7 are realized.

1 is a circuit diagram of a circuit configuration of a semiconductor device having a charge reuse type dynamic body potential control function according to a first embodiment of the present invention; FIG. 2 is a cross-sectional view illustrating a cross-sectional structure of a PMOS transistor 1 and an NMOS transistor 2 in the control target logic circuit illustrated in FIG. 1. FIG. 6 is a timing diagram illustrating a body potential control operation of the semiconductor device of the first embodiment. It is explanatory drawing which showed typically the internal state of the control object logic circuit at the time of an operation state. 2 is a plan view showing a layout configuration of the semiconductor device of First Embodiment; FIG. It is sectional drawing which shows the AA cross-section of FIG. It is explanatory drawing which shows the case where the transistor equivalent to the PMOS transistor shown in FIG. 6 is formed on a bulk substrate. It is explanatory drawing which showed the structure of the NMOS transistor in the case of forming on a bulk substrate. FIG. 6 is a circuit diagram of a circuit configuration of a semiconductor device having a charge recycle type dynamic body potential control function according to a second embodiment of the present invention. FIG. 10 is a timing diagram illustrating a body potential control operation of the semiconductor device of the second embodiment. It is explanatory drawing which showed typically the internal state of the control object logic circuit 6 at the time of an operation state. It is explanatory drawing which showed typically the internal state of the to-be-controlled logic circuit 6 at the time of the operation state when n MOS transistors common to gate and drain are provided in series. It is explanatory drawing which shows the other aspect of a semiconductor device. FIG. 14 is a circuit diagram illustrating details of an internal configuration of the apparatus of FIG. 13. It is a circuit diagram which shows the structure of the DTMOS circuit which is the conventional dynamic body potential control method. It is a circuit diagram which shows the structure of the VTCMOS circuit which controls the body potential of a logic circuit with a charge pump circuit. It is a circuit diagram which shows the modification of a DTMOS circuit.

Explanation of symbols

1, 2 control circuit, 6 control target logic circuit, 7 control target logic circuit block, 11 semiconductor substrate, 12 buried insulating film, 13 SOI layer, 61 P substrate, D1, D2 parasitic diode, Q1, Q21, Q11 PMOS transistor Q2, Q12, Q13, Q13-1 to Q13-n, Q22 NMOS transistor, TF1 transfer gate.

Claims (10)

A control target logic circuit including a logic gate formed on a predetermined substrate and having at least one MOS transistor capable of individually setting a potential of a body region sandwiched between a source region and a drain region;
A control circuit formed on the predetermined substrate and controlling a potential of a body region of the at least one MOS transistor;
The control circuit includes:
A first switching means having one end connected to a first power supply line to which a first power supply voltage is supplied and the other end connected to a first node;
A second switching means having one end connected to a second power supply line to which a second power supply voltage lower than the first power supply voltage is supplied and the other end connected to a second node; A body region of at least one MOS transistor is electrically connected to one of the first and second nodes;
Further comprising third switching means interposed between the first and second nodes;
The control circuit includes:
When the control target logic circuit is in a standby state, the first and second switching units are set to an on state, the third switching unit is set to an off state, and the first and second nodes are set to the first and second nodes. Performing a first control operation electrically connected to the power source of
Performing a second control operation for setting the first and second switching means to an OFF state and the third switching means to an ON state when the control target logic circuit is in an operation state;
The at least one MOS transistor has a higher degree of forward bias at the PN junction between the source region and the body region in the state during the second control operation than in the state during the first control operation. Characteristic,
Semiconductor device. The semiconductor device according to claim 1,
The at least one MOS transistor includes a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type, and a body region of the first MOS transistor is connected to the first node. A body region of the second MOS transistor is connected to the second node;
The first switching means includes a first standby state transistor of a first conductivity type that is turned on in the standby state and turned off in the operation state, and the second switching means is in the standby state. A second standby state transistor of a second conductivity type that is in an on state and is in an off state during the operation state;
Semiconductor device. The semiconductor device according to claim 2,
The third switching means includes a transfer gate that short-circuits the first and second nodes in an on state.
Semiconductor device. The semiconductor device according to claim 2,
The third switching means includes
At least one operation state transistor that is turned off in the standby state and turned on in the operation state;
Connected in series to the transistor for operation state, one end is provided on the first node side, the other end is provided on the second node side, and between the one end and the other end when supplying current. A potential difference setting means for generating a predetermined potential difference;
Semiconductor device. The semiconductor device according to claim 4,
The potential difference setting means includes a diode-connected MOS transistor,
Semiconductor device. The semiconductor device according to claim 4,
The potential difference setting means includes a plurality of diode-connected MOS transistors, each of which is diode-connected and connected in series to each other.
Semiconductor device. A semiconductor device according to any one of claims 4 to 6,
The at least one operation state transistor includes:
A first operating state transistor having one electrode connected to the first node and the other electrode connected to one end of the potential difference setting means;
A second operating state transistor having one electrode connected to the second node and the other electrode connected to the other end of the potential difference setting means;
Semiconductor device. A semiconductor device according to any one of claims 1 to 7,
The logic gate of the controlled logic circuit includes a plurality of logic gates;
Each of the plurality of logic gates includes the at least one MOS transistor;
Semiconductor device. A semiconductor device according to any one of claims 1 to 8,
The predetermined substrate includes a semiconductor substrate, an SOI substrate having a buried insulating film formed on the semiconductor substrate and an SOI layer formed on the buried insulating film,
Semiconductor device. A semiconductor device according to any one of claims 1 to 8,
The predetermined substrate includes a bulk substrate,
Semiconductor device.

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