JP2527723B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is also equipped with a logic circuit which requires a relatively large number of input / output (I / O) pins with respect to the number of logic gates. The present invention relates to the configuration of the I / O buffer of a possible CMOS master slice large scale integrated circuit device (LSI).

[Conventional technology]

FIG. 3 is a plan view showing a conventional CMOS master slice LSI. In FIG. 3, (1) is a conventional LSI chip,
(2) is a basic cell row in which basic cells, which are composed of p-channel MOS transistors and n-channel MOS transistors, and which form a logic gate are regularly arranged; (4) is an I / O buffer cell area provided on the periphery of the chip (1), (5) is power supply wiring for supplying power to the basic cell row (2), (6)
Are a power supply pad and an I / O pad provided on the periphery of the semiconductor chip (1).

In the conventional CMOS master slice LSI, the I / O buffer (4) is arranged on the periphery of the semiconductor chip (1),
I / O pads (6) for interfacing with the outside of the LSI are also arranged on the periphery of the chip (1). Power wiring is applied to the I / O buffer area (4), and the power supply to the internal area where the basic cells are arranged is connected to the power wiring on the I / O buffer area (4). It is supplied by the internal area power supply wiring (5).

FIG. 4 is an enlarged view of the portion indicated by IV in FIG. Power is supplied to the basic cell row (2) in the internal region by the internal region power supply wirings (7) and (8). (7) is
GND, (8) is the V _DD line.

[Problems to be solved by the invention]

Since the conventional CMOS master slice LSI is configured as described above, the number of I / O buffers is limited only by arranging them on the periphery of the chip. There was a problem such as high price.

The present invention has been made to solve the above problems, and a CMOS master slice LSI capable of increasing the number of I / O pins without increasing the chip size.
Aim to get.

[Means for solving problems]

In the semiconductor integrated circuit according to the present invention, basic cells are arranged under a power supply wiring layer of a constant width provided in a logic gate region inside an integrated circuit device that supplies power to an internal cell region.
The basic cell is used to form an I / O buffer.

[Action]

P channel of a basic cell arranged under a power supply wiring layer of a constant width provided in a logic gate region inside an integrated circuit device
An I / O buffer is configured by combining a MOS transistor and an n-channel MOS transistor. From these I / O buffers and I / O buffers on the periphery of the chip, through the I / O pads on the periphery of the chip or bumps provided on the chip, LS
I Exchange signals with the outside world.

Example of Invention

FIG. 1 is a plan view showing an embodiment of the present invention (1a)
Is the IC chip of this embodiment, and the same reference numerals as those in the conventional example of FIG. 3 indicate the same parts, and the description thereof will be omitted. First
In the figure, (9) is an I / O buffer area configured by using the basic cells of the basic cell row (2).

Basic cells are arranged under the power wiring (5) for supplying power from the power wiring on the I / O buffer area (4) arranged on the periphery of the chip (1a) to the internal area. The power supply wiring (5) is arranged above (2).
An input or output buffer is formed by combining the p-channel MOS transistor and the n-channel MOS transistor of the basic cell in the region (9) where the power supply wiring (5) and the basic cell column (2) intersect. FIG. 2 is an enlarged view of the portion indicated by II in FIG. In Figure 2, (7) is
GND and (8) are V _DD lines, and (9) is an area where I / O buffers are configured.

〔The invention's effect〕

As described above, according to the present invention, the basic cells are arranged under the power supply line of the constant width provided in the logic gate region inside the integrated circuit device, and the basic I /
Since I / O buffers are configured in areas other than the O buffer cell area, many I / O buffers can be mounted without increasing the chip size and reducing the number of data.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention, FIG. 2 is an enlarged view of a portion indicated by II in FIG. 1, and FIG. 3 is a conventional CM.
FIG. 4 is a plan view of the OS master slice LSI, and FIG. 4 is an enlarged view of a portion indicated by IV in FIG. In the figure, (1a) is an IC chip, (2) is a basic cell row,
(4) is the I / O buffer cell area, (5) is the power supply wiring,
(9) is an input and output (I / O) buffer area composed of basic cells. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A basic cell, which comprises a plurality of pairs of a first conductivity type MOS transistor and a second conductivity type MOS transistor opposite to the first conductivity type, and which constitutes a logic gate, is regularly arranged. Master slice type complementary MO
In the semiconductor integrated circuit device, a plurality of the above basic elements are provided between the semiconductor substrate and the power supply wiring layer of a constant width provided in the logic gate region inside the integrated circuit device for supplying to the input / output buffer cells and the logic gate. A semiconductor integrated circuit device, wherein cells are arranged, and input and output buffers are configured by using a first conductivity type MOS transistor and a second conductivity type MOS transistor in the basic cell.