JPH1187626A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To significantly reduce the layout area of a low-threshold MOS transistor used for a logic circuit. SOLUTION: In inverters Iv1-Iv4, a layout is provided such that a diffusion layer K1 is shared by transistor T4 and T8, wherein a second reference electric potential Vss is supplied through a wiring H1 and transistors T1 and T5 in which a first reference voltage VST is supplied by a wiring H4, while a diffusion layer K2 is shared by transistors T3 and T7 in which a power source VDT is supplied by a wiring H2 and transistors T2 and T6 with a power source VDD supplied through a wiring H3. The inverters Iv1-Iv4 are so laid out in a vertical direction such that the inverters Iv2 and Iv4 are positioned near the upper parts of the inverters Iv1 and Iv3, with intervals among the inverters Iv1-Iv4 are signficantly shortened for reduced area of a semiconductor chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a CMOS (Co) device used for a logic circuit.
elementary Metal Oxide S
The present invention relates to a technique effective when applied to an area-saving layout of a P-channel MOS transistor and an N-channel MOS transistor of a semiconductor device.

[0002]

2. Description of the Related Art According to studies made by the present inventor, a semiconductor integrated circuit device is a MOS integrated circuit used for a logic circuit or the like.
Higher speed is achieved by lowering the threshold voltage of the transistor.

Further, when the threshold voltage of the MOS transistor is lowered, the current at the time of standby due to the subthreshold current is increased and power consumption is increased. Sub-threshold leakage current reduction circuit (SCR
C: Subthreshold Current Re
By providing a “Duplication Circuit”, the sub-threshold current of these MOS transistors is reduced.

[0004] An example of this type of semiconductor integrated circuit device is described in detail in November 5, 1994.
Published by Shofukan Co., Ltd., Kiyoo Ito (Author), "Super LSI
Memory "P368, which is a DRAM (D
dynamic Random Access Memory
y) Describes a subthreshold current reduction method in a memory.

[0005]

However, the present inventor has found that the above-mentioned semiconductor integrated circuit device has the following problems.

That is, the sub-threshold leakage current reducing circuit requires two types of power supply voltages to be supplied during standby. For example, when a plurality of inverters are connected in series, different power supplies must be supplied alternately. Therefore, there is a problem that the diffusion layer of the adjacent MOS transistor cannot be shared and the layout area becomes large.

An object of the present invention is to provide a semiconductor integrated circuit device capable of greatly reducing the layout area of a low threshold MOS transistor used in a CMOS logic circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a first sub-threshold leak reducing circuit for reducing a sub-threshold leak current of a CMOS.
MOS transistors supplied with one and the same power supply type among different power supply types consisting of a power supply and a first reference potential and a second power supply and a second reference potential are adjacent to each other,
The layout is performed by sharing the diffusion layer of the transistor, thereby constituting the CMOS logic circuit.

In the semiconductor integrated circuit device of the present invention, a MOS transistor to which a first power supply is laid out by sharing a diffusion layer and a first reference potential laid out by sharing a diffusion layer are supplied. And a CMOS logic circuit composed of MOS transistors to be supplied and a second power supply M laid out by sharing a diffusion layer.
A CMOS logic circuit including an OS transistor and a MOS transistor to which a second reference potential is supplied laid out by sharing a diffusion layer is provided in the vertical direction in the plane of the semiconductor chip.

Further, according to the semiconductor integrated circuit device of the present invention,
A semiconductor integrated circuit device, wherein a channel, which is a signal line for transmitting a signal, is laid out between a first and second power supply and a power supply line for supplying the first and second reference potentials.

As described above, the diffusion layer is shared and C
Since the layout of the MOS logic circuit can be performed, the layout area of the MOS transistor can be largely reduced, and since the MOS transistors are laid out vertically in the plane of the semiconductor chip, the number of channels wired in the horizontal direction can be reduced. And the size of the semiconductor chip can be reduced.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a logic circuit according to one embodiment of the present invention, and FIG. 2A is an explanatory diagram of a well region of a logic circuit formed on a semiconductor chip according to one embodiment of the present invention. (B) is an explanatory view of an element layout in a logic circuit; (c) is an explanatory view of power supply and channel wiring in a third wiring layer; and (d) is an explanatory view of a power supply unit in a well region.

In this embodiment, a logic circuit 1 such as a signal transmission circuit provided in a semiconductor integrated circuit device and transmitting signals between various functional blocks at high speed includes inverters (CMOS logic circuits) Iv1 to Iv4 in series. It is constituted by a so-called inverter chain connected.

Further, the inverter Iv1, Iv3, power (first power) V _DD and the power supply voltage between the first reference potential V _ST is supplied to the inverter Iv2, Iv4 is power (second power supply ) supply voltage of V _DT and the second reference potential V _SS is electrically connected so as to supply.

Furthermore, the inverter Iv1, Iv3, the power supply V _DD and has P-channel MOS transistor and N-channel MOS transistor between the first reference potential V _ST and is constituted by connecting in series, one of the P-channel MOS transistor Is electrically connected to the power supply _VDD, and the other connection of the N-channel MOS transistor is electrically connected to the first reference potential _VST .

Meanwhile, the inverter Iv2, Iv4 is, P-channel MOS transistor and N-channel MOS transistor is constituted by connecting in series between the power supply V _DT and the second reference potential V _SS, of the P-channel MOS transistor one connection portion is connected to the power supply V _DT electrically, other connection portion of the N-channel MOS transistor is electrically connected to the second reference potential V _SS.

Here, the power supply V _DD , the power supply V _DT , the first
The reference potential V _ST and the second reference potential V _SS, are supplied by the sub-threshold leakage current reduction circuit to reduce the subthreshold current of the MOS transistors in the standby mode, the potential at the standby time, the power supply V _DD
But about 3.3V, about power V _DT is 3.1 V, the first reference potential V _ST is approximately 0.2V, the second reference potential which is approximately 0.0 V.

Further, the power supply V _DT is approximately 3.3V at the time of active of the inverter IV1 to IV4, the first reference potential V _ST
Is switched to about 0.0V to supply power.

Then, each of the inverters Iv1 to Iv4
, One of the MOSs not operating during standby
The sub-threshold current is reduced by applying a reverse bias to the transistor.

Next, the element layout of the logic circuit 1 is shown in FIG.
This will be described with reference to (a) to (d).

FIGS. 2A to 2D show the well region, the element layout, the power supply in the third wiring layer, the wiring of the signal channel, and the power supply section in the well region, respectively. Although FIGS. 2A to 2D are separately shown, they are formed so as to overlap in an actual layout.

First, as shown in FIG. 2A, for example, an N well W1 is formed on a P type silicon substrate which is a semiconductor chip, and the P well is formed with the N well W1 interposed therebetween.
A well W2 is formed.

The inverters Iv1 to Iv1
v4 is a transistor (MO) as shown in FIG.
S transistor) T1 to T8, and the transistor T
1, T2, transistors T3, T4, transistor T
5, T6 and transistors T7, T8 are connected in series.

In the transistors T1, T4, T5, and T8 in the P well W2, an impurity region functioning as a source and a drain, that is, an N-type diffusion layer K1 is formed at both sides of the channel, and is formed at the center. Similarly, in the transistors T2, T3, T6, and T7 of the N well W1, a P-type diffusion layer K2 is formed at both sides of the channel.

Further, one of the diffusion layers K1 and K2 of the transistors T1 and T2 and the gate G of the transistors T3 and T4 are electrically connected by a wiring LH of a second wiring layer.
One of the diffusion layers K1 and K2 of the transistors T4 and T3 and the gates G of the transistors T5 and T6 are also electrically connected by the wiring LH of the second wiring layer.

The other diffusion layers K1 and K2 of the transistors T5 and T6 and the gates G of the transistors T7 and T8 are also electrically connected by the wiring LH of the second wiring layer.

Next, as shown in FIGS. 2B and 2C,
The other diffusion layer K1 of the transistor T4 and the transistor T
8 is formed in common with one of the diffusion layers K1, and the second reference potential V _SS is connected to the wiring (power supply line) in the diffusion layer K1.
They are electrically connected by H1.

The other diffusion layer K of the transistor T3
2 and the one diffusion layer K2 of the transistor T7 is formed form a common, they are electrically connected by the power supply V _DT wiring (power supply line) H2 to this diffusion layer K2.

Further, the other diffusion layer K2 of the transistor T2 and one diffusion layer K2 of the transistor T6 are formed in common, and a power supply _VDD is supplied to the diffusion layer K2 by a wiring (power supply line) H3. Connected.

The other diffusion layer K of the transistor T1
1 and one diffusion layer K1 of the transistor T5 are formed in common, and the diffusion layer K1 has a first reference potential V
_ST is electrically connected by wiring (power supply line) H4.

The inverters Iv1 to Iv4
Is not laid out in the lateral direction of the semiconductor chip, but is formed so that inverters Iv1, Iv3 and inverters Iv2, Iv4 are adjacent to each other.
It is laid out vertically so that v4 is located.

Therefore, these inverters Iv1 to Iv4
Can be greatly reduced, so that the electrical connection at the input / output units of the inverters Iv1 to Iv4 is
As described above, the local wiring, that is, the wiring LH of the second wiring layer can be used. Further, these local wirings may use the wiring of the first wiring layer.

The wirings H1 to H4 are formed in a third wiring layer located above the inverters Iv1 to Iv4, and are provided between the wirings H1 and H2, between the wirings H2 and H3, and between the wirings H3 and H3. A channel SC, which is a signal line, is wired in the horizontal direction between the signal line H4 and the wiring H4.

Here, near the periphery of the diffusion layer K1, as shown in FIG. 2D, power supply sections SE1 and SE2, which are diffusion layers for supplying the power supply _VDD to the N well W1, are formed. and which, in the peripheral portion near the diffusion layer K2 and the second reference potential V _SS to supply feed unit SE3 is formed in the P-well W2.

In this case, the power supply to the N-well
The power supply V _DD is supplied to the power supply section SE3 using the wiring H5 of the wiring layer of FIG. For example, the second reference potential V _SS is supplied to the power supply unit SE1 using the wiring H6 of the second wiring layer.

Thus, in the present embodiment, diffusion layers K1 and K3 are shared by inverters Iv1 and Iv3,
Since the diffusion layers K2 and K4 are shared by the inverters Iv2 and Iv4, the inverters Iv1 to Iv1 when the sub-threshold leakage current reduction circuit is used are used.
The layout area of Iv4 can be significantly reduced.

The input / output units of the inverters Iv1 to Iv4 are connected to the wiring LH of either the first wiring layer or the second wiring layer.
Since the number of channels SC can be reduced, the width of the wirings H1 to H4 such as a power supply can be increased, and the noise resistance of the semiconductor integrated circuit device can be improved.

Further, in the present embodiment, the layout of inverters Iv1 to Iv4 formed on a P-type silicon substrate has been described.
4 may be formed, for example, on an N-type silicon substrate.

In this case, as shown in FIGS. 3A to 3D, the N well W1 is formed so as to sandwich the P well W2. In addition, each inverter Iv1
Similarly, Iv4 is not laid out in the lateral direction of the semiconductor chip.
v3, the diffusion layer K2 is connected to the inverter Iv2,
It is shared by Iv4, and is laid out vertically so that inverters Iv2 and Iv4 are located near the upper part of inverters Iv1 and Iv3.

Thus, also in this case, the low threshold MO
The layout area of inverters Iv1 to Iv4 using S transistors can be significantly reduced. Also,
Since the number of channels SC can be reduced, the wiring width of the wirings H1 to H4 such as a power supply can be increased, and the noise resistance performance of the semiconductor integrated circuit device can be improved.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above-described embodiment, a logic circuit composed of a plurality of inverters has been described. However, an N-type logic circuit composed of a low-threshold MOS transistor used in a sub-threshold leakage current reduction circuit is described.
Even when used for the layout of various logic circuits such as AND, NOR, and inverters for driving a large current, the layout area can be significantly reduced.

In the case of an inverter for driving a large current,
As shown in FIGS. 4A to 4D, by dividing and laying out the transistor T9 which is an N-channel MOS transistor, the gate G length of the transistor T10 which is a P-channel MOS transistor can be increased.

[0047]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, by laying out a CMOS logic circuit by sharing a diffusion layer,
Even if a CMOS logic circuit is formed using the sub-threshold leak reduction circuit, the layout area of the MOS transistor can be greatly reduced.

(2) In the present invention, the number of channels wired in the horizontal direction can be reduced by laying out the MOS transistors in the vertical direction on the plane of the semiconductor chip, and the semiconductor chip can be further miniaturized. can do.

(3) Further, in the present invention, the operation speed can be increased without increasing the size of the semiconductor integrated circuit device by the above (1) and (2).

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a logic circuit according to an embodiment of the present invention.

FIG. 2A is an explanatory diagram of a well region of a logic circuit formed on a semiconductor chip according to one embodiment of the present invention;
(B) is an explanatory diagram of an element layout in a logic circuit,
(C) is an explanatory view of a power supply and channel wiring in the third wiring layer, and (d) is an explanatory view of a power supply unit in a well region.

FIG. 3A is an explanatory diagram of a well region of a logic circuit formed on a semiconductor chip according to another embodiment of the present invention,
(B) is an explanatory diagram of an element layout in a logic circuit,
(C) is an explanatory view of a power supply and channel wiring in the third wiring layer, and (d) is an explanatory view of a power supply unit in a well region.

FIG. 4A is an explanatory diagram of a well region of a logic circuit formed on a semiconductor chip according to another embodiment of the present invention,
(B) is an explanatory diagram of an element layout in a logic circuit,
(C) is an explanatory view of a power supply and channel wiring in the third wiring layer, and (d) is an explanatory view of a power supply unit in a well region.

[Explanation of symbols]

Reference Signs List 1 logic circuit Iv1 to Iv4 inverter (CMOS logic circuit) W1 N well W2 P well T1 to T8 transistor (MOS transistor) K1 diffusion layer K2 diffusion layer LH wiring H1 to H4 wiring (power supply line) SC channel SE1 to SE3 power supply section H5 , H6 wiring T9, T10 transistor V _DD power supply (first power supply) V _DT power (second power source) V _ST first reference potential V _SS second reference potential

Claims (3)

[Claims] A first sub-threshold leakage reduction circuit for reducing a sub-threshold leakage current;
A semiconductor integrated circuit device comprising a CMOS logic circuit to which different power supply types including a power supply and a first reference potential and a second power supply and a second reference potential are supplied, wherein one of the different power supply types MOS to which two same power supply types are supplied
A semiconductor integrated circuit device, wherein the CMOS logic circuit is configured by laying out transistors adjacent to each other and sharing a diffusion layer of the MOS transistor. 2. The semiconductor integrated circuit device according to claim 1, wherein said MOS transistor to which a first power supply laid out by sharing a diffusion layer is supplied, and a first reference laid out by sharing a diffusion layer. A CMOS logic circuit composed of the MOS transistor to which a potential is supplied and a second reference which is laid out by sharing the diffusion layer and the MOS transistor to which the second power supply is laid out by sharing the diffusion layer; A semiconductor integrated circuit device, wherein a CMOS logic circuit comprising the MOS transistor to which a potential is supplied is provided by being laid out in a vertical direction on a plane of a semiconductor chip. 3. The semiconductor integrated circuit device according to claim 2, wherein the signal line transmits a signal between the first and second power supplies and the respective power supply lines for supplying the first and second reference potentials. A semiconductor integrated circuit device having channels laid out.