JPS63120438A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To manufacture a CMOS master slice LSI enabling I/O pin numbers to be increased without enlarging the chip size by a method wherein basic cells are arranged below power supply wiring layer feeding power to inner regions to constitute I/O buffer using the basic cells. CONSTITUTION:Multiple basic cells are arranged between a semiconductor substrate and a power supply wiring layer feeding power to an input/output buffer cell and a logic gate of a complementary MOS semiconductor integrated circuit device of master slice system to constitute the input/output buffer using the first and the second conductivity type MOS transistors in the basic cells. For example, the basic cells are arranged below the power supply wiring 5 to feed power to inner region from the power supply wiring on the I/O buffer region 4 arranged around the chip periphery of 1a to make the power supply wiring 5 pass on the basic cell rows 2. Finally, P channel MOS transistor and N channel MOS transistor of basic cells in the region 9 wherein power supply wiring 5 and the basic cell row 2 intersect with each other are combined with each other to constitute the output buffer.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention can also be implemented with a logic circuit that requires a relatively large number of input/output (Ilo) bins compared to the number of logic gates E. The present invention relates to the configuration of the I10 buffer of a CMOS master slice large-scale integrated circuit device (LSI).

[Conventional technology]

FIG. 3 is a plan view showing a conventional CMOS master slice LSI. In FIG. 1, C1) is a conventional LSI chip, and (2) is a p-channel MOS transistor and an n-channel MOS transistor, which constitute a logic gate. C3) is a wiring band region for connecting logic gates, (4) is an I10 banfa cell region provided at the periphery of step [1],
(5) is the power supply wiring for supplying power to the basic cell row (2), and (6) is the power supply wiring (4) installed on the periphery of the semiconductor chip (1).
) are arranged around the periphery of the semiconductor chip (1), and the LS
I10 pad for interfacing externally (
6) are also arranged around the periphery of the balance wheel (1). Power supply wiring is provided in the I10 buffer area (4).

Power is supplied to the internal area where the basic cells are arranged by an internal area power wiring (5) connected to the JZ power wiring and the engineering 10 bumper area (4).

FIG. 4 is an enlarged view of the bulge portion indicated by ■ in FIG. 3. Power supply wiring for the internal region +7), (8) l Therefore, power is supplied to the basic cell column (2) of the internal region.

(7) is the GND line, and (8) is the VDD line.

[Problem that the invention seeks to solve]

Since a conventional CMOS master slice LSI is configured as described above, there is a limit to the number of I10 bumpers that can be arranged just around the edge of the chip, and if the chip size is increased to increase the number of I10 bins, the chip cost will increase. There were problems such as high prices.

This invention was developed in order to solve the above-mentioned problems.
The object of the present invention is to obtain a CMOS master slice LSI that can increase the number of bins.

Basic cells are also arranged under the power wiring layer that supplies power to the internal cell area, and these basic cells are utilized.

This is a configuration of an I10 buffer.

[Effect]

9. The I10 buffer is constructed by combining the p-channel MOS transistor of the basic cell and the n-channel MO8) transistor. These I10 buffers and the Ilo buffer at the periphery of the chip are exchanged. [Embodiment of the invention] 嘱Figure 1 is a plan view showing one embodiment of this invention.

(1a) is an IC chip of this embodiment, and the same reference numerals as in the conventional example in FIG. 3 indicate equivalent parts, and the description thereof will be avoided from duplication. In FIG. 1G, reference numeral 4 indicates a 1/10 buffer area constructed using the basic cells of the basic cell row (2).

A 10-bumper area (
4) Arrange the basic cells in F of the power wiring (5) for supplying power from the upper power wiring to the internal area, and place the power wiring (5) so that it passes above the basic cell row (2). do.

The area where the power distribution @ (5) and the basic cell row (2) intersect (
The p-channel MOS transistor of the basic cell in 9) and the n-channel MOS transistor in 8) are combined to form an input or output buffer. FIG. 2 is an enlarged view of the portion indicated by ■ in FIG. 1. In Figure 2 F, (7
) is GND, (8) is V. D line, (9)
is the area where the I10 buffer is configured.

〔Effect of the invention〕

As mentioned above, if this F3Al problem occurs, basic cells are also arranged under the power supply line, and using these basic cells, the original I1
Since a 10-bandwidth module is configured in addition to the 0-bandwidth cell area, the chip size is increased. Therefore, many "engine" buffers can be installed without reducing the number of gates.

[Brief explanation of the drawing]

Figure 1 is a plan view showing an embodiment of this invention, and Figure 2 is @
1. FIG. 1 is an enlarged view of the part shown as 2, and FIG. 3 is a plan view of a conventional CMOS master slice LSI. FIG. 4 is an enlarged view of the portion shown as ■ in FIG. 3. In Figure ζ, (1a) is the IC chip, (2) is the basic cell row, (4) is the I10 breadth cell area, (5) is the power supply wiring, and (9) is the human power and output (I
lo) Buffer area. Note that the same reference numerals in Figure 1 indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A master in which basic cells to constitute a logic gate, each consisting of a pair of a plurality of first conductivity type MOS transistors and a second conductivity type MOS transistor opposite to the first conductivity type, are regularly arranged. Slicing complementary MO
In the S semiconductor integrated circuit device, a plurality of the basic cells are arranged also between the semiconductor substrate and a power supply wiring layer that supplies input/output buffer cells and the logic gate, and a first conductivity type in the basic cells is arranged. MOS transistor and second
1. A semiconductor integrated circuit device comprising an input and an output buffer using conductive type MOS transistors.