JPH0834247B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standard cell type semiconductor integrated circuit device for designing a mask layout using a computer.

2. Description of the Related Art Conventionally, a mask pattern of this type of semiconductor integrated circuit is
The configuration was as shown in FIG. In FIG. 2, 11
Is a cell row of cells having a built-in circuit function, 12 is a circuit function cell having a built-in circuit function, 13 is a cell having no built-in circuit function, and is simply a circuit function cell containing a circuit function
It is called a through cell for connecting between 12 and mainly connects power supply lines, wells, etc. between adjacent circuit function cells 12 and, for some reason, circuit function cells.
This through cell when the signal line cannot pass above 12
It is often used when placing 13 to make a space between each circuit functional cell 12 and passing a signal line.

Reference numeral 14 denotes a dummy cell, which has the same structure as the through cell 13 but is used when adjusting the width of the cell row 11. Reference numeral 15 is a wiring region for wiring a signal line between the cell columns 11.

With such a conventional structure, as shown in FIG. 2, when the unit cells are arranged to form a block, the through cell 13 or the dummy cell 14 is formed in a considerable area in the cell row 11. May occupy.

On the other hand, as a phenomenon peculiar to a CMOS type semiconductor, there is a latch-up phenomenon. There are various measures to prevent this,
As one of the countermeasures, there is a method of reducing contact between the substrate and the power supply line to reduce the substrate resistance. In the conventional method, the contact between the substrate and the power supply line is made only in the cell region including the circuit function. Therefore, when a large number of through cells and dummy cells are inserted, the substrate resistance tends to be high, and the latch-up withstanding capacity tends to be low.

The present invention solves such a problem, and an object of the present invention is to enhance the latch-up resistance when designing a block using standard cells.

Means for Solving the Problem In order to solve this problem, the present invention has a structure in which a contact between a substrate and a power supply line is provided in a through cell or a dummy cell to reduce the substrate resistance.

Function With this configuration, the potential of the power source and the substrate can be applied to any region in the cell row, and the latch-up withstand capability can be improved.

Embodiment FIG. 1 is a mask pattern diagram of a through cell according to an embodiment of the present invention. An example of a P-well type CMOS is shown. The dummy cells also have the same structure. In FIG. 1, 1 is a VDD potential metal wiring layer, 2 is a VSS potential metal wiring layer,
Reference numeral 3 is a P well, 4 is an N type diffusion layer, and 5 is a contact. The VDD potential is grounded to the substrate through this contact. Further, 6 is a P-type diffusion layer, and similarly P well 3
The inside is also grounded to the VSS potential. Depending on the size of the free area,
A plurality of dummy cells can be arranged.

Although FIG. 1 shows an example of the P-well CMOS integrated circuit, it can be applied to the N-well CMOS and other CMOS integrated circuits.
Also, due to various restrictions, only the P-type substrate or only the N-type substrate may have a potential.

As described above, according to the present invention, by arranging a through cell or a dummy cell, which is in contact with a power source and a substrate, in a vacant region of a cell row, it is possible to enhance latch-up without increasing the chip area. The effect of being able to be obtained is obtained.

[Brief description of drawings]

FIG. 1 is a plan pattern diagram showing the structure of a through cell used in one embodiment of the present invention, and FIG. 2 is a mask pattern diagram of a conventional example device. 1 ... VDD potential metal wiring layer, 2 ... VSS potential metal wiring layer,
3 ... P-well, 4 ... N-type diffusion layer, 5 ... Contact, 6 ... P-type diffusion layer.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/04 A D

Claims (1)

[Claims] 1. A semiconductor integrated circuit device in which a plurality of circuit function cells are laterally arranged, wherein a substrate is connected to a power supply potential between at least one of the circuit function cells and a circuit function is not built in. A semiconductor integrated circuit device having a cell inserted therein.