JP3175678B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device with reduced electromagnetic interference.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, various circuits such as a gate array and a memory are arranged and formed on a single semiconductor substrate. For example, in a memory circuit, a decoder, a sense amplifier circuit, and an input / output circuit are provided. In the gate array, input / output circuits are arranged at high density. For this reason, an electromagnetic field generated in the circuit may be a factor, and electromagnetic interference may occur in an electronic component close to the semiconductor integrated circuit device. For example, consider a case where a plurality of circuits C1 to C3 are laid out in parallel as shown in FIG. That is, VCC (power supply) composed of aluminum wiring along the periphery of the semiconductor substrate
A line VCC0 and a GND (ground) line GND0 are provided in parallel, and each of the circuits C1 to C3 is connected to these VCC lines and GND.
And VCC lines, respectively,
0 and the GND line GND0 via a through hole TH. Each circuit has a configuration in which a current flows from the VCC line VCC0 to the GND line GND0. Therefore, when each circuit is operated and a current flows through the circuit in the direction shown by the arrow in the figure, an electromagnetic field is generated based on the current, and this causes electromagnetic interference (EMI) in electronic components arranged in close proximity. ). In particular, when the plurality of circuits C1 to C3 are operated at the same time, the direction of current in each circuit is in the same direction, so that the generated electromagnetic field is also in the same direction, and these electromagnetic fields are superimposed. However, the above-mentioned electromagnetic interference cannot be ignored.

For example, a memory generally includes an input circuit, a cell, a sense amplifier circuit, and an output circuit on a semiconductor substrate. In such a memory, by applying a desired voltage to an input terminal and a power supply terminal, information stored in a cell is read by a sense amplifier circuit and output to an output terminal through an output circuit. FIG. 5 shows an example of a sense amplifier circuit in such a memory.
P channel MOS transistor Q1 and N channel MO
S transistors Q2 and Q3, which are connected to a cell and an output circuit (not shown),
And GND. FIG. 6 shows an example of the layout, in which a plurality of sense amplifier circuits SA1 and SA2 are arranged corresponding to a plurality of cells CEL1 and CEL2, respectively, which are connected to a VCC line VCC0 and a GND line GND0, respectively. These sense amplifier circuits SA1, SA2
Is a current detection type sense amplifier circuit used for a non-volatile memory such as an EPROM. As shown in FIG. 5, the current detection type sense amplifier circuit includes a P-channel MOS transistor Q1 and N-channel MOS transistors Q2 and Q3. . Then, the VCC lines VCC0 and G are connected by through holes TH.
Electrical connection to the ND line GND0 is made. In these sense amplifier circuits SA1 and SA2, the current flowing from the source to the drain of the P-channel MOS transistor Q1 and from the drain to the source of the N-channel MOS transistor Q2 may or may not flow depending on the cell state. Therefore, the potential of the contact connected to the output circuit changes, and the potential of the contact is compared with the potential of the reference circuit (not shown), so that the output of the output circuit indicates a high level or a low level as information.

In such a sense amplifier circuit,
During the above-described operation, the VCC line VCC0 is connected to the GND line GN
Since the current flows toward D0, an electromagnetic field is generated in each of the sense amplifier circuits SA1 and SA2 during operation. Therefore, when a plurality of sense amplifier circuits are operated at the same time, the electromagnetic fields generated in each sense amplifier circuit are superimposed, and the electromagnetic field strength of the entire memory is increased. In particular, in recent memories in which the number of cells or the number of sense amplifier circuits is increased with the increase in memory capacity, the electromagnetic field strength of the entire memory becomes remarkable with the increase in the number of sense amplifier circuits. In addition, electromagnetic interference to nearby electronic components becomes increasingly non-negligible.

[0005] Such electromagnetic interference is not limited to the above-described sense amplifier circuit of the memory, but rather includes input / output circuits and other circuits in various semiconductor integrated circuit devices, particularly a plurality of circuits having the same or similar configuration. This also occurs in a semiconductor integrated circuit device having a configuration in which are arranged.

[0006]

As described above, in the conventional semiconductor integrated circuit device, a plurality of circuits are connected to the VCC line and the GND line.
Since they are arranged in the same direction with respect to the line, when each circuit is operated, current flows in the same direction, and an electromagnetic field in the same direction is generated. For this reason, the electromagnetic field in each circuit is superimposed, the electromagnetic field strength of the entire semiconductor integrated circuit is increased, and the effect of electromagnetic interference on electronic components arranged close to the semiconductor integrated circuit device cannot be ignored. ing.

An object of the present invention is to provide a semiconductor integrated circuit device capable of eliminating or reducing the influence of electromagnetic interference in a semiconductor integrated circuit device having a configuration in which a plurality of circuits are arranged.

[0008]

According to the present invention, there are provided a first high potential wiring and a first low potential wiring extending along one side on a semiconductor substrate, and a first high potential wiring and a first high potential wiring. Low electricity
A second high-potential wiring and a second low-potential wiring extending in parallel with the required wiring at a required interval; and a plurality of circuit to be set, between each of the plurality of circuit the <br/> first high potential wire and the second low-potential wiring or said second high-potential wire, and each of which is configured to be electrically connected between said first low-potential wiring.

[0009] Since a plurality of circuits have currents flowing in opposite directions to each other, the direction of the electromagnetic field generated by the current is also opposite between the circuits having different current directions, and these electromagnetic fields are mutually reciprocal. Offset by For this reason,
The electromagnetic field as a whole of the semiconductor integrated circuit device is eliminated,
Alternatively, the influence of the electromagnetic field on the electronic components arranged close to each other can be ignored.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a layout diagram on a semiconductor integrated circuit device showing a basic configuration of the present invention. A first VCC line V is provided on a semiconductor substrate constituting a semiconductor integrated circuit device.
CC1 and the first GND line GND1 extend in parallel with each other, and are separated from the second VCC line VCC2 by a predetermined distance.
The GND line GND2 extends in parallel. In addition, a plurality of circuits, here, three circuits C1, C2, and C3 are arranged along the extending direction of these VCC lines and GND lines. The plurality of circuits are electrically connected to the VCC line and the GND line, respectively, by through holes TH.
Connected to D line. That is, in the example of FIG. 1, the circuit C1 disposed at the center is the second VCC line VCC.
2 and the first GND line GND1, and the circuits C2 and C3 arranged on both sides thereof are connected to the first VCC line VC1.
It is connected between C1 and the second GND line GND2.

Therefore, in this configuration, each of the circuits C1 to C1
When C3 operates, as shown by the arrow in the figure, the central circuit C1 causes a current to flow upward from the second VCC line VCC2 toward the first GND line GND1, and the circuit C2 on both sides. , C3 are the first VCC line VC
A current flows from C1 to the second GND line GND2 downward in the drawing. For this reason, an electromagnetic field in the clockwise direction is generated in the center circuit C1, and the circuits C2 and C2 on both sides are generated.
At C3, an electromagnetic field in the counterclockwise direction is generated. As a result, the direction of the electromagnetic field in the adjacent circuit is reversed,
The electromagnetic fields of adjacent circuits cancel each other, resulting in a reduction in the strength of the electromagnetic field. Therefore,
When the arranged circuits have the same configuration and the current flowing in each circuit is equal, and when the plurality of circuits is an even number, the electromagnetic field of the semiconductor integrated circuit device as a whole is canceled out by the cancellation of the electromagnetic field in the adjacent circuit. It becomes almost 0. When an odd number of circuits are arranged, the electromagnetic field of the entire semiconductor integrated circuit device becomes an electromagnetic field of one circuit, and can be suppressed to a weak one. This makes it possible to eliminate or suppress the influence of electromagnetic interference on the electronic components arranged in close proximity.

Next, a specific example of the present invention will be described. FIG. 2 is a plan layout diagram showing an example in which the present invention is applied to the sense amplifier circuit of FIG. 5 described in the prior art. Along a peripheral portion of a semiconductor substrate forming a memory, a first VCC line V
CC1 and the first GND line GND1 extend in parallel with each other, and the second VCC line VCC2 and the second
GND line GND2 extends in parallel. These VCC
The line and the GND line are made of aluminum wiring. And
A plurality of, here two sense amplifier circuits SA1 and DA2 are arranged so as to extend over the VCC line and the GND line and along the extending direction. As shown in FIG. 5, the sense amplifier circuits SA1 and SA2
It comprises a channel MOS transistor Q1 and N-channel MOS transistors Q2, Q3, and is electrically connected to the corresponding cells CEL1, CEL2, respectively. The MOS transistors Q1, Q2, Q3 are:
In the sense amplifier circuit SA2 on the right side in the figure, the first V
It is connected between the CC line VCC1 and the second GND line GND2, and is connected between the second VCC line VCC2 and the first GND line GND1 in the sense amplifier circuit SA1 on the left side of the drawing.

That is, in the case of this embodiment, in the sense amplifier circuit SA2 on the right side of the figure, an N-channel MOS
The source of the transistor Q2 and the source of the P-channel MOS transistor Q1 are connected to the first VCC line VCC1 by through holes TH, respectively, and the drain of the N-channel MOS transistor Q2 and the gate of the P-channel MOS transistor Q1 are respectively connected to the second by the through holes TH.
It is connected to GND line GND2. In the sense amplifier circuit SA1 on the left side of the figure, the source of the N-channel MOS transistor Q2 and the P-channel MOS transistor Q2
1 are connected to the second VC by through holes TH.
The drain of N-channel MOS transistor Q2 and P-channel MOS transistor Q1 are connected to C line VCC2.
Are connected to the first GND by the through holes TH, respectively.
It is connected to the line GND1.

Therefore, during the operation of each sense amplifier circuit, the drain of the N-channel MOS transistor Q2 connected to the first VCC line VCC1 and the source of the N-channel MOS transistor Q2 connected to the second GND line GND2 in the sense amplifier circuit DA2 on the right side in the figure. And the N-channel MOS connected to the second VCC line VCC2 in the sense amplifier circuit SA1 on the left side of the figure.
From the drain of the transistor Q2 to the first GND line GND1
, The currents flowing to the source of the N-channel MOS transistor Q2 are in opposite directions, and the electromagnetic fields generated in the sense amplifier circuits SA1 and SA2 are also in opposite directions and cancel each other out.
Becomes Therefore, in a memory having a large number of sense amplifier circuits, if the currents flowing through the sense amplifier circuits are equal, if the number of sense amplifier circuits is even, the electromagnetic fields are completely canceled out and the electromagnetic field of the entire memory is reduced. The field is 0, and in the case of an odd number, only the electromagnetic field in one sense amplifier circuit is left. As a result, even when the number of sense amplifier circuits is increased with an increase in memory capacity, the electromagnetic field strength of the entire memory can be made extremely small, and the effect of electromagnetic interference on nearby electronic components can be ignored. It becomes possible.

Here, according to the present invention, first and second VCC lines VCC1, BCC2 and GN
Since the D lines GND1 and GND2 are provided, an arrangement space on the semiconductor substrate is required correspondingly, and it is conceivable that the density of the semiconductor integrated circuit device may be reduced. However, since the number of circuits borne by each VCC line and GND line is reduced by half with the doubling of each VCC line and GND line, the line width of each VCC line and GND line can be reduced by half. The layout area is rarely increased. For example, the line width of the VCC line and the GND line required for the current flowing through each sense amplifier circuit is set to 100 μm.
m, in the conventional memory layout shown in FIG. 6, one VCC line VCC0 and one VCC line VCCO are used for the currents flowing through the two sense amplifier circuits SA1 and DA2, respectively.
The line width of the ND line GND0 is 200 μm, and the width when the VCC line and the GND line are arranged in parallel needs to be 400 μm, ignoring the space between the lines. In contrast,
In the case of the embodiment of FIG. 2, two VCC lines VCC
1 and BCC2 and the GND lines GND1 and GND2 each have only one sense amplifier circuit connected thereto, so that the first and second VCC lines VCC1, VCC2 and GND are connected to each other.
The line width of each of the D lines GND1 and GND2 is 100 μm, and the width when these lines are located in parallel is 400 μm if the interval between the lines is ignored. Therefore, VC
The area occupied by the C line and the GND line becomes equal. Actually, since the space between each VCC line and the GND line is required, the arrangement area is slightly increased in the configuration of the present invention.
Its value is small and almost negligible.

Next, a second embodiment of the present invention will be described. FIG. 3 is a plan layout diagram of an embodiment in which the present invention is applied to an output circuit. The first VCC line VCC1 and the first
A GND line GND1 extends in parallel with the second VCC line VCC2 and a second GND
The D line GND2 extends in parallel. In addition, the first
A plurality of output pads PAD1 and PAD2 are arranged along the extending direction between the VCC line and the GND line, and the second VCC line and the GND line. Output circuits OC1 and OC2 are arranged. It should be noted that each of the VCC lines VCC1, VCC2 and GND lines GND1, GND2 and output pads PAD1, PAD
AD2 is formed of aluminum. Each of the output circuits OC1 and OC2 here comprises one P-channel MOS transistor Q4 and one N-channel MOS transistor Q5. Each transistor has a gate connected to an internal circuit and a source connected to an internal circuit. , The drain is connected to the VCC lines VCC1, VCC2 or GND lines GND1, GND2 via the through holes TH.
Or the output pads PAD1, PAD
2 are connected. In the adjacent output circuit, in one output circuit OC1, the P-channel MOS transistor Q4 is connected to the second VCC line VCC2, the N-channel MOS transistor Q5 is connected to the first GND line GND1, and the other output circuit adjacent thereto is connected. In the circuit OC2, the P-channel MOS transistor Q4 is connected to the first VCC line VCC1
Further, the N-channel MOS transistor Q5 is connected to the second GND line GND2.

Therefore, in the transition of the internal signal change, in the output circuit OC1, the second GND line is connected to the second GND line VCC2 from the source to the drain of the P-channel MOS transistor Q4 and from the drain to the source of the N-channel MOS transistor Q5. A current flows through the line GND2, and the output circuit OC2 outputs the first VCC line VC
A current flows from C1 to the second GND line GND2 through the source and drain of the P-channel MOS transistor Q4 and further from the drain to source of the N-channel MOS transistor Q5. Since these current directions are opposite to each other, the electromagnetic fields generated by the currents cancel each other, and as a result, the electromagnetic field amount becomes zero. Therefore, even when a large number of output circuits are arranged, assuming that the currents flowing through the respective output circuits are equal, the adjacent output circuits cancel each other out of electromagnetic fields. The field strength becomes 0 when the number of output circuits is even, and becomes one value when the number of output circuits is odd, so that the influence of the electromagnetic interference becomes almost negligible.

In this embodiment, the first and second VCC lines VCC1 and VCC2 and the GND line GND are also provided.
1 and GND2 are VCC line and G
Each VCC line, G
The line width of the ND line can be reduced by half, and the area occupied by these first and second VCC lines and GND lines is almost the same as that of one VCC line and GND line, respectively. It is possible to realize a high-density semiconductor integrated circuit device with almost no influence on the degree of integration in the above.

Here, in the present invention, when a large number of circuits are arranged in one direction, the direction of the current of each circuit may be alternate, that is, alternately reversed. The direction may be reversed every other (n is a positive number of 2 or more). If the value of n is too large in the case of every nth unit, there is a possibility that regions where the electromagnetic fields in opposite directions cannot cancel each other may occur. However, by appropriately setting the number of n units, the entire semiconductor integrated circuit device becomes It is possible to obtain a sufficient effect as a canceling effect of the electromagnetic field.

In the above embodiment, the present invention is applied to a sense amplifier circuit and an output circuit of a memory. However, in a semiconductor integrated circuit device, a plurality of identical or similar circuits are arranged. The present invention can be similarly applied to a semiconductor integrated circuit device including In some cases, one VCC line and G
By forming the wiring path leading from the ND line to each circuit in the opposite direction between the adjacent circuits, it is possible to reverse the current flowing direction in the adjacent circuit while having one VCC line and GND line. Orientation is also possible.

[0021]

As described above, the present invention can be applied to a plurality of times.
The paths are respectively a first high potential wiring and the second low potential wiring
Or between the second high potential wiring and the first low potential wiring.
Since each of which is electrically connected between the voltage line, each <br/> plurality of circuits becomes Rukoto directed in the reverse direction flow direction of the respective currents with each other, the current between the direction of the current is different circuits The directions of the electromagnetic fields generated by these fields are also reversed, and these electromagnetic fields cancel each other. For this reason, the electromagnetic field as a whole of the semiconductor integrated circuit device is eliminated or suppressed, the influence of the electromagnetic field on the electronic components arranged in close proximity can be ignored, and the electromagnetic interference can be prevented beforehand.
Further, even when the first and second high-potential wirings and the low-potential wiring are provided in order to reverse the direction of the current in each circuit, the width of each wiring is reduced by reducing the current flowing through each wiring. Therefore, the wiring layout area does not increase due to the increase in the number of wirings, and a high-density semiconductor integrated circuit device can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic layout diagram for explaining a basic configuration of the present invention.

FIG. 2 is a layout diagram of a sense amplifier circuit according to the first embodiment of the present invention.

FIG. 3 is a layout diagram of an output circuit according to a second embodiment of the present invention.

FIG. 4 is a schematic layout diagram for explaining a conventional problem.

FIG. 5 is a circuit diagram illustrating an example of a sense amplifier circuit.

FIG. 6 is a layout diagram of an example of a conventional sense amplifier circuit.

[Explanation of symbols]

 VCC1 First VCC line VCC2 Second VCC line GND1 First GND line GND2 Second GND line SA1, SA2 Sense amplifier circuit OC1, OC2 Output circuit CEL1, CEL2 Cell PAD1, PAD2 Output pad Q1 to Q5 MOS transistor TH Through hole

Claims (5)

(57) [Claims] 1. A first high potential wire and a first low-potential wiring which extends along one on a semiconductor substrate, these first
Of the second high-potential wiring and the second low-potential wiring which extends parallel keep predetermined distance between the high potential wiring and a first low potential wiring, the first and second respective high-potential wire and a low between the potential line and a plurality of circuit are arranged along the extending direction of said plurality of circuit the <br/> second low-potential wiring and each of the first high-potential wiring, or a semiconductor integrated circuit device, characterized in that each of which is electrically connected between said second high-potential wiring and the first low-potential wiring. 2. The semiconductor integrated circuit device according to claim 1 , wherein an even number of the plurality of circuits are provided, and half of the circuits and the remaining half of the circuits are set so that the currents flow in opposite directions. Wherein said plurality of circuits provided an odd number, according to claim 1 in which the circuit of the other half, except one of them, the circuit of the other half are set so that a current respectively the opposite direction 3. The semiconductor integrated circuit device according to 1. 4. The semiconductor device according to claim 1, wherein said plurality of circuits are sense amplifier circuits of a semiconductor memory device.
3. The semiconductor integrated circuit device according to any one of 3 . Wherein said plurality of circuits, a semiconductor integrated circuit device according to any one of claims 1, characterized in that an output circuit 3.