JPS62114259A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS62114259A JPS62114259A JP60255257A JP25525785A JPS62114259A JP S62114259 A JPS62114259 A JP S62114259A JP 60255257 A JP60255257 A JP 60255257A JP 25525785 A JP25525785 A JP 25525785A JP S62114259 A JPS62114259 A JP S62114259A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- input
- output circuit
- output
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特に半導体チップ
上の回路ブロックのレイアウトに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to the layout of circuit blocks on a semiconductor chip.
一般に、半導体集積回路装置は、第２図のような回路構
成を有している。外部からの信号は入力端子から静電保
護部を介して入力回路に入シ、外部信号レベルから内部
信号レベルに変換される。Generally, a semiconductor integrated circuit device has a circuit configuration as shown in FIG. A signal from the outside enters the input circuit from the input terminal via the electrostatic protection section, and is converted from the external signal level to the internal signal level.
内部回路においては所望の論理をと〕、出力回路におい
て出力端子に接続される外部負荷全駆動する。出力前段
回路は、内部回路の駆動能力が、出力回路の入力容量に
対して小さく、内部回路から出力回路への遅延が大きい
場合に設けらｎるものである。まｆｃ第２図において出
力回路と出力端子間にも静電保護部が示さｎているが、
一般には出力回路では寄生ダイオード等が静電保護とし
て働き特別な静電保護部を要さない場合もめる。The internal circuit uses a desired logic], and the output circuit drives all external loads connected to the output terminal. The output pre-stage circuit is provided when the driving capacity of the internal circuit is small relative to the input capacitance of the output circuit and the delay from the internal circuit to the output circuit is large. In Fig. 2, an electrostatic protection section is also shown between the output circuit and the output terminal.
Generally, parasitic diodes and the like act as electrostatic protection in the output circuit, and there are cases where a special electrostatic protection section is not required.
第３図は、第２図の回路構成を有する従来の半導体集積
回路装置のチップレイアウトの一例である。第３図は、
パ・ソケージの入力あるいは出力端子とボンディングワ
イヤ等でつながｎるバッドｌに対応して配置された入力
回路２、出力前段回路４、出力回路及び静電保護部５と
内部回路３を示している。第３図のレイアウトは、共通
の拡散工程によって作らｎた半導体基板を配線工程で品
種機能分化を行なうマスタスライス方式半導体集積回路
装置の一般的なチップレイアウトである。種々の品種機
能全分化させるためには、設計の信頼度の上からレイア
ウト構成をむしろ単純化する必要があ勺、第３図におい
てもパッド１、出力回路及び静電保護部５％出力前段回
路４、入力回路２とをひとつのブロックとして、内部回
路３の周囲に規則的に配置した構成をとっている。FIG. 3 is an example of a chip layout of a conventional semiconductor integrated circuit device having the circuit configuration shown in FIG. Figure 3 shows
It shows an input circuit 2, a pre-output circuit 4, an output circuit, an electrostatic protection section 5, and an internal circuit 3, which are arranged corresponding to the pads 1 connected to the input or output terminals of the P/S cage by bonding wires, etc. . The layout shown in FIG. 3 is a general chip layout of a master slice type semiconductor integrated circuit device in which semiconductor substrates manufactured by a common diffusion process are separated into product types and functions in a wiring process. In order to completely differentiate the functions of various products, it is necessary to simplify the layout configuration from the viewpoint of design reliability.As shown in Figure 3, pad 1, the output circuit, and the electrostatic protection section 5% output pre-stage circuit. 4. The input circuit 2 is arranged as one block and regularly arranged around the internal circuit 3.
第３図葡見て、明らかなように、チップコーナ部６の処
置が従来から問題となっていた。チップコーナ部６を全
く活用しないのは集積度の点で好ましくないはか）でな
く、パッドを配置できるにもかかわらず、対応する入出
力回路セルがないために外部に引き出す信号本数が制限
されてしまうという欠点がめる。このため、このチップ
コーナ部に、他と異なる形状の入出力回路セルをおいた
シ、電源引き出し部として用いる事の処置を施すことが
行なわｎているが、前者は設計工数の増大、及び、設計
の信Ｘ＝Ｖの点で好ましくない。またこの場合他と電気
的特性の異なる入出力回路セルが存在することになシ、
特性の最大最小値幅が大きくなる原因となり、この半導
体チップ全組み込むシステムにおける設計を難しくして
しまう。後者は電源位置の固定化を招き、特に、マスタ
スライス方式集積回路装置の様に、複数種類のパッケー
ジ搭載を想定する時、そのパッケージ種類数の制限ｔも
たらす他、ユーザの電源ビン位置に対する多様な要求に
対応で＠なくなってしまうという欠点がある。As is clear from FIG. 3, the treatment of the chip corner portion 6 has been a problem in the past. Not only is it undesirable from the point of view of integration to not utilize the chip corner section 6 at all, but even though pads can be placed, the number of signals drawn out to the outside is limited because there is no corresponding input/output circuit cell. The disadvantage is that it is difficult to understand. For this reason, it is common practice to place an input/output circuit cell with a different shape to the chip corner and use it as a power supply drawer, but the former increases the number of design steps and This is unfavorable from the point of view of design principle: X=V. Also, in this case, there will be input/output circuit cells with different electrical characteristics from others.
This causes the maximum and minimum width of the characteristics to become large, making it difficult to design a system in which all of the semiconductor chips are incorporated. The latter leads to fixation of the power supply position, and especially when it is assumed that multiple types of packages are installed, such as in a master slice integrated circuit device, the number of package types is limited. There is a drawback that @ disappears when responding to requests.
本発明の目的は、設計の信頼度を損うことなく集積度を
同上させ、従来よシも相対的に多くの信号を外部に引き
出せる様にすることにある。An object of the present invention is to increase the degree of integration without impairing the reliability of the design, and to make it possible to draw out relatively more signals to the outside than in the past.
本発明の半導体集積回路装置は所望の論理を構成する内
部ゲートセル群とバッファ機能を有する入出力回路セル
群とから構成さする半導体集積回路装置において、入出
力回路セル群の各入出力回路セルが七扛それ複数の回路
単位から構成さｎｌかつ各入出力セルを構成する回路単
位の相対位置関係が複数種類存在することｔ％徴として
いる。The semiconductor integrated circuit device of the present invention is comprised of an internal gate cell group constituting a desired logic and an input/output circuit cell group having a buffer function, in which each input/output circuit cell of the input/output circuit cell group is It is assumed that each input/output cell is composed of a plurality of circuit units, and that there are a plurality of types of relative positional relationships between the circuit units that constitute each input/output cell.
第１図は本発明の一実施例を示すものである。 FIG. 1 shows an embodiment of the present invention.
付番は第３図に対応させている。第１図においては、チ
ップコーナ部に出力回路及び、静電保護部５を配列し、
こｎらに対凪する出力前段回路４と入力回路２とを左右
辺の入出力回路セルの内側に配置している。このような
チップレイアウトにすることによって、第３図に比して
、谷コーナ５本ずつ計２０本の信号音外部にとフ出せる
ことになシ、特に内部ゲートセル数の少ない小チップに
おいて信号ビン数が増加した場合にその効果が大きい０
次に第１図の半導体集積回路装置の設計方法について説
明する。入出力回路セルを構成する回路単位各々は、入
出力回路セル各々で同一形状をもち、コーナ一部の入出
力回路セルと辺中央部の入出力回路セルとは回路単位の
配置の仕方が異なるのみである。即ちコーナ部で辺中央
部と異なる形状の入出力回路セルを構成する必要がなく
、配置についてのみ考慮するだけでよいので、設計工数
の増大金招くこともなく設計の信頼度の点でも好ましい
。Numbering corresponds to Fig. 3. In FIG. 1, the output circuit and the electrostatic protection section 5 are arranged in the chip corner part,
A pre-output circuit 4 and an input circuit 2, which are compatible with each other, are arranged inside the input/output circuit cells on the left and right sides. By adopting such a chip layout, a total of 20 signal tones can be outputted from each of the five valley corners compared to the one shown in Fig. 3. Especially in small chips with a small number of internal gate cells, the signal bins can be The effect is greater when the number increases.Next, a method for designing the semiconductor integrated circuit device shown in FIG. 1 will be described. Each of the circuit units that make up the input/output circuit cell has the same shape, and the arrangement of the circuit units is different between the input/output circuit cell in the corner part and the input/output circuit cell in the center part of the side. Only. That is, there is no need to configure input/output circuit cells in the corner portions having a different shape from those in the center portions of the sides, and only the placement needs to be considered, which is preferable from the point of view of design reliability without incurring an increase in design man-hours.
また、回路単位各々は同一形状ｔもつため、回路単位各
々の電気的特性のバラツキも少なく、入出力回路セル全
体としての電気的特性のバラツキも小さい。Further, since each circuit unit has the same shape t, there is little variation in the electrical characteristics of each circuit unit, and there is also little variation in the electrical characteristics of the input/output circuit cell as a whole.
次に、コーナ部の入出力回路セルの各回路単位間の接続
に関しては、谷回路単位毎に、入出力端子位ｔ’を固定
し、回路単位間の接続は常にこの入出力端子位ｔｔｌ−
経て行なうこととし、ある程度の固定配線をコーナ部の
出力回路及び静電保護部と辺中央部の対応する出力前段
回路及び入力回路との間に設けることによって、辺甲央
の入出力回路セルと同様の配置接続関係を保つことがで
きる。Next, regarding the connection between each circuit unit of the input/output circuit cells in the corner part, the input/output terminal position t' is fixed for each valley circuit unit, and the connection between the circuit units is always at this input/output terminal position ttl-
By installing a certain amount of fixed wiring between the output circuit and electrostatic protection section at the corner and the corresponding pre-output circuit and input circuit at the center of the side, the input/output circuit cell at the center of the side will be connected. A similar arrangement and connection relationship can be maintained.
この様な固定配線を利用した設計方式は、特にマスタス
ライス方式集積回路装置の様に棟々の回路機能を入出力
回路セルにもたせる場合に、設計の信ｆ４度の上から重
要な意味をもつ
〔発明の効果〕
以上説明したように、本発明は、内部ゲートセル群と入
出力回路セル群から構成される半導体集積回路において
、入出力回路セル全構成する複数個の回路単位の配置を
、チップ辺中央部とコーナ部とイ変えることによって、
設計の信頼層を損うことなく、同様な面積をもつチップ
に比して多数の信号を外部にとシ出せるという効果′ｔ
−有する。A design method using fixed wiring like this has an important meaning from the standpoint of design reliability, especially when providing individual circuit functions to input/output circuit cells, such as in a master slice integrated circuit device. [Effects of the Invention] As explained above, in a semiconductor integrated circuit composed of an internal gate cell group and an input/output circuit cell group, the arrangement of a plurality of circuit units constituting all the input/output circuit cells can be arranged on a chip. By changing the center part of the side and the corner part,
The effect is that a larger number of signals can be transmitted to the outside compared to a chip with a similar area without compromising the reliability layer of the design.
- have.
第１図は本発明の一実施例を示すチップレイプラト図で
ある。第２図は、本発明の対象とする半導体集積回路装
置の回路構成を示すブロック図。
第３図は従来のチップレイプラト図である。
１・・・・・・パッド、２・・・・・・入力回路、３・
・・・・・内部回路、４・・・・・・出力前段回路、５
・・・・・・出力回路及び静電保護部、６・・・・・・
チッグコーナ部。
茅 １ ゴ
第 ２ 回FIG. 1 is a chip lay plate diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing the circuit configuration of a semiconductor integrated circuit device to which the present invention is applied. FIG. 3 is a diagram of a conventional chip lay plate. 1...Pad, 2...Input circuit, 3.
...Internal circuit, 4...Output pre-stage circuit, 5
...Output circuit and electrostatic protection section, 6...
Chig corner section. Kaya 1 Go 2nd
Claims (1)
ァ機能を有する入出力回路セル群とから構成される半導
体集積回路装置において、前記入出力回路セル群の各入
出力回路セルがそれぞれ複数の回路単位から構成され、
かつ各入出力セルを構成する前記複数の回路単位の相対
位置関係が複数種存在することを特徴とする半導体集積
回路装置。In a semiconductor integrated circuit device consisting of an internal gate cell group constituting a desired logic circuit and an input/output circuit cell group having a buffer function, each input/output circuit cell of the input/output circuit cell group has a plurality of circuit units. It consists of
A semiconductor integrated circuit device characterized in that there are a plurality of types of relative positional relationships between the plurality of circuit units constituting each input/output cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60255257A JPH06101521B2 (en) | 1985-11-13 | 1985-11-13 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60255257A JPH06101521B2 (en) | 1985-11-13 | 1985-11-13 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62114259A true JPS62114259A (en) | 1987-05-26 |
| JPH06101521B2 JPH06101521B2 (en) | 1994-12-12 |
Family
ID=17276229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60255257A Expired - Lifetime JPH06101521B2 (en) | 1985-11-13 | 1985-11-13 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06101521B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4992845A (en) * | 1988-12-02 | 1991-02-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device having input/output buffer cells each comprising a plurality of transistor regions arranged in a single line |
| US5016080A (en) * | 1988-10-07 | 1991-05-14 | Exar Corporation | Programmable die size continuous array |
| US5300796A (en) * | 1988-06-29 | 1994-04-05 | Hitachi, Ltd. | Semiconductor device having an internal cell array region and a peripheral region surrounding the internal cell array for providing input/output basic cells |
| US5473182A (en) * | 1992-07-01 | 1995-12-05 | Nec Corporation | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6095935A (en) * | 1983-10-31 | 1985-05-29 | Fujitsu Ltd | Gate array integrated circuit device |
-
1985
- 1985-11-13 JP JP60255257A patent/JPH06101521B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6095935A (en) * | 1983-10-31 | 1985-05-29 | Fujitsu Ltd | Gate array integrated circuit device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5300796A (en) * | 1988-06-29 | 1994-04-05 | Hitachi, Ltd. | Semiconductor device having an internal cell array region and a peripheral region surrounding the internal cell array for providing input/output basic cells |
| US5016080A (en) * | 1988-10-07 | 1991-05-14 | Exar Corporation | Programmable die size continuous array |
| US4992845A (en) * | 1988-12-02 | 1991-02-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device having input/output buffer cells each comprising a plurality of transistor regions arranged in a single line |
| US5473182A (en) * | 1992-07-01 | 1995-12-05 | Nec Corporation | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06101521B2 (en) | 1994-12-12 |
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