JPH0760855B2 - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPH0760855B2
JPH0760855B2 JP62224653A JP22465387A JPH0760855B2 JP H0760855 B2 JPH0760855 B2 JP H0760855B2 JP 62224653 A JP62224653 A JP 62224653A JP 22465387 A JP22465387 A JP 22465387A JP H0760855 B2 JPH0760855 B2 JP H0760855B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
input
output buffer
block
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62224653A
Other languages
Japanese (ja)
Other versions
JPS6466950A (en
Inventor
荘一 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62224653A priority Critical patent/JPH0760855B2/en
Publication of JPS6466950A publication Critical patent/JPS6466950A/en
Publication of JPH0760855B2 publication Critical patent/JPH0760855B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118Masterslice integrated circuits
    • H01L27/11898Input and output buffer/driver structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路装置に関し、特にスタンダードセル方
式による集積回路装置に関する。
The present invention relates to an integrated circuit device, and more particularly to a standard cell type integrated circuit device.

〔従来の技術〕[Conventional technology]

一般に、スタンダードセル方式のLSI設計に用いられる
入出力バッファブロックの大きさは、特に、出力バッフ
ァの駆動能力の大きさの違いにより、半導体チップの辺
に平行する方向の幅は一定でも辺に垂直な方向の奥行の
大きさが異なっている。一方、半導体チップの4辺への
入出力バッファブロックの配置は顧客からの実装状態の
要求により決り、これら大きさの違う入出力バッファブ
ロックの位置を半導体チップの4辺内で相互に調整する
ことは、通常、不可能である。
Generally, the size of the input / output buffer block used in standard cell LSI design is perpendicular to the side of the semiconductor chip even if the width in the direction parallel to the side of the semiconductor chip is constant due to the difference in the driving capacity of the output buffer. Depth sizes in different directions are different. On the other hand, the layout of the input / output buffer blocks on the four sides of the semiconductor chip is determined by the customer's mounting condition requirements, and the positions of these different size input / output buffer blocks should be mutually adjusted within the four sides of the semiconductor chip. Is usually impossible.

第2図は従来の集積回路装置の一例の平面図である。FIG. 2 is a plan view of an example of a conventional integrated circuit device.

第2図に示すように、半導体チップ1aの中央部領域に形
成された論理部ブロック2と、論理部ブロック2の周辺
の半導体チップ1a上に形成された同一機能で駆動能力の
異なる複数の入出力バッファブロック3,3a,3bと、外部
接続のための複数のボンディングパッド5とを含んで構
成される。
As shown in FIG. 2, the logic block 2 formed in the central region of the semiconductor chip 1a and a plurality of input chips having the same function and different driving capabilities formed on the semiconductor chip 1a around the logic block 2 are provided. The output buffer blocks 3, 3a, 3b and a plurality of bonding pads 5 for external connection are included.

入出力バッファブロック3,3a,3bは半導体チップ1aの辺
に平行な方向の幅は同一寸法であるが、辺に垂直な方向
の奥行の大きさが異なり入出力バッファブロック3,3a,3
bの順に大きくなっている。
The input / output buffer blocks 3, 3a, 3b have the same width in the direction parallel to the sides of the semiconductor chip 1a, but the depths in the direction perpendicular to the sides are different, and the input / output buffer blocks 3, 3a, 3b are different.
It becomes larger in the order of b.

このような入出力バッファブロック3,3a,3bを半導体チ
ップ1aの1つの辺に沿って複数個列状に設けた場合、論
理部ブロック2の領域と入出力バッファブロック列の領
域との間の境界は最も奥行の大きい入出力バッファブロ
ック3bで決り、それらの間に大きなデッドスペース4が
生じる。
When a plurality of such input / output buffer blocks 3, 3a, 3b are provided in a row along one side of the semiconductor chip 1a, the area between the logic block 2 and the area of the input / output buffer block row is The boundary is determined by the input / output buffer block 3b having the largest depth, and a large dead space 4 is generated between them.

デッドスペース4は自動設計の場合、特に論理部ブロッ
ク2を形成する内部領域の外周に任意の凹凸状態が生じ
ると、内部領域として有効に利用することが著しく困難
になり、又、処理速度が遅くなるために、そのまま放置
されてできたものである。
In the case of automatic design, the dead space 4 becomes extremely difficult to be effectively used as an internal area, especially when an arbitrary uneven state occurs on the outer periphery of the internal area forming the logic block 2, and the processing speed is slow. Therefore, it was made by leaving it alone.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上述した従来の集積回路装置は、駆動能力の異なる入出
力バッファブロックを任意配置するようになっているの
で、半導体チップのサイズが大きくなるという欠点があ
る。
In the above-mentioned conventional integrated circuit device, since the input / output buffer blocks having different driving capabilities are arbitrarily arranged, there is a drawback that the size of the semiconductor chip becomes large.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の集積回路装置は、半導体チップ上の中央部領域
に形成された論理部ブロックと、該論理部ブロックの外
周の前記半導体チップ上に前記半導体チップの各辺に沿
って配列され且つ前記辺に平行な方向の幅が同一で前記
辺に垂直な方向の奥行が駆動能力の大きさに比例して異
なる複数の入出力バッファブロックとを備える集積回路
装置において、前記入出力バッファブロックのうちの大
きい駆動能力を有する入出力バッファブロックが隣接す
る小さな駆動能力を有する入出力バッファブロックの背
後に向けてブロックの最後部を折り曲げたL字状の形状
を有する。
An integrated circuit device according to the present invention includes a logic block formed in a central region of a semiconductor chip, and a semiconductor chip on the outer periphery of the logic block, the logic block being arranged along each side of the semiconductor chip and In a plurality of input / output buffer blocks having the same width in the direction parallel to the direction and different in depth in the direction perpendicular to the side in proportion to the magnitude of the driving capability. An I / O buffer block having a large driving capacity has an L-shaped shape in which the last part of the block is bent toward the back of an adjacent input / output buffer block having a small driving capacity.

〔実施例〕 第1図は本発明の一実施例を示す半導体チップの平面図
である。
[Embodiment] FIG. 1 is a plan view of a semiconductor chip showing an embodiment of the present invention.

第1図に示すように、半導体チップ1の中央部領域に論
理部2aが形成され、論理部ブロック2aの外周に半導体チ
ップ1の辺に沿って複数の入出力バッファブロック3,3
a,6,7が配列される。ここで、これらの入出力バッファ
ブロック3,3a,6,7は半導体チップ1の辺に平行な方向の
幅が同一で、且つ、辺に垂直な方向の奥行が駆動能力の
大きさに比例して小さい方から3,3a,6(又は7)の順に
大きくなっており、駆動能力の大きい入出力バッファブ
ロック6,7は隣接するそれよりも小さい駆動能力の入出
力バッファブロック3又は3aの背後に向けてブロックの
最後部を折り曲げたL字状の形状を有しており、入出力
バッファブロック6,7の奥行を小さくすることができ
る。また、これらの入出力バッファブロックの配列の外
周にボンディングパッド5が配列されている。
As shown in FIG. 1, a logic part 2a is formed in a central region of the semiconductor chip 1, and a plurality of input / output buffer blocks 3, 3 are formed along the sides of the semiconductor chip 1 on the outer periphery of the logic part block 2a.
a, 6,7 are arranged. Here, these input / output buffer blocks 3, 3a, 6, 7 have the same width in the direction parallel to the side of the semiconductor chip 1, and the depth in the direction perpendicular to the side is proportional to the magnitude of the driving capability. The I / O buffer blocks 6 and 7 having a larger driving capacity are arranged in the order of 3, 3a, 6 (or 7) from the smaller one, and the I / O buffer blocks 6 and 7 having a smaller driving capacity are located behind the I / O buffer blocks 3 or 3a having a smaller driving capacity. It has an L-shaped shape in which the rearmost portion of the block is bent toward, and the depth of the input / output buffer blocks 6 and 7 can be reduced. Further, bonding pads 5 are arranged on the outer periphery of the arrangement of these input / output buffer blocks.

従って、内部の論理部ブロック2aは、第1図に破線で示
す第2図の従来の論理部ブロック2に比べて拡大が可能
になり、デッドスペース4aが削減されて集積度が向上す
る。換言すれば、同一のLSI規模のものに対しては半導
体チップのサイズを小さくできる。
Therefore, the internal logic block 2a can be expanded as compared with the conventional logic block 2 of FIG. 2 shown by the broken line in FIG. 1, the dead space 4a is reduced, and the degree of integration is improved. In other words, the size of the semiconductor chip can be reduced for the same LSI scale.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、最大の駆動能力を有する
入出力バッファブロックの形状をL字状とすることによ
り、半導体チップの一辺に沿って形成される入出力バッ
ファブロック列の奥行を小さくできるので、集積度を向
上できるという効果がある。
As described above, according to the present invention, the depth of the input / output buffer block row formed along one side of the semiconductor chip can be reduced by making the shape of the input / output buffer block having the maximum driving capability L-shaped. Therefore, there is an effect that the degree of integration can be improved.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の第1の実施例を示す平面図、第2図は
従来の集積回路装置の一例を示す平面図である。 1,1a……半導体チップ、2,2a……論理ブロック、3,3a,3
b……入出力バッファブロック、4,4a……デッドスペー
ス、5……ボンディングパッド、6,7……入出力バッフ
ァブロック。8……並列接続された入出力バッファブロ
ック。
FIG. 1 is a plan view showing a first embodiment of the present invention, and FIG. 2 is a plan view showing an example of a conventional integrated circuit device. 1,1a …… Semiconductor chip, 2,2a …… Logic block, 3,3a, 3
b ... I / O buffer block, 4, 4a ... Dead space, 5 ... Bonding pad, 6, 7 ... I / O buffer block. 8 ... Input / output buffer blocks connected in parallel.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体チップ上の中央部領域に形成された
論理部ブロックと、該論理部ブロックの外周の前記半導
体チップ上に前記半導体チップの各辺に沿って配列され
且つ前記辺に平行な方向の幅が同一で前記辺に垂直な方
向の奥行が駆動能力の大きさに比例して異なる複数の入
出力バッファブロックとを備える集積回路装置におい
て、前記入出力バッファブロックのうちの大きい駆動能
力を有する入出力バッファブロックが隣接する小さい駆
動能力を有する入出力バッファブロックの背後に向けて
ブロックの最後部を折り曲げたL字状の形状を有するこ
とを特徴とする集積回路装置。
1. A logic unit block formed in a central region on a semiconductor chip, and arranged on the semiconductor chip on the outer periphery of the logic unit block along each side of the semiconductor chip and parallel to the side. In an integrated circuit device having a plurality of input / output buffer blocks having the same width in the same direction and different depths in the direction perpendicular to the sides in proportion to the magnitude of the driving capability, the large driving capability of the input / output buffer blocks The I / O buffer block having the above-mentioned structure has an L-shape in which the last part of the block is bent toward the back of the adjacent I / O buffer block having a small driving capacity.
JP62224653A 1987-09-07 1987-09-07 Integrated circuit device Expired - Lifetime JPH0760855B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62224653A JPH0760855B2 (en) 1987-09-07 1987-09-07 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62224653A JPH0760855B2 (en) 1987-09-07 1987-09-07 Integrated circuit device

Publications (2)

Publication Number Publication Date
JPS6466950A JPS6466950A (en) 1989-03-13
JPH0760855B2 true JPH0760855B2 (en) 1995-06-28

Family

ID=16817095

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62224653A Expired - Lifetime JPH0760855B2 (en) 1987-09-07 1987-09-07 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0760855B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2700273B1 (en) * 1993-01-12 1995-03-31 Salomon Sa Method of decorating a ski top.
US5691218A (en) * 1993-07-01 1997-11-25 Lsi Logic Corporation Method of fabricating a programmable polysilicon gate array base cell structure
US5552333A (en) * 1994-09-16 1996-09-03 Lsi Logic Corporation Method for designing low profile variable width input/output cells
TW360962B (en) * 1998-02-16 1999-06-11 Faraday Tech Corp Chip with hybrid input/output slot structure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57139954A (en) * 1981-02-24 1982-08-30 Nec Corp Master-sliced large scale integrated circuit
JPS62154640A (en) * 1985-12-26 1987-07-09 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPS6466950A (en) 1989-03-13

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