JPH06204395A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase circuit speed of the entire system of a semiconductor device, reduce power consumption, miniaturize the system, increase density, improve ease of manufacture, and reduce manufacturing cost. CONSTITUTION:In a semiconductor device where a plurality of LSI chips 14 are mounted on a substrate 12, the LSI chips 14 are laid out via a spacing 16 in vertical direction and a spacing 18 in horizontal direction, a fixed wiring LSI chip 20 which is not affected by a custom part is laid out at the spacing, a wiring customizing LSI chip 22 corresponding to customization is laid out at the cross part of the vertical and horizontal spacings 16 and 18, and the LSI chips 14 are connected via these.

Description

Detailed Description of the Invention

[0001]

This invention relates to a plurality of LSIs on a substrate.
The present invention relates to a semiconductor device mounted with a chip.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 10, a plurality of LSI chips 1 called a multi-chip module are mounted on a silicon substrate 2, and the silicon substrate 2 is further mounted on a ceramic substrate 3. There is a semiconductor device.

In this semiconductor device, the plurality of LS
The I chip is wire-bonded to an aluminum wiring pattern (not shown) formed on the silicon substrate 2, and the aluminum wiring pattern is wire-bonded to the outside.

[0004]

In the above conventional semiconductor device, since the thick aluminum wiring is laid on the silicon substrate 2, the resistance capacitance between the LSI chips 1 becomes large,
As a result, there are problems that power consumption increases, processing speed decreases, and cost increases. Further, these have hindered the increase in density and super-scale of semiconductor devices.

The present invention has been made in view of the above-mentioned problems of the prior art. The aluminum wiring is not extended between the LSI chips for a long time, and the wiring is almost directly connected to increase the processing speed. It is an object of the present invention to provide a semiconductor device capable of reducing the power consumption, downsizing the device, and increasing the circuit density and the ultra-large scale.

[0006]

SUMMARY OF THE INVENTION According to the present invention, in a semiconductor device in which a plurality of LSI chips are mounted on a substrate and each LSI chip is connected to each other, a common wiring LSI chip and a wiring LSI chip are provided between the LSI chips. The above object is achieved by a semiconductor device characterized in that a customized LSI chip is arranged adjacent to each other, and the LSI chips are connected via these.

Further, the plurality of LSI chips are arranged with a space in the vertical and horizontal directions, the common wiring LSI chip is arranged in a space between adjacent LSI chips, and the wiring customized LSI chip is arranged in the vertical and horizontal directions. They may be arranged at the intersections of the gaps.

Further, the common wiring LSI chip and the wiring customizing chip may be arranged in the same gap between adjacent LSIs.

Further, the LSI chip, common wiring LSI
The chip and the wiring customizing chip may be arranged so as to be substantially in contact with each other so that the wiring end portions are close to each other, and may be connected between the respective wiring end portions.

[0010]

According to the present invention, a common wiring LSI in which a plurality of LSI chips on a substrate are arranged adjacent to each other
Since the wiring is connected via the chip and the wiring customized LSI chip, it is possible to quickly connect the wiring without arranging the aluminum wiring, with a small resistance capacity, and at low cost.

Therefore, the processing speed can be increased, the power consumption can be reduced, and the apparatus can be downsized, and the circuit can be easily densified and super-scaled.

According to the second aspect, the common portion is connected via the common wiring LSI chip, the custom-made portion is connected via the wiring customized LSI chip, and the common wiring LSI chip is adjacent to the LSI chip. In the gap between
Since the wiring customized LSI chips are arranged at the intersections of the vertical and horizontal gaps respectively, the combination of the common portion and the custom-made portion can be achieved at the lowest cost.

According to the third aspect, even when the number of LSI chips is small, the common part and the custom-made part can be optimally combined.

According to the fourth aspect, the connection distance for wire bonding or the like can be minimized.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, a semiconductor device 10 according to this embodiment has six LSI chips 1 on a substrate 12.
4 are arranged in a checkerboard pattern with a vertical gap 16 and a horizontal gap 18 therebetween, and the vertical gaps 16 and the horizontal gaps 18 between the respective LSI chips 14 are arranged so as to almost contact the adjacent LSI chips 14. Fixed wiring LSI chips 20 are arranged (to fill the gap), and wiring customized LSI chips 22 are arranged at the intersections of the vertical gaps 16 and the horizontal gaps 18, respectively. Chip and wiring Customized LSI chip 22
The six LSI chips 14 are connected to each other via the.

Here, the fixed wiring LSI chip 20 is used.
Defines a common part of the semiconductor device 10 excluding a custom-ordered part, and the wiring customized LSI chip 2
2 changes the semiconductor device 10 by changing this part.
Corresponds to the custom-made part where the whole is customized LSI.

The bonding pads 14A, 20A and 22A of the LSI chip 14, the fixed wiring LSI chip 20 and the wiring customized LSI chip 22 are arranged so that the connected portions are adjacent and facing each other, as shown in an enlarged view in FIG. It is located in.

The bonding pads 14A, 20A,
22A mutual connection, as shown in an enlarged view in FIG.
A wiring layer 24 such as an aluminum vapor deposition layer is formed so as to straddle the end faces of adjacent LSI chips, or wiring is performed by wire bonding, soldering, or the like. A fixed mask is used to form the aluminum vapor deposition layer.

Even if there is a gap between the LSI chip 14, the fixed wiring LSI chip 20, and the wiring customized LSI chip 22, as shown in FIG.
Since the opposite corners of these LSI chips are melted to fill the gap, the wiring layer 24 can reliably connect the adjacent LSI chips.

Reference numeral 26 in FIG. 1 denotes a pin which is exposed from the substrate 12, and the corresponding bonding pad 14B of the LSI chip 14 is wire-bonded to the pin 26. Here, the LSI chip 14 is connected to the fixed wiring L
Bonding pad 1 for connecting to SI chip 20
4A is provided via a small I / O buffer 28, as shown in FIG.
Bonding pad 14B connected to is large I / O
It is arranged via the buffer 30.

In this embodiment, the LSI chip 14
Fixed wiring LSI chip 20 and wiring customization L
Since the connection is made through the SI chip 22, the circuit speed of the entire semiconductor device 10 can be increased, the power consumption can be reduced, the system can be downsized, and the density can be increased.

Also, the connection except the custom-made part is fixed wiring LS.
Fixed chip LSI with I chip 20 and changes
Wiring customized LSI for changing the connection between chips 20
Since the wires are connected via the chip 22, it is easy to manufacture an ultra-large-scale circuit and the manufacturing cost can be reduced.

The above embodiment relates to the semiconductor device 10 having six LSI chips 14 mounted thereon, but the present invention is not limited to this, and any device having two or more LSI chips mounted thereon can be used. Good.

Therefore, for example, as shown in FIG.
The semiconductor device 10A may be provided with one LSI chip 14 or may be the semiconductor device 10B provided with two LSI chips 14 as shown in FIG.

In the semiconductor device 10B of FIG. 7, a fixed wiring LSI chip 20 and a wiring customized LSI chip 22 are arranged between two LSI chips 14.

In this case, the wiring customized LSI chip 22 may be directly connected to the LSI chip 14 unlike the case of the embodiment shown in FIG.

Further, as shown in FIG. 8, LSI chips 15 of different sizes may be combined.

In this case, the small LSI chip 15 and the LS
A fixed wiring LSI chip 21 having a variable size may be arranged in a large area between the I chip 14 and the I chip 14.

Further, as in the semiconductor device 10D shown in FIG. 9, a field programmable gate array (FP
Instead of the LSI chip and the wiring customization chip, the GA) 32 may be arranged alternately with the fixed wiring LSI chip 34.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is an enlarged plan view showing an arrangement state of bonding pads before connection in the apparatus of the embodiment.

FIG. 3 is a plan view similar to FIG. 2 showing a state after connection of the embodiment.

FIG. 4 is an enlarged sectional view showing a wiring layer portion of the embodiment.

FIG. 5 is an enlarged plan view showing an arrangement state of I / O buffers of the embodiment.

FIG. 6 is a plan view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a plan view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a plan view showing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 9 is a plan view showing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 10 is a side view showing a conventional multi-chip module.

[Explanation of symbols]

 10, 10A, 10B, 10C, 10D ... Semiconductor device 12 ... Substrate 14, 15 ... LSI chip 16 ... Vertical gap 18 ... Horizontal gap 20, 21 ... Fixed wiring LSI chip 22 ... Wiring customized LSI chip 24 ... Wiring layer 32 … FPGA

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 27/04 D 8427-4M

Claims (4)

[Claims] 1. A semiconductor device in which a plurality of LSI chips are mounted on a substrate and the respective LSI chips are connected to each other.
A semiconductor device characterized in that a common wiring LSI chip and a wiring customized LSI chip are arranged adjacent to each other between I chips, and the respective LSI chips are connected via these. 2. The plurality of LSI chips are arranged with a gap in the vertical and horizontal directions, and the common wiring LSI chip is placed in a gap between adjacent LSI chips.
In addition, the wiring customized LSI chip is arranged at an intersection of vertical and horizontal gaps, respectively. 3. The common wiring LSI according to claim 1.
Chip and wiring customized chip are adjacent LSI
A semiconductor device, wherein the semiconductor device is arranged in the same gap between the two. 4. The LSI according to claim 1, 2 or 3.
A semiconductor device characterized in that a chip, a common wiring LSI chip, and a wiring customizing chip are arranged so as to be in contact with each other so that their wiring end portions are close to each other, and are connected between the respective wiring end portions.