JPH06204394A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase circuit speed, reduce power consumption, miniaturize a system, and increase density by directly connecting adjacent LSI chips in a semiconductor device using a plurality of LSI chips. CONSTITUTION:An LSI chip 15 for wiring is adjacent between LSI chips 14 and 16 in a semiconductor device 10 while they are in contact or there is slight space among them and then they ate connected by a wiring layer 18 consisting of aluminum deposition layer, etc.

Description

Detailed Description of the Invention

[0001]

This invention relates to a plurality of LSIs on a substrate.
The present invention relates to a semiconductor device mounted with a chip.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 8, a plurality of LSI chips 1 called a multi-chip module are mounted on a silicon substrate 2, and the silicon substrate 2 is further mounted on a ceramic substrate 3. There is a semiconductor device.

In this semiconductor device, the plurality of LS
The I-chip 1 is wire-bonded to an aluminum wiring pattern (not shown) formed on the silicon substrate 2, and the aluminum wiring pattern is wire-bonded to the outside.

[0004]

In the conventional semiconductor device described above, since the thick aluminum wiring is laid long on the silicon substrate 2, the resistance capacitance between the LSI chips 1 becomes large, resulting in an increase in power consumption. There are problems that the processing speed is lowered and the cost is increased.

The present invention has been made in view of the above-mentioned problems of the prior art. The LSI chips are connected in a substantially direct connection state to simplify manufacturing, improve the circuit speed, and reduce the power consumption. It is an object of the present invention to provide a semiconductor device capable of reducing the package size.

[0006]

According to the present invention, in a semiconductor device in which a plurality of LSI chips are mounted on a substrate and each LSI chip is connected to each other, wiring LSI chips are almost contacted between adjacent LSI chips. The above object is achieved by a semiconductor device characterized in that the wiring ends of the adjacent LSI chips are connected to the wiring LSI chip.

Further, between the adjacent LSI chips, an I / O buffer having a capacity smaller than that of an I / O buffer for external connection is used.
You may make it connect using an / O buffer.

[0008]

In the present invention, adjacent LSIs are
Since the chips are connected to each other in a direct connection state with the shortest distance, the manufacturing is simple, the circuit speed can be improved, the power consumption can be reduced, and the package can be downsized.

According to the second aspect, since the I / O buffer having a small capacity can be used for the connection between the respective LSI chips, it is possible to further reduce the power consumption and the manufacturing cost.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, a semiconductor device 10 according to this embodiment has two LSI chips 1 on a substrate 12.
4 and 16 are mounted on both LSI chips 14,
The bonding pads 16 are arranged so that the bonding pads to be connected to each other face each other, and are connected via the wiring LSI chip 15 arranged between them.

As shown in FIG. 2, these bonding pads 14A and 16A are arranged close to the bonding pad 15A of the adjacent wiring LSI chip 15, and as shown in FIG. They are connected by a wiring layer 18 formed by vapor deposition.

Here, even if there is a small gap between the LSI chips 14 and 16 and the wiring LSI chip 15, as shown in FIG. Since the opposite corners melt and fill the gap,
The wiring layer 18 can reliably connect the both LSI chips 14 and 16 and the wiring LSI chip 15.

Reference numeral 20 in FIG. 1 denotes a pin which is exposed from the substrate 12 to the outside. The corresponding bonding pads 14B and 16B of the LSI chips 14 and 16 are wire-bonded to the pins 20.

Here, the bonding pads for connecting to the wiring LSI chip 15 in the LSI chips 14 and 16 are provided via a small I / O buffer 22 as shown in FIG. On the other hand, the bonding pads 14B and 16B connected to the pin 20.
Are arranged via a large I / O buffer 24.

In this embodiment, since the adjacent LSI chips 14 and 16 are connected by the wiring layer 18 made of the aluminum vapor deposition layer, the wiring capacitance becomes very small.

The bonding pad connected by the wiring layer 18 may have a smaller capacity than the I / O buffer 24 connected to the pin 20.

Therefore, it is possible to improve the circuit speed, reduce the power consumption, and reduce the size of the package.

Further, since the connection between the adjacent LSI chips 14 and 16 can be made by aluminum vapor deposition or the like, the manufacturing is simplified.

In the above embodiment, two LSI chips 14,
Regarding the semiconductor device 10 including 16
The present invention is not limited to this, and a large number of LS
It is naturally applied to a semiconductor device using an I chip.

For example, as shown in FIG.
It can be naturally applied to the semiconductor device 28 using the individual LSI chips 26. In the case of this embodiment, each of the left and right is 3
A wiring LSI chip 27 is arranged vertically between the individual LSI chips 26. The wiring layers 18 also directly connect between the LSI chips 26 adjacent in the vertical direction.

Further, as in the semiconductor device 28A of the third embodiment shown in FIG. 6B, wiring LSI chips 27 may be arranged vertically and horizontally between the six LSI chips 26.

In the above embodiment, the bonding pads of the adjacent LSI chips are connected to each other, but the present invention is not limited to this. For example, as in the fourth embodiment shown in FIG. Wiring 32A, 34A between the LSI chip 32 and the wiring LSI chip 34 with the pads omitted
Are extended to the opposite end face, and the wiring layer 18 is formed near the end face.
You may connect by.

In the above embodiment, the adjacent LSs are
The wiring layer 18 for connecting the I-chip is composed of a vapor-deposited layer of aluminum, but the present invention is not limited to this, and if necessary, a film-like wiring that can be directly formed on the LSI chip. It may be a layer, or other connecting means such as wire bonding or solder may be used.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is an enlarged plan view showing a positional relationship of bonding pads in the apparatus of the embodiment.

FIG. 3 is an enlarged plan view showing a state in which bonding pads of the embodiment are connected by a wiring layer.

FIG. 4 is an enlarged sectional view showing a wiring layer portion of the embodiment.

FIG. 5 is an enlarged plan view showing an arrangement state of I / O buffers of the embodiment.

FIG. 6 is a plan view showing a semiconductor device according to second and third embodiments of the present invention.

FIG. 7 is an enlarged plan view showing an essential part of a semiconductor device according to a fourth embodiment of the invention.

FIG. 8 is a side view showing a conventional multi-chip module.

[Explanation of symbols]

 10, 28, 30 ... Semiconductor device 12 ... Substrate 14, 16, 26, 32 ... LSI chip 14A, 16A ... Bonding pad 15, 27, 34 ... Wiring LSI chip 18 ... Wiring layer 22, 24 ... I / O buffer

Claims (2)

[Claims] 1. In a semiconductor device in which a plurality of LSI chips are mounted on a substrate and the respective LSI chips are connected to each other, wiring LSI chips are arranged in contact with each other between adjacent LSI chips, and the adjacent LSI chips are arranged. A semiconductor device in which a wiring end portion of an LSI chip is connected to the wiring LSI chip. 2. The semiconductor device according to claim 1, wherein the adjacent LSI chips are connected by using an I / O buffer having a capacity smaller than that of an I / O buffer for external connection. .