KR20010018945A - Semiconductor package - Google Patents
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- KR20010018945A KR20010018945A KR1019990035108A KR19990035108A KR20010018945A KR 20010018945 A KR20010018945 A KR 20010018945A KR 1019990035108 A KR1019990035108 A KR 1019990035108A KR 19990035108 A KR19990035108 A KR 19990035108A KR 20010018945 A KR20010018945 A KR 20010018945A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
본 발명은 반도체패키지에 관한 것으로, 더욱 상세하게 설명하면 두께를 얇게 유지하면서도 다수의 반도체칩을 적층하여 초박형인 동시에 적층형의 반도체패키지를 제공하고, 또한 와이어 스위핑(sweeping) 현상도 제거할 수 있는 반도체패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package. More specifically, the present invention relates to a semiconductor package in which a plurality of semiconductor chips are stacked while maintaining a thin thickness, thereby providing a semiconductor package of ultra thin and stacked type, and also capable of eliminating wire sweeping. It's about packages.
최근의 반도체패키지는 칩스케일(chip scale) 반도체패키지, 마이크로 볼그리드어레이(micro ball grid array) 반도체패키지 및 초박형(ultra thin) 반도체패키지 등과 같이 점차 소형화 및 박형화 추세에 있다. 또한 다수의 반도체칩을 적층함으로써 다기능의 반도체칩을 하나의 반도체패키지에 구현할 수 있는 적층형 반도체패키지도 개발되고 있으며, 이것의 구조는 도3a 및 도3b에 도시된 바와 같다. 여기서 도3a는 단면도이고 도3b는 봉지부가 형성되지 않았을 때의 평면도이다.Recently, semiconductor packages are gradually becoming smaller and thinner, such as chip scale semiconductor packages, micro ball grid array semiconductor packages, and ultra thin semiconductor packages. In addition, a stacked semiconductor package that can implement a multifunctional semiconductor chip in one semiconductor package by stacking a plurality of semiconductor chips has also been developed, and its structure is as shown in FIGS. 3A and 3B. 3A is a cross-sectional view and FIG. 3B is a plan view when no encapsulation portion is formed.
상기한 적층형 반도체패키지는 수지층(21)을 중심으로 그 상,하면에는 회로패턴(23)이 형성된 회로기판(20)이 구비되고, 상기 회로기판(20)의 상면 중앙에는 제1반도체칩(2a)이 접착제(10)로 접착되어 있다. 도면중 미설명 부호 24는 상,하면에 위치된 회로패턴(23)을 연결하는 도전성 비아홀이고, 25는 회로패턴(23)을 외부환경으로부터 보호하기 위한 커버코트이다.The multilayer semiconductor package includes a circuit board 20 having circuit patterns 23 formed on and under the resin layer 21, and a first semiconductor chip () formed at the center of the upper surface of the circuit board 20. 2a) is bonded with the adhesive agent 10. In the figure, reference numeral 24 denotes a conductive via hole connecting the circuit patterns 23 positioned on the upper and lower surfaces, and 25 denotes a cover coat for protecting the circuit pattern 23 from the external environment.
또한 상기 제1반도체칩(2a)의 상면에는 역시 접착제(10)로 제2반도체칩(2b)이 접착되어 있으며, 상기 제1반도체칩(2a)과 제2반도체칩(2b)의 입출력패드(4)는 서로 간섭하지 않토록 다른 방향을 향하여 형성되어 있다. 즉, 도4b에 도시된 바와 같이 제1반도체칩(2a)의 입출력패드(4)가 상,하부를 향하고 있다면, 제2반도체칩(2b)의 입출력패드(4)는 좌,우를 향하도록 함으로써 상호 간섭하지 않도록 되어 있다. 상기 제1반도체칩(2a) 및 제2반도체칩(2b)의 입출력패드(4)는 각각 회로기판(20)의 회로패턴(23)에 도전성와이어와 같은 접속수단(30)으로 접속되어 있고, 상기 회로기판(20)의 하면에 형성된 회로패턴(23)에는 다수의 도전성볼(50)이 융착되어, 차후 메인보드로 반도체칩을 신호를 전달할 수 있도록 되어 있다. 한편, 상기 제1반도체칩(2a) 및 제2반도체칩(2b), 접속수단(30)은 봉지재로 봉지된 봉지부(40)에 의해 외부환경으로부터 보호되도록 되어 있다.In addition, the second semiconductor chip 2b is also bonded to the upper surface of the first semiconductor chip 2a by an adhesive 10, and the input / output pads of the first semiconductor chip 2a and the second semiconductor chip 2b ( 4) are formed in different directions so as not to interfere with each other. That is, as shown in FIG. 4B, if the input / output pad 4 of the first semiconductor chip 2a faces up and down, the input / output pad 4 of the second semiconductor chip 2b faces left and right. This prevents mutual interference. The input / output pads 4 of the first semiconductor chip 2a and the second semiconductor chip 2b are connected to the circuit pattern 23 of the circuit board 20 by connecting means 30 such as conductive wires, respectively. A plurality of conductive balls 50 are fused to the circuit pattern 23 formed on the lower surface of the circuit board 20 so that the semiconductor chip can be transmitted to the main board later. On the other hand, the first semiconductor chip 2a, the second semiconductor chip 2b, and the connecting means 30 are protected from the external environment by the encapsulation portion 40 encapsulated with the encapsulant.
그러나 종래의 이러한 적층형 반도체패키지는 회로기판상에 제1반도체칩이 접착되고, 또한 그 제1반도체칩 상면에 제2반도체칩이 접착됨으로써 반도체패키지의 두께를 과도하게 증가시키는 문제가 있다. 이러한 문제는 결국 상기 반도체패키지를 사용하는 장치나 장비의 두께를 두껍게 하는 요인이 된다.However, such a conventional stacked semiconductor package has a problem that the thickness of the semiconductor package is excessively increased by adhering the first semiconductor chip to the circuit board and adhering the second semiconductor chip to the upper surface of the first semiconductor chip. This problem eventually becomes a factor of increasing the thickness of the device or equipment using the semiconductor package.
또한 제2반도체칩의 입출력패드와 회로기판 사이의 높이차가 큼으로써 제2반도체칩과 회로패턴을 연결하는 접속수단의 만곡높이(loop height)가 높아지는 경향이 있고, 또한 만곡높이가 큼으로써 접속수단의 스위핑 발생 가능성이 커져 그만큼 반도체패키지의 제조 공정중 불량확률이 높아지는 단점이 있다.In addition, the height difference between the input and output pads of the second semiconductor chip and the circuit board tends to be high, so that the loop height of the connecting means for connecting the second semiconductor chip and the circuit pattern tends to be high, and the connection height is also high, so that the connection means The possibility of sweeping increases, which increases the probability of defects during the manufacturing process of semiconductor packages.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 발명한 것으로, 두께를 얇게 유지하면서도 다수의 반도체칩을 적층할 수 있는 반도체패키지를 제공하고 또한 와이어 스위핑 현상도 제거할 수 있는 반도체패키지를 제공하는데 있다.Therefore, the present invention has been invented to solve the above conventional problems, and provides a semiconductor package that can be stacked a plurality of semiconductor chips while maintaining a thin thickness, and also provides a semiconductor package that can eliminate the wire sweeping phenomenon. It is.
도1a 내지 도1c는 본 발명의 제1실시예에 의한 반도체패키지를 도시한 단면도이다.1A to 1C are cross-sectional views showing a semiconductor package according to a first embodiment of the present invention.
도2a 내지 도2c는 본 발명의 제2실시예에 의한 반도체패키지를 도시한 단면도이다.2A through 2C are cross-sectional views illustrating a semiconductor package according to a second embodiment of the present invention.
도3a 및 도3b는 종래의 적층형 반도체패키지를 도시한 단면도 및 봉지부가 형성되지 않은 상태의 평면도이다.3A and 3B are sectional views showing a conventional stacked semiconductor package and a plan view of a state in which an encapsulation portion is not formed.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
2a,2b; 제1반도체칩, 제2반도체칩 4; 입출력패드2a, 2b; A first semiconductor chip and a second semiconductor chip 4; I / O pad
10; 접착제 20; 회로기판10; Adhesive 20; Circuit board
21; 수지층 22; 관통공21; Resin layer 22; Through hole
23; 회로패턴 24; 비아홀(via hole)23; Circuit pattern 24; Via hole
25; 커버코트(cover coat) 30; 접속수단25; Cover coat 30; Connection
40; 봉지부 50; 도전성볼40; Encapsulation 50; Conductive ball
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 일면에 다수의 입출력패드가 형성된 제1반도체칩과; 상기 제1반도체칩의 입출력패드가 형성된 면에 접착제로 접착된 제2반도체칩과; 상기 제1반도체칩 및 제2반도체칩이 수용될 수 있는 크기로 관통공이 형성된 수지층을 중심으로 표면에는 회로패턴이 형성되고, 상기 회로패턴은 커버코트로 코팅된 회로기판과; 상기 회로기판의 회로패턴과 제1반도체칩 및 제2반도체칩의 입출력패드 사이를 전기적으로 연결시키는 전기적 접속수단과; 상기 제1반도체칩, 제2반도체칩 및 접속수단을 외부환경으로부터 보호하도록 봉지재로 봉지하여 형성된 봉지부와; 상기 회로기판의 회로패턴에 융착된 다수의 도전성볼을 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention comprises: a first semiconductor chip having a plurality of input / output pads formed on one surface thereof; A second semiconductor chip bonded with an adhesive to a surface on which the input / output pad of the first semiconductor chip is formed; A circuit pattern is formed on a surface of the resin layer having a through hole formed in a size to accommodate the first semiconductor chip and the second semiconductor chip, and the circuit pattern is coated with a cover coat; Electrical connection means for electrically connecting the circuit pattern of the circuit board and the input / output pads of the first semiconductor chip and the second semiconductor chip; An encapsulation portion formed by encapsulating the first semiconductor chip, the second semiconductor chip, and the connecting means with an encapsulant so as to protect it from an external environment; It characterized in that it comprises a plurality of conductive balls fused to the circuit pattern of the circuit board.
여기서, 상기 제1반도체칩 또는 제2반도체칩 중 어느 하나는 평면상 직사각형인 것을 구비함이 바람직하다.Here, it is preferable that any one of the first semiconductor chip or the second semiconductor chip is provided with a planar rectangle.
또한, 상기 제1반도체칩과 제2반도체칩에 형성된 입출력패드는 단면 또는 평면상에서 서로 다른 위치에 형성함이 바람직하다.In addition, the input / output pads formed on the first semiconductor chip and the second semiconductor chip may be formed at different positions on a cross section or a plane.
더불어, 상기 제1반도체칩은 제2반도체칩이 접착된 면의 반대면이 봉지부 외부로 노출되도록 함이 바람직하다.In addition, the first semiconductor chip is preferably such that the opposite side of the surface on which the second semiconductor chip is bonded is exposed to the outside of the encapsulation portion.
또한, 상기 제1반도체칩 및 제2반도체칩의 입출력패드는 도전성볼의 형성 방향과 동일 방향으로 위치시키거나 또는 상기 제1반도체칩 및 제2반도체칩의 입출력패드는 도전성볼의 형성 방향과 반대 방향으로 위치시킬 수 있다.In addition, the input / output pads of the first semiconductor chip and the second semiconductor chip may be positioned in the same direction as the conductive ball formation direction, or the input / output pads of the first semiconductor chip and the second semiconductor chip may be opposite to the conductive ball formation direction. Can be positioned in a direction.
상기와 같이 입출력패드와 도전성볼의 형성 방향이 반대 방향을 향하고 있는 경우에, 상기 회로기판은 수지층의 상,하면에 회로패턴을 형성하고, 상,하의 회로패턴은 도전성 비아홀로 상호 접속함이 바람직하다.When the input and output pads and the conductive balls are formed in opposite directions as described above, the circuit board forms circuit patterns on the upper and lower surfaces of the resin layer, and the upper and lower circuit patterns are interconnected by conductive via holes. desirable.
상기와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 회로기판에 관통공이 형성되고, 상기 관통공에 제1반도체칩 및 제2반도체칩이 적층됨으로써, 상기 관통공이 제1반도체칩의 두께를 상쇄시켜 다수의 반도체칩이 적층됨에도 불구하고 반도체패키지의 두께를 얇게 유지할 수 있는 장점이 있다.According to the semiconductor package according to the present invention as described above, through holes are formed in the circuit board, and the first semiconductor chip and the second semiconductor chip are stacked in the through holes, so that the through holes cancel the thickness of the first semiconductor chip. Although a plurality of semiconductor chips are stacked, there is an advantage that the thickness of the semiconductor package can be kept thin.
또한, 상기와 같이 다수의 반도체칩이 적층된 구조를 함으로써 다기능을 갖는 다수의 반도체칩을 하나의 반도체패키지에 구비할 수 있게 된다.In addition, as described above, by stacking a plurality of semiconductor chips, a plurality of semiconductor chips having multifunctions may be provided in a single semiconductor package.
또한, 상기 제2반도체칩의 입출력패드와 회로기판 사이의 높이차가 종래 제1반도체칩과 회로기판 사이의 높이차와 같음으로써 접속수단의 만곡높이가 크지 않고, 따라서 접속수단의 스위핑 발생 가능을 낮출 수 있는 장점이 있다.Further, since the height difference between the input / output pad and the circuit board of the second semiconductor chip is the same as the height difference between the first semiconductor chip and the circuit board, the curvature height of the connecting means is not large, thus reducing the possibility of sweeping of the connecting means. There are advantages to it.
이하 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art may easily implement the present invention.
도1a 내지 도1c는 본 발명의 제1실시예에 의한 반도체패키지를 도시한 단면도이다.1A to 1C are cross-sectional views showing a semiconductor package according to a first embodiment of the present invention.
일면에 다수의 입출력패드(도시되지 않음)가 하면을 향하여 형성된 제1반도체칩(2a)이 위치되어 있고, 상기 제1반도체칩(2a)의 입출력패드가 형성된 동일면에는 접착제(10)로 제2반도체칩(2b)이 접착되어 있으며, 상기 제2반도체칩(2b)의 입출력패드(4) 역시 하면을 향하고 있다. 상기 접착제(10)는 통상적인 에폭시 접착제를 사용하거나 또는 양면 테이프 등을 이용할 수 있다.A first semiconductor chip 2a having a plurality of input / output pads (not shown) formed on one surface thereof is disposed on a lower surface thereof, and the second surface is formed of an adhesive 10 on the same surface on which the input / output pad of the first semiconductor chip 2a is formed. The semiconductor chip 2b is bonded, and the input / output pad 4 of the second semiconductor chip 2b also faces the lower surface. The adhesive 10 may be a conventional epoxy adhesive or a double-sided tape.
여기서, 상기 제1반도체칩(2a) 또는 제2반도체칩(2b)중 적어도 하나는 평면상 직사각형 모양으로 형성함으로써 입출력패드(4)가 서로 간섭하지 않아 차후 접속수단(30)의 연결 작업을 용이하게 하도록 함이 바람직하며, 제1반도체칩(2a) 및 제2반도체칩(2b) 모두 직사각형으로 구비할 수도 있다. 더불어, 상기 제1반도체칩(2a)과 제2반도체칩(2b)의 입출력패드(4)는 단면 또는 평면상으로 보았을 때 서로 다른 위치에 형성되거나 위치되도록 함으로써 상기 접속수단(30)의 연결 작업을 보다 용이하게 함이 바람직하다. 즉, 상기 제1반도체칩(2a)의 입출력패드가 평면상에서 상,하면의 가장자리에 위치되었다면, 제2반도체칩(2b)의 입출력패드는 평면상에서 좌,우측에 위치하도록 함이 바람직하다.Here, at least one of the first semiconductor chip 2a or the second semiconductor chip 2b is formed in a planar rectangular shape so that the input / output pads 4 do not interfere with each other, thereby facilitating the connection of the connecting means 30 later. Preferably, the first semiconductor chip 2a and the second semiconductor chip 2b may have a rectangular shape. In addition, the input and output pads 4 of the first semiconductor chip 2a and the second semiconductor chip 2b are connected or connected to the connection means 30 by being formed or positioned at different positions in a cross-sectional or planar view. It is preferable to make it easier. That is, if the input / output pads of the first semiconductor chip 2a are positioned on the top and bottom edges of the plane, the input / output pads of the second semiconductor chip 2b may be positioned on the left and right sides of the plane.
한편, 상기 제1반도체칩(2a)의 외주연에는 회로기판(20)이 위치되어 있다. 상기 회로기판(20)에는 일정크기의 관통공(22)이 형성되고, 그 관통공(22)에 제1반도체칩(2a)이 수용되어 있는 것이다. 상기 회로기판(20)은 수지층(21)을 중심으로 하면에 도전성 회로패턴(23)이 미세하게 형성되어 있으며, 상기 회로패턴(23)은 외부환경으로부터 보호되도록 커버코트(25)로 코팅되어 있다.On the other hand, the circuit board 20 is positioned on the outer periphery of the first semiconductor chip 2a. The circuit board 20 has a through hole 22 having a predetermined size, and the first semiconductor chip 2a is accommodated in the through hole 22. The circuit board 20 has a fine conductive circuit pattern 23 formed on the bottom surface of the resin layer 21, and the circuit pattern 23 is coated with a cover coat 25 to be protected from the external environment. have.
또한, 상기 제1반도체칩(2a) 및 제2반도체칩(2b)의 입출력패드(4)는 회로기판(20)의 하면에 형성된 회로패턴(23)과 도전성와이어 등의 전기적 접속수단(30)에 의해 연결되어 있다. 따라서 상기 제1반도체칩(2a) 및 제2반도체칩(2b)의 전기적 신호는 상기 접속수단(30)에 의해 회로패턴(23)으로 전달되거나 또는 전달받는다.In addition, the input / output pads 4 of the first semiconductor chip 2a and the second semiconductor chip 2b may include a circuit pattern 23 formed on the bottom surface of the circuit board 20 and electrical connection means 30 such as conductive wires. Connected by Therefore, the electrical signals of the first semiconductor chip 2a and the second semiconductor chip 2b are transmitted to or received from the circuit pattern 23 by the connection means 30.
그리고, 상기 제1반도체칩(2a), 제2반도체칩(2b), 접속수단(30) 등은 외부의 먼지, 습기 및 기계적 충격 등으로부터 보호되도록 봉지재로 봉지되어 있다. 상기 봉지재로 봉지된 영역을 봉지부(40)라 한다. 더불어, 상기 회로기판(20)의 하면에 형성된 회로패턴(23)에는 다수의 도전성볼(50)이 융착되어 차후 메인보드에 실장가능하게 되어 있다. 상기 도전성볼(50)은 솔더볼(solder ball)로 함이 바람직하다.The first semiconductor chip 2a, the second semiconductor chip 2b, the connecting means 30, and the like are encapsulated with an encapsulant so as to be protected from dust, moisture, mechanical shock, and the like. The region encapsulated with the encapsulant is called encapsulation 40. In addition, a plurality of conductive balls 50 are fused to the circuit pattern 23 formed on the bottom surface of the circuit board 20 to be mounted on the main board later. The conductive ball 50 is preferably a solder ball (solder ball).
여기서, 상기 제1반도체칩(2a) 및 제2반도체칩(2b)의 입출력패드(4) 형성 방향은 회로패턴(23) 또는 도전성볼(50)의 형성 방향과 같으므로, 상기 회로기판(20)의 상면에는 회로패턴(23)이나 커버코트(25) 층을 별도로 더 형성하지 않음이 바람직하다.Here, since the direction in which the input / output pads 4 of the first semiconductor chip 2a and the second semiconductor chip 2b are formed is the same as the direction in which the circuit pattern 23 or the conductive balls 50 are formed, the circuit board 20 is formed. It is preferable that the circuit pattern 23 or the cover coat 25 layer is not additionally formed on the upper surface of the substrate.
또한, 상기 제1반도체칩(2a)의 상면 즉, 제2반도체칩(2b)과 접하지 않는 반대면은 봉지부(40) 외측으로 노출시켜 열방산 성능을 향상시킴이 바람직하다. 또한 도1b에서와 같이 상기 제1반도체칩(2a) 및 수지층(21) 상면에는 열도전성층(60) 예를 들면, 구리(Cu), 알루미늄(Al) 등의 도전성층을 더 형성하여 열방산 성능을 더욱 향상시킬 수도 있다.In addition, the upper surface of the first semiconductor chip 2a, that is, the opposite surface not in contact with the second semiconductor chip 2b, may be exposed outside the encapsulation portion 40 to improve heat dissipation performance. In addition, as shown in FIG. 1B, a thermally conductive layer 60, for example, copper (Cu), aluminum (Al), or the like is further formed on the first semiconductor chip 2a and the resin layer 21 to form heat. It is also possible to further improve acid performance.
더불어, 도1a, 도1b에서는 반도체칩(2a,2b)의 입출력패드(4)가 하면을 향하여 있지만, 도1c에서와 같이 그 입출력패드(4)가 상면을 향하도록 하는 것도 가능하다. 이때에는 상기 회로기판(20)의 상면 즉, 수지층(21)의 상면에도 회로패턴(23)을 형성하고, 상기 회로패턴은 하부의 회로패턴과 도전성 비아홀(23a)로 연결하여 신호 경로를 확보한다. 더불어, 상기 수지층(21)의 상면의 회로패턴(23)도 외부환경으로부터 보호하기 위해 커버코트(25)로 코팅함이 바람직하다.1A and 1B, the input / output pads 4 of the semiconductor chips 2a and 2b face the bottom surface, but the input / output pads 4 may face the top surface as shown in Fig. 1C. In this case, a circuit pattern 23 is formed on the upper surface of the circuit board 20, that is, the upper surface of the resin layer 21, and the circuit pattern is connected to the lower circuit pattern and the conductive via hole 23a to secure a signal path. do. In addition, the circuit pattern 23 on the upper surface of the resin layer 21 is also preferably coated with a cover coat 25 to protect from the external environment.
도2a, 도2b 및 도2c는 본 발명의 제2실시예에 의한 반도체패키지를 도시한 단면도이다.2A, 2B and 2C are cross-sectional views showing a semiconductor package according to a second embodiment of the present invention.
상기 제2실시예는 제1실시예와 유사한 구조이며 그 차이점만을 설명하면 다음과 같다.The second embodiment has a structure similar to that of the first embodiment, and only the difference will be described as follows.
일면에 다수의 입출력패드(도시되지 않음)가 상면을 향하여 형성된 제1반도체칩(2a)이 위치되어 있고, 상기 제1반도체칩(2a)의 입출력패드(4)가 형성된 동일면에는 접착제(10)로 제2반도체칩(2b)이 접착되어 있으며, 상기 제2반도체칩(2b)의 입출력패드(4) 역시 상면을 향하고 있다. 상기 제1반도체칩(2a)의 하면은 봉지부(40) 외측으로 노출시켜 열방산 능력이 증진되도록 하였다.The first semiconductor chip 2a having a plurality of input / output pads (not shown) formed on an upper surface thereof is positioned on one surface thereof, and the adhesive 10 is formed on the same surface on which the input / output pads 4 of the first semiconductor chip 2a are formed. The second semiconductor chip 2b is bonded to each other, and the input / output pad 4 of the second semiconductor chip 2b also faces the upper surface. The lower surface of the first semiconductor chip (2a) is exposed to the outside of the encapsulation portion 40 to enhance the heat dissipation ability.
또한, 상기 제1반도체칩(2a)의 외주연에는 회로기판(20)이 위치되어 있는데, 이는 상기 회로기판(20)에 일정크기의 관통공(22)을 형성하고, 상기 관통공(22)에 제1반도체칩(2a)을 위치시킨 것이다. 상기 회로기판(20)은 수지층(21)을 중심으로 상,하면에 도전성 회로패턴(23)이 미세하게 형성되어 있으며, 상기 회로패턴(23)은 외부환경으로부터 보호되도록 커버코트(25)가 코팅되어 있다. 또한 상기 수지층(21) 상,하면에 형성된 회로패턴(23)은 도전성 비아홀(24)로 상호 접속되어 있다.In addition, a circuit board 20 is positioned on an outer circumference of the first semiconductor chip 2a, which forms a through hole 22 having a predetermined size in the circuit board 20, and the through hole 22. The first semiconductor chip 2a is placed on the substrate. The circuit board 20 has finely formed conductive circuit patterns 23 on the upper and lower surfaces of the resin layer 21. The circuit pattern 23 has a cover coat 25 so as to be protected from an external environment. Coated. In addition, the circuit patterns 23 formed on and under the resin layer 21 are interconnected by conductive via holes 24.
더불어, 상기 제1반도체칩(2a)의 입출력패드는 상기 회로기판(20)의 상면에 형성된 회로패턴(23)과 전기적 접속수단(30)에 의해 접속되어 있으며, 마찬가지로 상기 제2반도체칩(2b)의 입출력패드(4) 역시 상기 회로기판(20)의 상면에 형성된 회로패턴(23)에 전기적 접속수단(30)으로 접속되어 있다. 따라서 제1반도체칩(2a) 및 제2반도체칩(2b)의 전기적 입출력신호는 접속수단(30)을 통하여, 회로기판(20) 상면에 형성된 회로패턴(23), 도전성비아홀(24) 및 회로기판(20) 하면에 형성된 회로패턴(23) 및 마지막으로 도전성볼(50)을 통하여 메인보드로 전달되거나 또는 전달받게 된다.In addition, the input / output pads of the first semiconductor chip 2a are connected to the circuit pattern 23 formed on the upper surface of the circuit board 20 by electrical connection means 30. Similarly, the second semiconductor chip 2b may be used. The input / output pads 4) are also connected to the circuit pattern 23 formed on the upper surface of the circuit board 20 by the electrical connection means 30. Accordingly, the electrical input / output signals of the first semiconductor chip 2a and the second semiconductor chip 2b are connected to the circuit pattern 23, the conductive via hole 24, and the circuit formed on the upper surface of the circuit board 20 through the connection means 30. Through the circuit pattern 23 formed on the lower surface of the substrate 20 and finally the conductive ball 50 is transmitted to or received from the main board.
여기서도 상기 회로기판(20)에 형성된 관통공(22)으로 인하여 제1반도체칩(2a)의 두께가 상쇄됨으로써 결국 초박형의 반도체패키지를 얻을 수 있게 되며, 또한 제2반도체칩(2b)과 회로기판(20) 사이를 접속하는 접속수단(30)의 만곡높이도 크지 않게 됨으로써 종래와 같은 접속수단(30)의 스위핑 현상을 방지하게 된다.Here too, the through-hole 22 formed in the circuit board 20 cancels the thickness of the first semiconductor chip 2a, so that an ultra-thin semiconductor package can be obtained. In addition, the second semiconductor chip 2b and the circuit board can be obtained. Since the curvature height of the connection means 30 which connects between 20 is also not large, the sweeping phenomenon of the connection means 30 conventionally is prevented.
한편, 도2b에 도시된 바와 같이 크기가 서로 다른 제1반도체칩(2a)과 제2반도체칩(2b)을 구비할 수도 있다. 즉, 제1반도체칩(2a)보다 작은 제2반도체칩(2b)을 구비하고, 상기 제2반도체칩(2b)을 제1반도체칩(2a)에 접착층(10)을 이용하여 접착하게 된다. 이때, 상기 제1반도체칩(2a) 및 제2반도체칩(2b)의 입출력패드(4)는 같은 방향으로도 형성될 수 있는 장점이 있고, 마찬가지로 초박형의 반도체패키지를 유지함은 물론이다. 또한 도2c에 도시된 바와 같이 회로기판(20)에 다수의 관통공(22)을 형성함으로써 다수의 반도체칩을 각각 적층한 형태로 할 수도 있으며, 이는 당업자의 선택적 사항에 불과하다.Meanwhile, as shown in FIG. 2B, the first semiconductor chip 2a and the second semiconductor chip 2b having different sizes may be provided. That is, the second semiconductor chip 2b smaller than the first semiconductor chip 2a is provided, and the second semiconductor chip 2b is attached to the first semiconductor chip 2a using the adhesive layer 10. At this time, the input and output pads 4 of the first semiconductor chip 2a and the second semiconductor chip 2b have the advantage that they can be formed in the same direction, as well as maintaining the ultra-thin semiconductor package. In addition, as shown in FIG. 2C, a plurality of through-holes 22 may be formed in the circuit board 20 so that a plurality of semiconductor chips may be stacked, respectively.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기예만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modifications may be made without departing from the scope and spirit of the present invention.
상기와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 회로기판에 관통공이 형성되고, 상기 관통공에 제1반도체칩 및 제2반도체칩이 적층됨으로써, 상기 관통공이 제1반도체칩의 두께를 상쇄시켜 다수의 반도체칩이 적층됨에도 불구하고 반도체패키지의 두께를 얇게 유지할 수 있는 효과가 있다.According to the semiconductor package according to the present invention as described above, through holes are formed in the circuit board, and the first semiconductor chip and the second semiconductor chip are stacked in the through holes, so that the through holes cancel the thickness of the first semiconductor chip. Although a plurality of semiconductor chips are stacked, there is an effect of keeping the thickness of the semiconductor package thin.
또한, 상기와 같이 다수의 반도체칩이 적층된 구조를 함으로써 다기능을 갖는 여러 반도체칩을 하나의 반도체패키지에 구비할 수 있는 효과가 있다.In addition, the structure in which a plurality of semiconductor chips are stacked as described above has the effect of providing a plurality of semiconductor chips having a multifunction in one semiconductor package.
더불어, 제2반도체칩의 입출력패드와 회로기판 사이의 높이차가 종래 제1반도체칩과 회로기판 사이의 높이차와 같음으로써 접속수단의 만곡높이가 크지 않고, 따라서 반도체칩이 적층된 구조임에도 불구하고 접속수단의 스위핑 발생 가능성을 낮출 수 있는 효과가 있다.In addition, since the height difference between the input and output pads of the second semiconductor chip and the circuit board is the same as the height difference between the first semiconductor chip and the circuit board, the curvature height of the connecting means is not large, and thus the semiconductor chip is laminated. There is an effect that can reduce the possibility of sweeping of the connecting means.
Claims (6)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0035108A KR100400826B1 (en) | 1999-08-24 | 1999-08-24 | semiconductor package |
| JP2000246332A JP2001077301A (en) | 1999-08-24 | 2000-08-15 | Semiconductor package and its manufacturing method |
| US09/648,284 US6798049B1 (en) | 1999-08-24 | 2000-08-24 | Semiconductor package and method for fabricating the same |
| US10/600,931 US6982488B2 (en) | 1999-08-24 | 2003-06-20 | Semiconductor package and method for fabricating the same |
| US11/129,596 US7211900B2 (en) | 1999-08-24 | 2005-05-13 | Thin semiconductor package including stacked dies |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0035108A KR100400826B1 (en) | 1999-08-24 | 1999-08-24 | semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010018945A true KR20010018945A (en) | 2001-03-15 |
| KR100400826B1 KR100400826B1 (en) | 2003-10-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-1999-0035108A KR100400826B1 (en) | 1999-08-24 | 1999-08-24 | semiconductor package |
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| Country | Link |
|---|---|
| KR (1) | KR100400826B1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8801279B2 (en) | 2010-12-28 | 2014-08-12 | Samsung Electronics Co., Ltd. | Semiconductor device with stacked structure having through electrode, semiconductor memory device, semiconductor memory system, and operating method thereof |
| US9780049B2 (en) | 2013-05-16 | 2017-10-03 | Samsung Electronics Co., Ltd. | Semiconductor package |
| CN108987352A (en) * | 2017-05-30 | 2018-12-11 | 英飞凌科技股份有限公司 | Encapsulation with the component being connected at carrier level |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101692441B1 (en) | 2010-08-25 | 2017-01-03 | 삼성전자주식회사 | Semiconductor package |
| KR102164545B1 (en) | 2014-09-11 | 2020-10-12 | 삼성전자 주식회사 | Semiconductor package and package-on-package device including the same and mobile device including the same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3105362B2 (en) * | 1992-09-12 | 2000-10-30 | 日本特殊陶業株式会社 | High density IC package and manufacturing method thereof |
| JP3655338B2 (en) * | 1995-02-28 | 2005-06-02 | シチズン時計株式会社 | Resin-sealed semiconductor device and manufacturing method thereof |
| KR19980023180A (en) * | 1996-09-25 | 1998-07-06 | 김광호 | Heatsink with printed circuit pattern and multichip package using the same |
| JPH11204565A (en) * | 1998-01-16 | 1999-07-30 | Toshiba Corp | Semiconductor device |
| KR100261447B1 (en) * | 1998-04-15 | 2000-07-01 | 최완균 | Multi chip package |
-
1999
- 1999-08-24 KR KR10-1999-0035108A patent/KR100400826B1/en not_active IP Right Cessation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8801279B2 (en) | 2010-12-28 | 2014-08-12 | Samsung Electronics Co., Ltd. | Semiconductor device with stacked structure having through electrode, semiconductor memory device, semiconductor memory system, and operating method thereof |
| US9780049B2 (en) | 2013-05-16 | 2017-10-03 | Samsung Electronics Co., Ltd. | Semiconductor package |
| CN108987352A (en) * | 2017-05-30 | 2018-12-11 | 英飞凌科技股份有限公司 | Encapsulation with the component being connected at carrier level |
| CN108987352B (en) * | 2017-05-30 | 2023-10-20 | 英飞凌科技股份有限公司 | Package with components connected at carrier level |
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| Publication number | Publication date |
|---|---|
| KR100400826B1 (en) | 2003-10-08 |
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