JPH011270A - Package for semiconductor integrated circuits - Google Patents
Package for semiconductor integrated circuitsInfo
- Publication number
- JPH011270A JPH011270A JP62-157076A JP15707687A JPH011270A JP H011270 A JPH011270 A JP H011270A JP 15707687 A JP15707687 A JP 15707687A JP H011270 A JPH011270 A JP H011270A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor integrated
- integrated circuits
- integrated circuit
- packages
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 230000010354 integration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
乙の発明は、半導体集積回路用のパッケージに関するも
のである。[Detailed Description of the Invention] [Industrial Application Field] The invention of B relates to a package for a semiconductor integrated circuit.
第４図、第５図、第６図は従来の半導体パッケージを示
す図であり、図において、１は半導体集積回路のチップ
、２はこのチップ１を保護するパッケージ、３及び４ば
このパッケージ２の両端に取付けられた入、出力ピンで
ある。4, 5, and 6 are diagrams showing conventional semiconductor packages. In the figures, 1 is a semiconductor integrated circuit chip, 2 is a package that protects this chip 1, and 3 and 4 are packages 2 and 4. These are input and output pins attached to both ends of the
以上のようなパッケージにおいて、ピン３より入力され
た信号は、チップ１の半導体集積回路の中で演算等の処
理を行い、出力ピン４にその結果を出力する。In the package as described above, a signal inputted from pin 3 is processed by arithmetic operations in the semiconductor integrated circuit of chip 1, and the result is outputted to output pin 4.
従来の半導体集積回路用パッケージは以上のように構成
されており、ＩＣを複数使用する回路では、その分だけ
パッケージが基板上に配置されることになり、大層場所
を取ってしまうという問題点があった。Conventional packages for semiconductor integrated circuits are constructed as described above, and in circuits that use multiple ICs, the problem is that the packages are placed on the board accordingly, which takes up a lot of space. there were.
乙の発明は上記のような問題点を解決するためになされ
たもので、使用ＩＣ（パッケージ）数を減少させるとと
もに、パッケージピンと他のパッケージ間の配線が不要
となるパッケージを得ることを目的とする。Party B's invention was made to solve the above problems, and aims to reduce the number of ICs (packages) used and to obtain a package that does not require wiring between package pins and other packages. do.
この発明に係る半導体集積回路用パッケージ（、？、１
個のパッケージ内に複数の集積回路（チ・ンプ）を収納
したものである。Package for semiconductor integrated circuit according to this invention (?, 1
Multiple integrated circuits (chips) are housed in a single package.
この発明におけるパッケージは、１個のパッケージに複
数のチップを収納することにより、従来のパッケージに
比し集積度を大幅に高めろことができろ。By accommodating a plurality of chips in one package, the package according to the present invention can greatly increase the degree of integration compared to conventional packages.
第１図、第２図、第３図はこの発明の一実施例を示すも
のであり、図において、１は各々半導体集積回路のチッ
プであり、これらの複数（図では３個）のチップを１個
のパッケージ２の中に収納し保護したものである。なお
３．４Ｎよパッケージの端に取付けられた人、出力ピン
である。1, 2, and 3 show an embodiment of the present invention. In the figures, 1 is a chip of a semiconductor integrated circuit, and a plurality of these chips (three in the figure) are shown. It is housed and protected in one package 2. Note that 3.4N is the output pin attached to the end of the package.
以上のように構成された半導体集積回路用パッケージで
は、１個のパッケージに複数のチップを収納するように
したので、ｍ積度を高めろことができるとともに、パッ
ケージの取るスペースを減らすことができ、コンパクト
化される。In the semiconductor integrated circuit package configured as described above, multiple chips are housed in one package, so it is possible to increase the m-package density and reduce the space taken up by the package. , is made compact.
以上のようにこの発明は、ＩＣのチップを複数個収納す
ることで、半導体集積回路用パッケージの集積度を高め
るという効果がある。As described above, the present invention has the effect of increasing the degree of integration of a semiconductor integrated circuit package by accommodating a plurality of IC chips.
第１図はこの発明の一実施例を示す平面図、第２図はそ
の正面図、第３図はその側面図であり、第４図は従来の
半導体集積回路用パッケージの平面図、第５図はその正
面図、第６図；よその側面図である。
図中、１（よ半導体集積回路のチップ、２はパッケージ
、３は入力ピン、４は出力ピンである。
尚、図中同一符号（よ同−又は相当部分を示す。FIG. 1 is a plan view showing an embodiment of the present invention, FIG. 2 is a front view thereof, and FIG. 3 is a side view thereof. FIG. 4 is a plan view of a conventional semiconductor integrated circuit package. The figure is a front view thereof, and FIG. 6 is a side view from the outside. In the figure, 1 is a chip of a semiconductor integrated circuit, 2 is a package, 3 is an input pin, and 4 is an output pin. In the figure, the same reference numerals (the same - or equivalent parts are shown).
Claims (1)
ージに複数のチップを収納したことを特徴とする半導体
集積回路用パッケージ。A package for a semiconductor integrated circuit, characterized in that a plurality of chips are housed in one package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15707687A JPS641270A (en) | 1987-06-23 | 1987-06-23 | Package for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15707687A JPS641270A (en) | 1987-06-23 | 1987-06-23 | Package for semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH011270A true JPH011270A (en) | 1989-01-05 |
| JPS641270A JPS641270A (en) | 1989-01-05 |
Family
ID=15641717
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15707687A Pending JPS641270A (en) | 1987-06-23 | 1987-06-23 | Package for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS641270A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5375740A (en) * | 1991-04-26 | 1994-12-27 | Toppan Printing Co., Ltd. | Manual dispenser for dispensing predetermined amounts of viscous material through actuation of a trigger |
| WO2004083072A1 (en) * | 1991-07-31 | 2004-09-30 | Takeo Kumada | Dispenser for paste-like substance and method of pushing out paste-like substance |
-
1987
- 1987-06-23 JP JP15707687A patent/JPS641270A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2560805B2 (en) | Semiconductor device | |
| JPS6193694A (en) | Ic device | |
| JPH011270A (en) | Package for semiconductor integrated circuits | |
| JPH0274046A (en) | Semiconductor integrated circuit device | |
| JPS6014460A (en) | Semiconductor integrated circuit | |
| US5463560A (en) | Semiconductor integrated circuit device | |
| JPH04188759A (en) | Semiconductor integrated circuit device | |
| KR20020007576A (en) | Chip-on-board type memory card | |
| JPH11186492A (en) | Semiconductor package and its mounting structure | |
| JPS60244111A (en) | Digital filter circuit | |
| JPH0250623B2 (en) | ||
| JPH01293647A (en) | Semiconductor device | |
| JPH0760855B2 (en) | Integrated circuit device | |
| JPH0349255A (en) | Sealing of semiconductor integrated circuit | |
| JPH11340272A (en) | Semiconductor integrated circuit and semiconductor integrated circuit device | |
| JPS5984455A (en) | Package for high density memory | |
| JPH01114061A (en) | Semiconductor package | |
| JPH03261152A (en) | Semiconductor integrated circuit device | |
| TW410410B (en) | An arrangement of data input/output circuits for use in a semiconductor memory device | |
| JPH01179424A (en) | Semiconductor device | |
| JPS6364054B2 (en) | ||
| JPS5813789U (en) | Video signal processing device | |
| JPH1012660A (en) | Integrated circuit for surface mounting | |
| JPH04180257A (en) | Method of mounting integrated circuit | |
| JPS58133837U (en) | semiconductor equipment |