410410 4537twf.d〇c/002 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（/ ) 本發明是有關於一種半導體記憶體元件’且特別是有 關於一種數據輸入/輸出電路，具有其銲墊和緩衝器適用於 極高度之半導體記憶體元件。 發明之背景 第1圖繪示根據習知技術所顯示半導體記憶體元件之 晶片佈局。在第1圖中，半導體記憶體元件形成在一半導 體晶片1上，以及包括四個記憶體記憶胞區塊10T、10B、 11T以及11B。每一記憶體記憶胞區塊10T、10B、11T以 及11B包括複數個記憶體記憶體記憶胞，雖然沒有顯示。 在正常運作期間(在內部運作期間），在每一記憶體記憶 胞區塊10T、ΙΟΒ、11T以及11B選擇一位元記憶體記憶胞， 以及數據寫入/讀出/從每一記憶體記憶胞區塊1〇Τ、10B、 11 τ 以及 11B。 在半導體晶片1之中心區域(一區域在記憶體記憶胞區 塊10T、10B、11T以及11B之間）所排列電路12、14以及 16，具有複數個銲墊和緩衝器用以作信號之輸入和輸出。 像銲墊排列於晶片中心區域之結構，例如一般熟知的導線 在晶片（Lead On Chip ; LOC)排列，在導線架構之尖端佈置 在晶片上，以及導線架構連接在個別尖端到銲墊，排列在 晶片之中心區域，藉由使用接合線。在晶片中心區域之銲 墊對準’允許藉由銲墊藕接於此區域，以降低關於對照結 構在銲墊上，其中銲墊排列在半導體晶片1沿著兩側之周 邊部分。在此改善半導體晶片1使用的效率。 第1圖之晶片佈局揭露美國專利字號N05,627,729名 ..請 :t •背 意 事 項 ' I 裝 訂 線 本·紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） 410410 453 7twf.doc/002 A7 B7 五、發明説明（7 ) ' 爲 LOC TYPE SEMICONDUCTOR MEMORY DEVICE，在 此用來參考配合。 請 I 讀 背 之 注 意 事 項 Λ ' ϊ έ. i 1 一般而言，相關低密度之半導體記憶體元件包裝使用 具有使用如 JEDEC 標準之 ODIC(Outer-DQ-Inner-Control) 型之腳位佈局的封裝，在ODIC型封裝的腳位佈局，數據 輸入/輸出腳位排列於封裝兩側外部，以及位址和控制腳位 排列於數據輸入/輸出腳位之內部。雖然數據輸入/輸出腳 位在此排列於兩側外部，在數據輸入/輸出腳位之間沒有偏 斜發生，因爲小的封裝。 訂 當積極密度增加，執行時間縮短，但是具有彼此相同 功能的腳位之信號之間偏斜（例如在數據輸入/輸出腳位之 間）可能發生於ODIC型封裝之案例。爲防止此問題所導致 起結果，NON-ODIC型之封裝可能被使用。此案例下之記 憶體元件包裝使用NON-ODIC型封裝，彼此間具有相同功 能之腳位共同排列於相鄰區域，使得具有相同功能信號間 之腳位的偏斜減小。 線 經濟部智慧財產局員工消費合作社印製 爲簡化封裝連結，典型上銲墊形成於半導體晶片上， 排列以相同佈局作封裝。特別是，如果半導體記憶體元件 封裝藉由使用具有ODIC型腳位步局之封裝，形成在半導 體晶片之銲墊上，可以使用ODIC型結合。相同的，如果 半導體記憶體元件封裝藉由使用NON-ODIC型腳位佈局之 封裝’形成於半導體晶片之銲墊可以使用NON-ODIC型排 列。 如果半導體記憶體元件之數據輸入/輸出、位址信號和 本纸張尺度適用中國國家標準（CMS ) A4規格（2I0X297公釐） 410410 4537twf.d〇c/002 乂， B7 五、發明説明（,） 控制信號墊，具有極高密度，例如lGiga-bit電容，排列根 據上述描繪銲墊排列方式，半導體記憶體元件之全部速度 延遲可被作成。特別是第1圖，當數據寫入/讀取到/從記 憶體記憶胞區塊10T和10B和到記憶體記憶胞區塊111和_ ΠΒ，數據線（或數據傳輸/接收途徑）15在數據輸入/輸出電‘ .路16和記憶體記憶胞區塊10T和10B之間，在長度在較 大於在數據輸入/輸出電路16和記憶體記憶胞區塊11T和 11B之間。即是，對應記憶體記憶胞區塊10ΊΓ和10B數據 線之電阻和電容·，遠大於對應記憶體記憶胞區塊11T和11B 數據線之電阻和電容。先前之信號增加.延遲在時間上大於 後者。因此造成執行時間更長。特別是，當從記憶體記憶 '胞區塊10T和10B之數據讀出顯示於所對應數據輸入/輸出 銲墊時的時間，延遲於根據從記憶體記憶胞區塊數據讀取 顯示在所對應數據輸入/輸出銲墊的時間。 因此，因爲藉由延遲數據輸出時間，來決定半導體記 憶體元件之數據輸出時間，對於在極高密度記憶體元件下 很難以實行，即是在極高密度記憶體元件根據上述腳位排 列方式無法在高速執行運作。 經濟部智慧財產局員工消費合作社印製 發明摘要 有鑒於此，本發明的目的就是在提供一種數據輸入/輸 出電路之排列，適用於極高密度之半導體記憶體元件。 本發明的另一目的，提出一種半導體記憶體元件具有 數據輸入/輸出電路之排列，能夠在高速下運作。 爲達成上述目的，根據本發明在此提供一種半導體記 本紙張尺度適用中國國家標準（CNS ) A4規格（2IOX297公釐） 4537tw 410,410 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（Y) 1思體兀件’包括·複數個憶體記憶胞區塊、複數數據輸 入/輸出電路、複數個控制信號電路以及複數個位址信號電 路。複數個記億體記憶胞區塊，位於行與列方向上，每一 記憶體記憶胞區塊具有複數個記憶體記憶胞，用以儲存數 .據訊息。以及複數個數據輸入/輸出電路，區分成一第一組 和一第二組，其中第一和第二組排列以便對應於記憶體記 憶胞區塊以及在所對應記憶體記憶胞區塊之間，其中數據 輸入/輸出電路分別具有一數據輸入/輸出銲墊和一數據輸 入/輸出緩衝器。，此外複數個位址信號電路，排列在該第一 和第二組之間，用以接收內部使用之複數個位址信號。其 中位址信號電路分別具有一位址信號墊和一位址信號緩衝 器。此外複數個控制信號電路相鄰排列於第一組之數據輸 入/輸出電路與記憶體記憶胞區塊之間，並對應於數據輸入 /輸出電路之第一組。其中，控制信號電路分別具有一控制 信號墊和一控制信號緩衝器，以及其中半導體記憶體元件 包裝藉由一Non-Outer-DQ-Irmer-Control (NON-ODIC)型之 封裝，該NON-ODIC型之封裝具有數據輸入/輸出腳位之結 構，每一該數據輸入/輸出腳位對應到共同排列於相鄰一起 之該第一與第二組之該數據輸入/輸出電路。 圖式之簡單描沭 . 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式’作詳細 說明如下： 第1圖繪示習知半導體記憶體元件之晶片佈局區塊圖 請 先 背 意 事 項 Λ 頁 訂 線 本紙張尺度適用申國國家標準（CNS ) A4規格（210X297公釐） 4 5 3 71 w ί· A7 B7 五、發明説明（Γ) 形； 第2圖繪示根據本發明之半導體記憶體元件之晶片佈 局區塊圖形；以及 第3圖繪示NON-ODIC型之具有接腳位佈局的封裝圖 經濟部智慧財產局員工消費合作社印製 形。 圖式之標號說明： 1:半導體晶片 10B，10T，11B，11T:記憶體記憶胞區塊 12，14，16:' 電路 15:數據線 100B，100T:記憶體記憶胞區塊 110B，110T:記憶體記憶胞區塊 120:數據輸入/輸出電路 122:數據輸入/輸出電路 124:控制信號電路 126:位址信號電路 128:位址匯流排 130:數據匯流排 132:數據匯流排 1000:半導體晶片 較佳實施例描述 本發明知要加實施例將在下面伴隨參考圖形進行描 述。 本發明之新的半導體記憶體元件，參考第2圖，數據 ΐ 先 閣 讀 •背 _ 裝 訂 線 本紙張尺度適用中國國家標準（CMS > A4規格（210 X 297公釐） A7 B7 410410 4 537twr.doc/002 五、發明説明（沴） 訂 輸入/輸出電路120之第一組具有其銲墊即緩衝器排列在半 導體晶片1000(在半導體晶片1000之中心區域)左側所對應 記憶體記憶胞區塊100T和100B之間，以及數據輸入/輸出 電路I22之第二組，在此位於(在半導體晶片1000之中心 .區域）右側所對應記憶體記憶胞區塊110T和110B之間。在 數據輸入/輸出電路120之第一組和數據輸入/輸出電路122 之第二組之間’控制信號電路124和位址信號電路126分 別具有排列之銲墊和緩衝器，如第2圖所示。半導體晶片 100.0具有鍵墊佈局如上所提出包裝藉由一 NON-ODIC (Non-Outer-DQ-Inner-Control)型之封裝，該 NON-ODIC 型 之封裝具有共同排列於封裝一側之數據輸入/輸出腳位之 結構。根據數據輸入/輸出電路之排列，當製造半導體記憶 體兀件時’具有極長I密度，例如一Giga-Bit電容，沒有偏 斜之數據輸入/輸出銲墊的信號之間能夠最小化，所以具有 非常密度之半導體元件能夠時現在高速執行運作。 經濟部智慧財產局員工消費合作社印製 再參考第2圖，繪示根據本發明之半導體記憶體元件 所繪示晶片佈局圖形。半導體記憶體元件包括四個記憶體 記憶胞區塊100T、100B、110T以及110B排列在矩陣形式。 每一記憶體記憶胞區塊100T、100B、110T以及110B包括 複數個記憶體記憶胞用以儲存Ι-bit訊息。數據輸入/輸出 電路120之第一組排列於記憶體記憶胞區塊ι〇〇τ和i〇〇B 之中心區域，數據輸入/輸出電路I22之第二組位於記憶體 記憶胞區塊110T和110B之中心區域。數據輸入/輸出電路 120之第一組對應於記憶體記憶胞區塊ι〇〇ΊΓ和i〇〇b，以 10 本紙張尺度適用中國國家樣準（CNS ) A4規格（210X29*7公釐） A7 B7410410 4537twf.d〇c / 002 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (/) The present invention relates to a semiconductor memory element, and in particular to a data input / output circuit. With its pads and bumpers, it is suitable for extremely high semiconductor memory devices. BACKGROUND OF THE INVENTION FIG. 1 shows a wafer layout of a semiconductor memory device according to a conventional technique. In Fig. 1, a semiconductor memory element is formed on a semi-conductive wafer 1 and includes four memory cell blocks 10T, 10B, 11T, and 11B. Each memory cell block 10T, 10B, 11T, and 11B includes a plurality of memory memory cells, although not shown. During normal operation (during internal operation), select a one-bit memory cell in each memory cell block 10T, 10B, 11T, and 11B, and write / read data to / from each memory cell Cell blocks 10T, 10B, 11 τ, and 11B. Circuits 12, 14 and 16 are arranged in the central area of semiconductor wafer 1 (an area between the memory cell blocks 10T, 10B, 11T and 11B), having a plurality of pads and buffers for signal input and Output. Structures like solder pads arranged in the central area of the wafer. For example, generally known wires are arranged on the chip (Lead On Chip; LOC), the tip of the wire structure is arranged on the wafer, and the wire structure is connected to the individual tips to the pads, arranged in The central area of the wafer, by using bonding wires. The pad alignment in the center region of the wafer allows the pad to be connected to this area to reduce the relative structure on the pad, wherein the pads are arranged on the peripheral portion of the semiconductor wafer 1 along both sides. The efficiency of use of the semiconductor wafer 1 is improved here. The layout of the chip in Figure 1 reveals the U.S. Patent No. N05,627,729 .. Please: t • Remembrance 'I Binder and paper size are applicable to China National Standard (CNS) A4 (210X297 mm) 410410 453 7twf. doc / 002 A7 B7 V. Description of the Invention (7) 'It is LOC TYPE SEMICONDUCTOR MEMORY DEVICE, which is used here for reference. Please read the precautions for reading Λ 'έ i. I 1 Generally speaking, the packaging of low-density semiconductor memory components is based on the use of ODIC (Outer-DQ-Inner-Control) pin layouts such as the JEDEC standard. Package, the pin layout of the ODIC type package, the data input / output pins are arranged outside the two sides of the package, and the address and control pins are arranged inside the data input / output pins. Although the data input / output pins are arranged outside the two sides here, no skew occurs between the data input / output pins because of the small package. When the active density is increased, the execution time is shortened, but the skew between the signals of pins with the same function (such as between data input / output pins) may occur in the case of ODIC-type packages. To prevent this problem from occurring, NON-ODIC type packages may be used. The memory component packaging in this case uses a NON-ODIC type package. Pins with the same function between them are arranged in adjacent areas, so that the skew of the pins with the same function signal is reduced. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. To simplify the packaging connection, typical pads are formed on the semiconductor wafers, arranged in the same layout as the package. In particular, if a semiconductor memory device package is formed on a pad of a semiconductor wafer by using a package having an ODIC type footstep, an ODIC type bonding can be used. Similarly, if a semiconductor memory device package is formed by a package using a NON-ODIC type pin layout, a pad formed on a semiconductor wafer can use a NON-ODIC type arrangement. If the data input / output, address signals and dimensions of this semiconductor memory device are applicable to the Chinese National Standard (CMS) A4 specification (2I0X297 mm) 410410 4537twf.d0c / 002 乂, B7 V. Description of the invention (, ) Control signal pads with extremely high density, such as lGiga-bit capacitors. Arrangement According to the pad layout method described above, all speed delays of semiconductor memory elements can be made. In particular, when data is written / read to / from the memory cell blocks 10T and 10B and to the memory cell blocks 111 and _ΠB, the data line (or data transmission / reception path) 15 is The data input / output circuit is larger between the circuit 16 and the memory cell blocks 10T and 10B than the data input / output circuit 16 and the memory cell blocks 11T and 11B. That is, the resistance and capacitance of the data lines corresponding to the memory cell blocks 10ΊΓ and 10B are much larger than the resistance and capacitance of the corresponding data lines of the memory cell blocks 11T and 11B. The previous signal increases. The delay is greater in time than the latter. This results in longer execution times. In particular, the time when the data from the memory cell blocks 10T and 10B are read and displayed on the corresponding data input / output pads is delayed from the time when the data is read from the memory cell blocks and displayed on the corresponding data block. Data input / output pad time. Therefore, because the data output time of the semiconductor memory device is determined by delaying the data output time, it is difficult to implement under the extremely high density memory device, that is, the extremely high density memory device cannot be arranged according to the above-mentioned pin arrangement method. Perform operations at high speed. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics Summary of the Invention In view of this, the object of the present invention is to provide a data input / output circuit arrangement suitable for extremely high density semiconductor memory devices. Another object of the present invention is to provide a semiconductor memory device having a data input / output circuit arrangement capable of operating at a high speed. In order to achieve the above purpose, according to the present invention, a semiconductor notebook paper size applicable to the Chinese National Standard (CNS) A4 specification (2IOX297 mm) 4537tw 410,410 A7 B7 is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Y) 1 thinking physical element 'includes a plurality of memory cell blocks, a plurality of data input / output circuits, a plurality of control signal circuits, and a plurality of address signal circuits. Plural memory cell blocks are located in the row and column directions. Each memory cell block has a plurality of memory cells for storing data information. And a plurality of data input / output circuits, divided into a first group and a second group, wherein the first and second groups are arranged so as to correspond to the memory cell block and between the corresponding memory cell block, The data input / output circuit has a data input / output pad and a data input / output buffer, respectively. In addition, a plurality of address signal circuits are arranged between the first and second groups to receive a plurality of address signals for internal use. The address signal circuit has a one-address signal pad and one-address signal buffer, respectively. In addition, a plurality of control signal circuits are adjacently arranged between the data input / output circuit of the first group and the memory cell block, and correspond to the first group of data input / output circuits. The control signal circuit has a control signal pad and a control signal buffer, and the semiconductor memory device is packaged by a Non-Outer-DQ-Irmer-Control (NON-ODIC) type package. The NON-ODIC The type of package has a structure of data input / output pins, and each of the data input / output pins corresponds to the data input / output circuits of the first and second groups which are arranged adjacent to each other. Brief description of the drawings. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings' as follows: FIG. 1 To draw a block diagram of the layout of a conventional semiconductor memory device, please note the following: Λ Page aligning The paper size applies to the National Standard of China (CNS) A4 (210X297 mm) 4 5 3 71 w ί · A7 B7 V. Description of the invention (Γ) shape; FIG. 2 shows a block layout block pattern of a semiconductor memory element according to the present invention; and FIG. 3 shows a NON-ODIC type package diagram with pin layout Printed by Intellectual Property Bureau employee consumer cooperatives. Explanation of the symbols of the drawings: 1: Semiconductor wafers 10B, 10T, 11B, 11T: Memory cell blocks 12, 14, 16 :: 'Circuit 15: Data lines 100B, 100T: Memory cell blocks 110B, 110T: Memory cell block 120: data input / output circuit 122: data input / output circuit 124: control signal circuit 126: address signal circuit 128: address bus 130: data bus 132: data bus 1000: semiconductor Description of Preferred Embodiments of the Wafer The embodiments of the present invention will be described below with reference to the drawings. The new semiconductor memory element of the present invention, refer to Figure 2, data ΐ read first • back _ binding line This paper size applies to Chinese national standards (CMS > A4 size (210 X 297 mm) A7 B7 410410 4 537twr .doc / 002 V. Description of the Invention (沴) The first group of the order input / output circuit 120 has its pads, that is, buffers arranged on the left side of the semiconductor wafer 1000 (in the center area of the semiconductor wafer 1000). Between the blocks 100T and 100B, and the second group of the data input / output circuit I22, which is located between the corresponding memory cells 110T and 110B (on the center and area of the semiconductor wafer 1000) on the right. Between the first group of the I / O circuit 120 and the second group of the data I / O circuit 122, the control signal circuit 124 and the address signal circuit 126 have arranged pads and buffers, respectively, as shown in FIG. 2. Semiconductor The chip 100.0 has a key pad layout as mentioned above. The package is packaged by a NON-ODIC (Non-Outer-DQ-Inner-Control) type package. The NON-ODIC type package has data inputs arranged on one side of the package. The structure of the I / O pin. According to the arrangement of the data I / O circuit, when manufacturing semiconductor memory components, it has a very long I density, such as a Giga-Bit capacitor, and there is no skewed data input / output pad signal. Can be minimized, so semiconductor devices with very high density can now perform high-speed operation. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and referring to Figure 2, the wafers shown in the semiconductor memory device according to the present invention are shown. Layout pattern. Semiconductor memory components include four memory cell blocks 100T, 100B, 110T, and 110B arranged in a matrix form. Each memory cell block 100T, 100B, 110T, and 110B includes a plurality of memory cell cells. It is used to store 1-bit information. The first group of data input / output circuit 120 is arranged in the central area of memory cell blocks ι〇〇τ and i〇〇B, and the second group of data input / output circuit I22 is located The central area of the memory cell blocks 110T and 110B. The first group of the data input / output circuit 120 corresponds to the memory cell blocks ι〇〇ΊΓ and i 〇b to 10 scale applicable Chinese paper-like quasi-national (CNS) A4 size (210X29 * 7 mm) A7 B7
41Q41Q 4537twf.doc/〇〇2 五、發明説明（7 ) 請 .先 閱 讀 背 © 之 注 意. 事 項. 1Λ. 1裝 Μ 及數據輸入/輸出電路122之第二組對應於記憶體記憶胞區 塊110T和110B。雖然在第2圖未顯示，數據輸入/輸出120 和122包括數據輸入/輸出墊和數據輸入/輸出緩衝器，對 相鄰來分別提供。 第2圖用以數據傳輸/接收之數據匯流排130，排列以 藕接相對應於記憶體記憶胞區塊1Q0T和100B之數據輸入 /輸出電路120之第一組，以及用以數據傳輸/接收之數據 匯流排132,排列以藕接對應於記憶體記憶胞區塊110T和 110B之數據輸入/輸出電路122之第二組。 訂 線丨 經濟部智慧財產局員工消費合作社印製 再參考第2圖，用以接收內部位址信號之位址信號電 路126，排列在記憶體記憶胞區塊110T和110B之間，以 及鄰近在數據輸入/輸出電路122之第二組。位址信號經由 —共用位址匯流排128，傳輸到記憶體記憶胞區塊100T、 100B、U0T以及110B。雖然未在第2圖顯示，位址信號 電路126包括數據輸入/輸出墊和數據輸入/輸出緩衝器， 對相鄰來分別提供。用以接收控制信號（例如內部時脈信 號、關於讀取/寫入運作之內部信號）之控制信號電路124， 排列在相鄰數據輸入/輸出電路120之第一組的記憶體記憶 胞區塊100T和100B之間。雖然在第2圖未顯示，數據輸 入/輸出120和122包括數據輸入/輸出墊和數據輸入/輸出 緩衝器，對相鄰來分別提供。 . 第3圖繪示封裝之數據輸入/輸出腳位和半導體晶片之 數據輸入/輸出銲墊之間關係圖形。在第3圖位址信號和控 制信號銲墊在封裝之中心區域，排列於數據輸入/輸出銲墊 11 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 410410 4537twf.dac/002 A7 B7 經濟部智慧財產41Q41Q 4537twf.doc / 〇〇2 V. Description of the invention (7) Please read the note of the first ©. Matters. 1Λ. 1 The second set of 122 and data input / output circuit 122 corresponds to the memory cell block 110T and 110B. Although not shown in Figure 2, the data input / output 120 and 122 include data input / output pads and data input / output buffers, and are provided adjacent to each other. FIG. 2 is a data bus 130 for data transmission / reception, arranged to connect the first group of data input / output circuits 120 corresponding to the memory cell blocks 1Q0T and 100B, and for data transmission / reception The data bus 132 is arranged to connect to the second group of the data input / output circuits 122 corresponding to the memory cell blocks 110T and 110B. Ordering line 丨 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs and referring to Figure 2, the address signal circuit 126 for receiving the internal address signal is arranged between the memory cell blocks 110T and 110B, and adjacent to The second group of data input / output circuits 122. The address signal is transmitted to the memory cell blocks 100T, 100B, U0T, and 110B via the shared address bus 128. Although not shown in Fig. 2, the address signal circuit 126 includes a data input / output pad and a data input / output buffer, which are provided separately for adjacent ones. A control signal circuit 124 for receiving a control signal (such as an internal clock signal and an internal signal related to read / write operation) is arranged in a memory cell block of the first group of adjacent data input / output circuits 120 Between 100T and 100B. Although not shown in Figure 2, the data input / output 120 and 122 include data input / output pads and data input / output buffers, and are provided separately for adjacent ones. Figure 3 shows the relationship between the data input / output pins of the package and the data input / output pads of the semiconductor chip. In Figure 3, the address signal and control signal pads are arranged in the central area of the package, and are arranged on the data input / output pads. 11 This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 410410 4537twf.dac / 002 A7 B7 Intellectual Property of the Ministry of Economic Affairs
办費合作社印製 五、發明説明（？） 120之第一組和數據輸入/輸出銲墊U2之第二組之間。即 數據輸入/輸出、位址信號和控制信號銲墊位於所根據的 ODIC型上。數據輸入/輸出腳位Dqi在封裝之兩側彼此共 同抬列相鄰。即是數據輸入/輸出腳位於所根據的NON-.ODIC型。當封裝腳位連結使用引線之所對應銲墊，該引線 彼此相互交錯連接，所以引線交錯成爲一短路電路。爲避 免這種問題，雖然在第3圖未顯示，引線可使用多層結構 來連結。雖然引線長度以交錯相較於習知會較長。電阻和 引線之電容因此變得較長可以忽略，卻因此遠小於半導體 晶片上之因素。 根據本發明之數據輸入/輸出電路的排列，當從記憶體 記憶胞區塊100T和100B或從記憶體記憶胞區塊110T和 110B所讀出數據，數據傳輸/接收途徑（或數據線）130在第 一組之數據輸入/輸出電路120和記憶體記憶胞區塊10T和 10B之間，相同或相似於在第二組之數據輸入/輸出電路 122和記憶體記憶胞區塊110T和110B之間。在此案例， 半導體記憶體元件具有電容，例如一 Giga-bit密度，使得 第一組120之數據輸入/輸出銲墊的信號之間沒有偏斜。相 同的，也使得第二組122之數據輸入/輸出銲墊的信號之間 沒有偏斜。更淸楚地說，因爲極高密度之半導體記憶體元 件封裝使用具有NON-ODIC型腳位佈局之封裝，沒有偏斜 \發生在封裝之數據輸入/輸出腳位的信號之間。因此，可以 %1^現在半導體記憶體元件在極高密度下，能夠運作以高速 :據執行運作。 12 請 先 Μ 讀 意 事 本 頁 裝 訂 線 本紙果尺度適用中國國家標準（CNS ) Μ規格（2!〇χ297公釐）Printed by the co-operative cooperative V. Invention description (?) 120 between the first group and the second group of data input / output pad U2. That is, the data input / output, address signal and control signal pads are located on the ODIC type according to which. The data input / output pins Dqi are adjacent to each other on both sides of the package. That is, the data input / output pin is based on the NON-.ODIC type. When the package pins are connected to the corresponding pads of the leads, the leads are staggered to each other, so the leads are staggered into a short circuit. To avoid this problem, although not shown in Figure 3, the leads can be connected using a multilayer structure. Although the lead length is longer than conventional, it is longer. The resistance and the capacitance of the leads therefore become longer and negligible, but are therefore much smaller than the factors on the semiconductor wafer. According to the arrangement of the data input / output circuit of the present invention, when data is read from the memory cell blocks 100T and 100B or from the memory cell blocks 110T and 110B, the data transmission / reception path (or data line) 130 The data input / output circuit 120 in the first group and the memory cell blocks 10T and 10B are the same or similar to the data input / output circuit 122 in the second group and the memory cell blocks 110T and 110B. between. In this case, the semiconductor memory device has a capacitance, such as a Giga-bit density, so that there is no skew between the signals of the data input / output pads of the first group 120. Similarly, there is no skew between the signals of the data input / output pads of the second group 122. More specifically, because the extremely dense semiconductor memory device package uses a package with a NON-ODIC pin layout, there is no skew \ between the signals of the data input / output pins of the package. Therefore, it is possible to operate semiconductor memory devices at very high densities at very high densities: high-speed operation is possible. 12 Please read the notice first. Binding line of this page. The size of the paper is applicable to the Chinese National Standard (CNS) Μ specification (2! 〇χ297 mm).
41041C 4537twf.doc/002 A 7 B7 五、發明説明（1 ) 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 I.--------^-------II------^ ..· 請先聞，讀背面之注意事項,-^、本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS > A4規格（210 X 297公釐）41041C 4537twf.doc / 002 A 7 B7 V. Description of the Invention (1) Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit of the present invention. Within the scope and scope, various modifications and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the appended patent application. I .-------- ^ ------- II ------ ^ .. · Please read first, read the notes on the back,-^, this page) Intellectual Property Bureau, Ministry of Economic Affairs Paper sizes printed by employee consumer cooperatives are in accordance with Chinese national standards (CNS > A4 size (210 X 297 mm)