1252490 九、發明說明： 【發明所屬之技術領域】 本發明係有關在記憶體模組中，一緩衝 模組中之至少兩個電路板中之一 於桃體 愔舻π》士 是衝裔係用於為該年 緩衝訊號 &體換組中之至少兩個電路板上之記憶體晶片 “己 【先前技術】 心城通常含有—個或多個積體電路（ic)w組，使 憶體介面而將該等晶片組叙接至記憶體模組。 在諸如中央處理單元（CPU)與記憶體模组之心 片組之間提供通訊。該記憶體介面可包括位㈣流排線曰、曰 指令訊號線及資料匯流排線。 起初，每-記憶體模組由一個一側或兩側上具有記憶體 晶片的I基板組成。然@，對高電腦效能及容量之需求的 增加導致了對更大及更快記憶體的需求。為滿足此需求， 開發了具有大體上互相平行安裳之兩個或兩個以上被電連 接的基板之單記憶體模組。美國專利第5,949,657號揭示了 此類型之記憶體模組的一實例。除了多基板記憶體模組外， 藉由在相同基板上土隹疊記憶體晶片纟增加記憶體密度。美國 專利第6,487，102號揭示了此晶片堆疊技術之一實例。 然而，隨著操作速度及記憶體模組數及/或連接至晶片組 之記憶體晶片的增加，電容負載的增加可對記憶體的量及 速度造成貫質限制。為減輕此等電容負載效應，開發了具 有一緩衝裔或暫存為以缓衝指令及位址線之記憶體模組。 此處，该杈組之母一基板包括用於減輕電容負載效應之此 95225.doc 1252490 緩衝器。此外，美目專利第6,487，1()2號提供了 — 暫存記憶體模組之一實例。 冉為 記憶體模組中之較新進展提供了全緩衝之記憶體模纪。 於-：緩衝之記憶體模組中，如與暫存記憶體模組中— 樣’綾衝與每一基板之記憶體晶片相關聯之指令及位址 2位於該模組之每一基板上的另一緩衝器緩衝資料線。據 :’全緩衝記憶體模組可將該記憶體模組與晶片組電於 i吳國專利第6,553,45G號揭示了全緩衝記憶體模: 貫例。 、〜一 【發明内容】 :據本發明之一貫施例的一實例，記憶體 -對之至少第-電路板及第二電路板， _= =第二電路板具有彼此面對之内面及彼此背離之::板 亥弟-電路板之内面與外面中之至少 數個記憶體晶片，且該第二恭玫4 ^ 叉待弟—设 一個面可支持第二複數 b 一電路板而電連接該等第體晶片。一電連接器藉由第 孚弟一歿數個記憶體晶片。將一緩衝哭 女置於第一 t路板之内面鱼 讀益 一福面/、外面中之一個面上，並為該等第 :個㈣體晶片及該等第二複數個記憶體晶片服務。 J： φ _ 中棱供了一全緩衝記憶體模組， 數〜緩衝器為該等第一複數個記 數個記憶體晶片緩衝資料及指令及位址訊號。弟—復 因此，在本發明之一告& , 緩衝。。 貝鈿例中，為整個模組提供使用 ^之全緩衝記憶體模組；因此減少了對多緩衝器= 95225.doc 1252490 連接之需求。 【實施方式】 圖1根據本發明說明了記憶體模組之一實施例的一實 例。如所示，電路板10包括中央處理單元（cpu)12&衆多槽 4每個彳s均此接收§己憶體模組20。提供了電路板丨〇及槽 14以將C P U 12電連接至安置於槽！ 4内之記憶體模組2 〇。 如圖1中所不，每個槽丨4提供一母連接器以接收記憶體模 組20之公連接部分。每—記憶體模組2()包括互相間隔開但 仍電連接並機械連接在—起的第__電路板观第二電路板 50 〇 第一電路板30具有外面32及内面34。外面32支持能形 級及綾衝器38之至少一組記憶體晶片36。第一電路 成第 板30之内面34支持能形成第二級之至少一組記憶體晶片 4〇可抗性連接器60被電附著及機械附著至第一電路板3〇 之内面34。意即’連接器6〇之外面64的一部分被機械連接 及電連接至第-電路板3G。連接器6()之内面66支持一個或 多個電連接至該處的暫存器7〇。 第一電路板50具有一外面52及一内面54。該外面支持能 形成第三級之一組記憶體晶片56，内面54亦支持能形成第 四級之一組記憶體晶片58。將連接器6〇之一部分電連接及 物理連接至第二電路板5G之内面54。—對扣件Μ亦提供第 電路板30與第二電路板5〇之間的機械連接。舉例而言， 。亥寺扣件80可為被安裝於第—電路板3()及第三電路板 通道内的柱。 如上所解釋，圖1根據本發明提供了該記憶體模組之機械 95225.doc 1252490 結構的一侧視圖。圖2說明了自第一電路板3〇之外表面32 . 的。己fe體模組20所見之一透視圖。圖3說明了自第二電路板 5〇之外表面52所見的記憶體模組2〇之另一透視圖。 其-人，將參考圖4至圖5來更詳細地描述記憶體模組之物 理結構。 圖4說明了第一電路板3〇之内表面34與第二電路板咒之 内表面54的關係圖。如圖所示，附著至第一電路板3〇之内 表面34的連接斋60包括突出部分n〇，暫存器連接於其 上。另外’連接器60之非突出部分藉由黏著劑112而物理附 著至第一電路板30之内表面34。 圖4亦展示了被物理附著至第二電路板5 〇之内表面5 4的 連接器60之末端。連接器6〇之端子％提供了至記憶體晶片 組56及58之機械連接以及電連接。下文將參考圖6來更詳細 地描述此等電連接。 圖5說明了緩衝器3 8至第一電路板3 〇之連接的物理結 構’以及連接器60至第一電路板3〇與該第二電路板％之連鲁 接。具體言之，圖5沿著圖4中所示之橫截面線v_yi提供了 5己fe體核組20之放大橫截面圖（並未按比例繪製）。如所示， 緩衝器38係電連接及物理連接至第—電路板3()。緩衝器％ 包括球栅陣列90,其焊接至第一電路板3〇之外表㈣上的 相應連接襯墊94。第-電路板3G包括導電線（未圖示），其可 電連接適當的連接襯㈣及記憶體晶片組36及4()。雖然圖5 中並未展示’但是一些導電線（未圖示）被安置於通道（未圖 . 示）内以與記憶體晶片組4〇連接。其它連接襯㈣則電料 95225.doc 1252490 至第一電路板30之終端100的端子。當將記憶體模組2〇插入 槽14内時，終端1 〇〇提供至槽丨4的電連接。 如圖5中進一步所示，外表面32上之另一些連接襯墊94 係電連接至位於第一電路板3〇之内表面34上的連接襯墊 96具體ο之，形成於第一電路板30中之通道内的導體98 完成了此電連接。將内表面34上之連接襯墊％電連接至可 挽性連接器60的連接襯墊62。將連接觀塾％及連接概塾^ 焊接在一起以在第一電路板3〇與可撓性連接器⑼之間形成 電連接及桟械連接。如圖5中所示，將位於連接器之外表 面上的一些連接襯墊62與位於連接器6〇之内表面“上的連 接襯墊68電連接。形成於貫穿連接器60之通道内的導體72 在連接襯墊62與連接襯墊68之間提供了電連接。 將暫存H7G電連接及機械連接至連接⑽。暫存器％包 括农柵陣列74，其焊接至連接概塾68中之個別的連接概 墊口此，暫存器70經由連接器60與緩衝器38電連接。 可撓性連接H6G在相對於第—電路板3()之連接㈣的末 端處提供了連接襯墊62與端子76之其它之間的一電傳導路 徑:該等端子76藉由導電線（未圖示）與記憶體晶片組56及58 電連接’ J«藉由電接點114提供了連接器6()與第二電路板別 ，間的機械附著。雖然圖5中未展示，但是該等導電線不僅 形成於第二電路板5〇之内表面54上，且亦安置於第二電路 板50之通道内（未圖示）以提供與記憶體晶片組％之電連 接因此，上述關於圖5而論述之記憶體模組的物理結構提 i、了如圖6中詳細論述的電連接。 95225.doc 1252490 圖6說明了上文關於圖1所描述之組件之間的電連接。如 所示，第一電路板30具有記憶體晶片之第一等級RC1及第 二等級RC2。第二電路板5〇具有記憶體晶片之第三等級rC3 及第四等級RC4。第一等級RC1&括被分為第一半等級36a 及第二半等級36b之記憶體晶片組36。第二等級RC2包括被 分為第一半等級40a及及第二半等級4〇b之記憶體晶片組 4 0。弟二荨級RC 3包括被分為第一半等級58a及第二半等級 58b之記憶體晶片組58。第四等級RC4包括被分為第一半等 _ 級56a及第二半等級56b之記憶體晶片組56。等級RC1-RC4 自CPU 12接收指令及位址（ca)訊號，且彼此及與cpu 12共 用資料（DQ)匯流排55。該等四個等級RC1-RC4中之一個被 各自之專級控制訊號RC而啓動，且基於c A訊號，該經啓動 之等級藉由CPU 12而在DQ匯流排55上傳達資料DQ。可將 來自CPU 12之訊號分類為兩種訊號：CA訊號及等級控制訊 號RC。一般將CA訊號提供給等，且等級控制訊 號RC係用以獨立控制每一等級之訊號。CA訊號包括ras、 φ C AS、位址訊號等，且等級控制訊號Rc包括（例如）晶片選 擇訊號CS。緩衝器38緩衝CA訊號、等級控制訊號Rc及資 料訊號DQ，且將其提供給等級RC1_RC4。具體言之，在圖 6中，CA訊號CAla、CAlb、為供應給記憶體 晶片組之各自半等級36a&4〇a、3讣及4仙、5心及56&和5化 及56b的緩衝訊號，且等級控制訊號rc丨、rc2、rc3及rc4 為分別供應給等級RC1-RC4中之每—等級的緩衝訊號。 另外，圖6展不了暫存器7〇緩衝第三與第四指令及位址訊 95225.doc 1252490 號CA2a與CA2b，且亦緩衝第三及第四等級控制訊號rC3及 RC4。圖6中亦展示了記憶體晶片組56及58之每一半等級 56a、5 8a、5 6b及58b包括與記憶體晶片組56及58的每一半 等級56a、5 8b、56b、5 8b相關聯的核對位元晶片86a、88a、 8 6b、8 8b。每一核對位元晶片86a、88a、86b及88b接收記 憶體晶片組56及58之相關聯的半等級的相同指令及位址訊 號C A，以及輸入或輸出核對位元資料。舉例而言，核對位 元晶片86a及88a接收核對位元資料cb〇-CB7，而核對位元 晶片8613及8 813則接收核對位元資料(：38-(：：]315。此核對位元 資料作為資料訊號DQ之一部分接收。 如由圖2所論證，記憶體模組2〇提供一全緩衝記憶體模 組。在此實施例中，單緩衝器38為第一電路板3〇及第二電 路板50上之記憶體晶片組提供了對資料訊號與指令及位址 訊號的緩衝。 因此，雖然對本發明進行了描述，但是應明白，可以多 種方式對相同的物進行改變。並不將此等變化視為背離了 本發明之精神及範疇，且對熟習此項技術者而言將變得顯 而易見之所有此等修改意欲包括於本發明之範疇内。 【圖式簡單說明】 圖1根據本發明說明了一記憶體模組之一實施例的一實 例； 圖2及圖3說明了圖丨中之記憶體模組的透視圖。 圖4說明了圖1之記憶體模組中之第一電路板之内表面及 第二電路板之内表面的關係圖；及 95225.doc -12- 1252490 一電路板之連接的物理結構，以及 一電路板與第二電路板之間一連 圖5說明了緩衝器至第 圖1之記憶體模組中的第 接器的連接； 圖6說明了圖1中之記憶體模組的組件之間的電連接。 【主要元件符號說明】 10 電路板 12 中央處理單元（CPU) 14 槽 20 記憶體模組 30 第一電路板 32 外面 34 内面 36 記憶體晶片 38 緩衝器 40a 第一半等級 40b 第二半等級 40 記憶體晶片 50 第二電路板 52 外面 54 内面 55 資料匯流排 56a 第一半等級 56b 第二半等級 56 記憶體晶片 95225.doc -13- 第一半等級 第二半等級 記憶體晶片 可撓性連接器 連接襯墊 外面 内面 連接襯墊 φ 暫存器 導體 球柵陣列 端子 扣件 核對位元晶片 核對位元晶片 核對位元晶片 鲁 核對位元晶片 球柵陣列 連接襯墊 連接襯墊 導體 終端 突出部分 黏著劑 -14- 114 1252490 CAla，CAlb， CA2a，CA2b CAs1252490 IX. Description of the Invention: [Technical Field] The present invention relates to a memory module in which at least one of at least two circuit boards in a buffer module is in a peach body For the memory chip of at least two boards on the buffering signal & body switching group for the year "Previous technology" Heart City usually contains one or more integrated circuits (ic) w group, so that The set of chips is connected to the memory module. The communication is provided between a core unit such as a central processing unit (CPU) and a memory module. The memory interface may include a bit (four) stream line 曰, 曰 command signal line and data bus line. Initially, each memory module consists of an I substrate with a memory chip on one or both sides. However, the increase in demand for high computer performance and capacity leads to In order to meet this demand, a single memory module having two or more electrically connected substrates substantially parallel to each other has been developed. U.S. Patent No. 5,949,657 Reveal this type of note An example of a bulk module. In addition to a multi-substrate memory module, memory density is increased by stacking memory chips on the same substrate. An example of this wafer stacking technique is disclosed in U.S. Patent No. 6,487,102. However, as the operating speed and the number of memory modules and/or the number of memory chips connected to the chipset increase, the increase in capacitive load can impose a quality limit on the amount and speed of the memory. To alleviate these capacitive loads. The effect is to develop a memory module with a buffered or temporarily stored buffer instruction and address line. Here, the mother substrate of the group includes the 95225.doc 1252490 buffer for reducing the capacitive loading effect. In addition, U.S. Patent No. 6,487,1 () No. 2 provides an example of a temporary memory module. 提供 Provides a fully buffered memory model for newer developments in memory modules. -: in the buffered memory module, such as in the temporary memory module, the instructions associated with the memory chip of each substrate and the address 2 are located on each substrate of the module. Another buffer buffer According to the fact that the 'full buffer memory module can electrically charge the memory module and the chipset to the U.S. Patent No. 6,553,45G to disclose the full buffer memory model: a case example. According to an embodiment of the consistent embodiment of the present invention, the memory - for at least the first circuit board and the second circuit board, _ = = the second circuit board has an inner surface facing each other and away from each other:: board Haidi - At least a plurality of memory chips on the inner surface of the circuit board and the outer surface, and the second surface of the circuit board supports a second plurality b circuit board to electrically connect the first body wafers. The connector uses a memory chip of Difudi. A buffering crying woman is placed inside the first t-board, and the fish is read on the surface of the Yifufu/, on the outside, and for the first: (4) body wafers and the second plurality of memory chip services. J: φ _ The middle edge provides a full buffer memory module, and the number ~ buffer is the first plurality of memory chip buffer data and command and address signals. The younger-following, therefore, in one of the present inventions, & . In the case of Bessie, the entire module is provided with a fully buffered memory module; thus reducing the need for a multi-buffer = 95225.doc 1252490 connection. [Embodiment] FIG. 1 illustrates an embodiment of an embodiment of a memory module in accordance with the present invention. As shown, the circuit board 10 includes a central processing unit (cpu) 12 & a plurality of slots 4 each receiving a § memory module 20 . A circuit board and slot 14 are provided to electrically connect the C P U 12 to the slot! 4 memory module 2 〇. As shown in Figure 1, each slot 4 provides a female connector to receive the male connector portion of the memory module 20. Each of the memory modules 2 () includes a second circuit board 50 that is spaced apart from each other but is still electrically connected and mechanically connected. The first circuit board 30 has an outer surface 32 and an inner surface 34. The outer face 32 supports at least one set of memory chips 36 of the energy level and buffer 38. The first circuit, the inner face 34 of the first board 30, supports at least one set of memory chips capable of forming a second stage. The resistive connector 60 is electrically and mechanically attached to the inner face 34 of the first circuit board 3''. That is, a part of the outer face 64 of the connector 6 is mechanically and electrically connected to the first circuit board 3G. The inner face 66 of the connector 6() supports one or more registers 7 that are electrically connected thereto. The first circuit board 50 has an outer surface 52 and an inner surface 54. The outer support can form a memory chip 56 of the third stage, and the inner surface 54 also supports the formation of a memory chip 58 of the fourth stage. One of the connectors 6 is electrically and physically connected to the inner face 54 of the second circuit board 5G. - A mechanical connection between the first circuit board 30 and the second circuit board 5A is also provided for the fasteners. For example, . The Hai Temple fastener 80 can be a post that is mounted in the first circuit board 3 () and the third circuit board channel. As explained above, Figure 1 provides a side view of the mechanical 95225.doc 1252490 structure of the memory module in accordance with the present invention. Figure 2 illustrates the surface 32 from the first circuit board 3 . A perspective view of the body module 20 as seen. Figure 3 illustrates another perspective view of the memory module 2 seen from the outer surface 52 of the second circuit board 5. The physical structure of the memory module will be described in more detail with reference to Figs. 4 through 5. Figure 4 illustrates a relationship of the inner surface 34 of the first circuit board 3 to the inner surface 54 of the second circuit board. As shown, the connection 60 attached to the inner surface 34 of the first circuit board 3 includes a protruding portion n〇 to which the register is attached. Further, the non-protruding portion of the connector 60 is physically attached to the inner surface 34 of the first circuit board 30 by the adhesive 112. Figure 4 also shows the end of the connector 60 physically attached to the inner surface 54 of the second circuit board 5 . The terminal % of the connector 6 provides mechanical and electrical connections to the memory chipsets 56 and 58. These electrical connections will be described in more detail below with reference to FIG. Figure 5 illustrates the physical structure of the connection of the buffer 38 to the first circuit board 3 and the connection of the connector 60 to the first circuit board 3A and the second circuit board %. In particular, Figure 5 provides an enlarged cross-sectional view of the five-body core set 20 (not drawn to scale) along the cross-sectional line v_yi shown in Figure 4. As shown, the buffer 38 is electrically and physically connected to the first circuit board 3 (). The buffer % includes a ball grid array 90 that is soldered to a corresponding connection pad 94 on the top (4) of the first circuit board 3. The first circuit board 3G includes conductive wires (not shown) that can electrically connect the appropriate connection pads (4) and the memory chip groups 36 and 4(). Although not shown in Fig. 5, some conductive lines (not shown) are disposed in the channels (not shown) to be connected to the memory chip set 4A. The other connection lining (4) is the material 95225.doc 1252490 to the terminal of the terminal 100 of the first circuit board 30. When the memory module 2 is inserted into the slot 14, the terminal 1 is provided with an electrical connection to the slot 4. As further shown in FIG. 5, other connection pads 94 on the outer surface 32 are electrically connected to the connection pads 96 on the inner surface 34 of the first circuit board 3, specifically formed on the first circuit board. The conductor 98 in the channel in 30 completes this electrical connection. The connection pads on the inner surface 34 are electrically connected to the connection pads 62 of the slidable connector 60. The connection view % and the connection profile ^ are soldered together to form an electrical connection and a mechanical connection between the first circuit board 3'' and the flexible connector (9). As shown in FIG. 5, some of the connection pads 62 on the outer surface of the connector are electrically connected to the connection pads 68 on the inner surface of the connector 6's. Formed in the passage through the connector 60. The conductor 72 provides an electrical connection between the connection pad 62 and the connection pad 68. The temporary storage H7G is electrically and mechanically connected to the connection (10). The register % includes an agricultural grid array 74 which is soldered to the connection profile 68 The individual connections are the pads, and the register 70 is electrically connected to the buffer 38 via the connector 60. The flexible connection H6G provides a connection pad at the end of the connection (4) with respect to the first board 3() An electrically conductive path between 62 and the other of terminals 76: the terminals 76 are electrically coupled to the memory chipsets 56 and 58 by conductive wires (not shown). The connectors are provided by electrical contacts 114. 6() is mechanically attached to the second circuit board. Although not shown in FIG. 5, the conductive lines are formed not only on the inner surface 54 of the second circuit board 5 but also on the second circuit board. Within 50 channels (not shown) to provide an electrical connection to the memory chipset %, The physical structure of the memory module discussed with respect to Figure 5 provides an electrical connection as discussed in detail in Figure 6. 95225.doc 1252490 Figure 6 illustrates the electrical connections between the components described above with respect to Figure 1. As shown, the first circuit board 30 has a first level RC1 and a second level RC2 of the memory chip. The second circuit board 5 has a third level rC3 and a fourth level RC4 of the memory chip. The first level RC1 & The memory chip set 36 is divided into a first half level 36a and a second half level 36b. The second level RC2 includes a memory chip set divided into a first half level 40a and a second half level 4〇b. 40. The second level RC 3 includes a memory chip group 58 divided into a first half level 58a and a second half level 58b. The fourth level RC4 includes a first half class _ level 56a and a second half. Memory chip set 56 of level 56b. Levels RC1-RC4 receive command and address (ca) signals from CPU 12, and share data (DQ) bus bars 55 with each other and with cpu 12. These four levels RC1-RC4 One of which is activated by a respective dedicated control signal RC, and based on the c A signal, the activated level is borrowed The CPU 12 communicates the data DQ on the DQ bus 55. The signals from the CPU 12 can be classified into two types of signals: a CA signal and a level control signal RC. The CA signal is generally provided to the like, and the level control signal RC is used. The signal of each level is independently controlled. The CA signal includes ras, φ C AS, address signal, etc., and the level control signal Rc includes, for example, a wafer selection signal CS. The buffer 38 buffers the CA signal, the level control signal Rc, and the data signal. DQ and provide it to level RC1_RC4. Specifically, in FIG. 6, the CA signals CAla, CAlb are buffers supplied to the respective half-levels 36a & 4〇a, 3讣 and 4, 5 and 56 & and 5 and 56b of the memory chip set. The signal, and the level control signals rc丨, rc2, rc3, and rc4 are buffer signals for each of the levels RC1-RC4, respectively. In addition, FIG. 6 does not display the third and fourth commands and address addresses 95225.doc 1252490, CA2a and CA2b, and also buffers the third and fourth level control signals rC3 and RC4. Also shown in FIG. 6 is that each of the half levels 56a, 58a, 56b, and 58b of the memory chip sets 56 and 58 are associated with each of the half levels 56a, 58b, 56b, 58b of the memory chip sets 56 and 58. The check bit wafers 86a, 88a, 8 6b, 8 8b. Each of the check bit wafers 86a, 88a, 86b, and 88b receives the associated half-level identical command and address signal C A of the memory chip sets 56 and 58, and the input or output check bit data. For example, the check bit wafers 86a and 88a receive the check bit data cb〇-CB7, and the check bit cells 8613 and 8 813 receive the check bit data (: 38-(::] 315. This check bit The data is received as part of the data signal DQ. As demonstrated by Figure 2, the memory module 2 provides a fully buffered memory module. In this embodiment, the single buffer 38 is the first circuit board 3 and the first The memory chip set on the two boards 50 provides buffering of data signals and commands and address signals. Accordingly, while the invention has been described, it should be understood that the same items may be modified in various ways. Such changes are considered to be within the spirit and scope of the present invention, and all such modifications as would become apparent to those skilled in the art are intended to be included within the scope of the present invention. The present invention illustrates an example of an embodiment of a memory module; Figures 2 and 3 illustrate perspective views of the memory module of the Figure. Figure 4 illustrates the first of the memory modules of Figure 1. The inner surface of a circuit board and a relationship diagram of the inner surface of the second circuit board; and 95225.doc -12- 1252490 a physical structure of the connection of the circuit board, and a connection between a circuit board and the second circuit board, FIG. 5 illustrates the buffer to the first FIG. Figure 8 illustrates the electrical connection between the components of the memory module of Figure 1. [Main component symbol description] 10 Circuit board 12 Central Processing Unit (CPU) 14 Slot 20 Memory Module 30 First Circuit Board 32 Outer Surface 34 Inner Surface 36 Memory Chip 38 Buffer 40a First Half Level 40b Second Half Level 40 Memory Chip 50 Second Circuit Board 52 Outer Surface 54 Inner Surface 55 Data Bus 56a First half level 56b second half level 56 memory chip 95225.doc -13- first half level second half level memory chip flexible connector connection pad outer inner surface connection pad φ register conductor ball grid Array terminal fastener check bit wafer wafer check bit wafer check bit wafer wafer nuclear check bit wafer ball grid array connection pad connection pad conductor terminal protruding part adhesive-14- 114 1252490 CAla, CAlb, CA2a, CA2b CAs
DQ RC1 RC2 RC3 RC4 RCs v-v， 電接點 指令及位址 指令及位址訊號 傳遞資料 第一等級 第二等級 第三等級 第四等級 等級控制訊號 橫截面線 95225.doc - 15-DQ RC1 RC2 RC3 RC4 RCs v-v, electrical contact command and address command and address signal transfer data first level second level third level fourth level level control signal cross section line 95225.doc - 15-