JPS6193694A - Ic device - Google Patents
Ic deviceInfo
- Publication number
- JPS6193694A JPS6193694A JP21541684A JP21541684A JPS6193694A JP S6193694 A JPS6193694 A JP S6193694A JP 21541684 A JP21541684 A JP 21541684A JP 21541684 A JP21541684 A JP 21541684A JP S6193694 A JPS6193694 A JP S6193694A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- memory element
- terminal
- terminals
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電子機器に用いられる集積回路装置に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an integrated circuit device used in electronic equipment.
従来例の構成とその問題点
近年、集積回路素子は、さまざまな電子t、5.器:て
用いらnている。また機器の複雑化に序ない、より高ど
度の実装が要求されている。Conventional configurations and their problems In recent years, integrated circuit devices have been developed using various types of electronics, 5. Container: Used. Furthermore, as equipment becomes more complex, more sophisticated implementation is required.
以下に従来の集積回路素子の実装について、図面を参照
しながら説明する。The mounting of conventional integrated circuit elements will be described below with reference to the drawings.
第1図は、プリント基板の両面にメモリ素子を実装する
場合のメモリ素子間の配線ヲ示すものである。FIG. 1 shows wiring between memory elements when memory elements are mounted on both sides of a printed circuit board.
第1図において、1,4はメモリ素子、2はメモリ素子
1のアドレス信号巌、であり、3はメモリ素子1を実装
し、回路を構成するプリント基板である。なおこの第1
図においてはメモリ素子1..4は、結線をわかりやす
く図解するためにプリント基板3の上方および下方に浮
かして描かnでいるが、実際にはプリント基板3の表面
および裏面に実装するものである。In FIG. 1, 1 and 4 are memory elements, 2 is an address signal of the memory element 1, and 3 is a printed circuit board on which the memory element 1 is mounted and constitutes a circuit. Note that this first
In the figure, memory element 1. .. 4 is drawn floating above and below the printed circuit board 3 in order to easily illustrate the wiring connections, but it is actually mounted on the front and back surfaces of the printed circuit board 3.
このようにメモリ素子を複数個用いて、メモリ回路を構
する場合、通常アドレス信号源2はすべて並列に接線
する。すなわち第1図において、例えば端子番号1,2
,3.4’iそ几ぞれアドレス信号端子とするとプリン
ト基板3の表[雨のメモリ素子1の1端子から、裏面の
メモリ素子4の1端子へ結線し、プリント基板3の異語
のメモリ素子1の2端子からプリント基板3の裏面のメ
モリ素子4の2端子へ結勝し、以下同様に3端子と3端
子、4端子と4端子をそれぞn結線する。When a memory circuit is constructed using a plurality of memory elements in this manner, all address signal sources 2 are normally connected in parallel and tangentially. That is, in FIG. 1, for example, terminal numbers 1 and 2
, 3.4'i respectively as address signal terminals, connect one terminal of the memory element 1 on the front side of the printed circuit board 3 to one terminal of the memory element 4 on the back side, and Wires are made from two terminals of the memory element 1 to two terminals of the memory element 4 on the back surface of the printed circuit board 3, and in the same way, 3 terminals are connected to 3 terminals, and 4 terminals are connected to 4 terminals, respectively.
しかし上記のような方法では、アドレス信号勝2どうし
が交差するため、実装密度があがらないまた配線長が長
くなるという欠点を有していた。However, in the above method, since the address signals W2 intersect with each other, the packaging density cannot be increased and the wiring length becomes long.
発明の目的
本発明は、前記欠点に鑑み、プリント基板の表面および
裏面に実装した集積回路素子において、同一機能を持つ
端子どうしを互いに接続する場合その配線が互いに交差
すること なくし、高密度実装が可能でまたその配線長
も最短となる集積回路装置を提供するものである。Purpose of the Invention In view of the above-mentioned drawbacks, the present invention provides a method for high-density mounting by eliminating the need for wiring to cross each other when terminals having the same function are connected to each other in integrated circuit elements mounted on the front and back surfaces of a printed circuit board. The present invention provides an integrated circuit device that has the shortest wiring length possible.
発明の構成
この目的を達成するために本考案は第1の集積回路素子
の端子配線を第2の集積回路素子の端子配列とを鏡像の
関係に構成したものである。Structure of the Invention In order to achieve this object, the present invention configures the terminal wiring of the first integrated circuit element in a mirror image relationship with the terminal arrangement of the second integrated circuit element.
実姉例の説明
以下本考案の一実殉例について、図面を参照しながら説
明する。Description of a practical example A practical example of the present invention will be described below with reference to the drawings.
第2図において、11はメモリ素子、12はアドレス信
号線、13はプリント基板であり、これらは前記第1図
において、1,2..3でそnぞれ示したものと同じで
ある。また14はその端子配列がメモリ素子11と鏡像
の関係にあり、メモリ素子11と同等の機能を持つメモ
リ素子である。In FIG. 2, 11 is a memory element, 12 is an address signal line, and 13 is a printed circuit board, which are the same as 1, 2, . .. These are the same as those shown in 3. Further, 14 is a memory element whose terminal arrangement is a mirror image of the memory element 11 and has the same function as the memory element 11.
この実姉例において、メモリ素子11と集積回路素子1
4において、同一の機能を持つ端子どうしを互に接続す
る場合、メモリ素子11と集積回路素子14は、その端
子が互に鏡像の関係にあるため、メモリ素子1の端子1
と集積回路素子4の端子16が同一機能をもち、以下同
様にメモリ素子1の端子2と集積回路素子4の端子15
、メモリ素子1の端子3と集積回路素子4の端子14、
メモリ素子1の端子4と集積回路素子4の端子13が同
一機能を侍つことになる。これらの同一機能をもつ端子
どうしを接続するとき、第2図より明らかなようにその
接続線であるアドレス信号線2は互に交差しない。In this example, a memory element 11 and an integrated circuit element 1
4, when terminals having the same function are connected to each other, the terminals of the memory element 11 and the integrated circuit element 14 are mirror images of each other.
and terminal 16 of integrated circuit element 4 have the same function, and similarly, terminal 2 of memory element 1 and terminal 15 of integrated circuit element 4 have the same function.
, terminal 3 of memory element 1 and terminal 14 of integrated circuit element 4,
Terminal 4 of memory element 1 and terminal 13 of integrated circuit element 4 serve the same function. When these terminals having the same function are connected to each other, as is clear from FIG. 2, the address signal lines 2, which are the connection lines, do not cross each other.
し友がって配線長を短く、しかも実装苦度金上げること
ができる。As a result, the wiring length can be shortened and the mounting difficulty can be increased.
なお上記実姉例はメモリ素子を用いたものであったが、
集積回路である限り他の素子にも適用することができる
。また、プリント基板13の表面裏面の両面に集積回路
素子を設ける場合に限らず、一方の面に近接させて用い
る場合にも同様の効果を得ることができる。Note that the actual sister example above used a memory element, but
It can also be applied to other devices as long as they are integrated circuits. Moreover, the same effect can be obtained not only when the integrated circuit element is provided on both the front and back surfaces of the printed circuit board 13, but also when it is used close to one surface.
発明の効果
以上の説明から明らかなように本発明によ扛は第1の集
積回路素子の端子配列と鏡1象の関係にある端子配列を
有する第2の集積回路素子パッケージを設は画素子を近
接させて用いる場合、もしくはプリント基板の両面に実
装して用いる場合その配線を互いに交差させることなく
各々の集積回路素子において同一機能を持つ端子を互に
接続することができる。この結果、高密度実装が可能で
ありまたその配線長が最短になるためその効果は大なる
ものがある。Effects of the Invention As is clear from the above description, the present invention provides a second integrated circuit element package having a terminal arrangement mirror-like with the terminal arrangement of the first integrated circuit element. When used in close proximity to each other or mounted on both sides of a printed circuit board, terminals having the same function in each integrated circuit element can be connected to each other without having their wiring cross each other. As a result, high-density packaging is possible and the wiring length is minimized, which has great effects.
第1図は従来の集積回路装置の分解斜視図、第2図は本
発明の一実癩例による集積回路装置の分解斜視図である
。
11.14・・・・・メモリ素子、12・・・・・・ア
ドレス信号勝、3・・・・・・プリント基板。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図
第2図FIG. 1 is an exploded perspective view of a conventional integrated circuit device, and FIG. 2 is an exploded perspective view of an integrated circuit device according to an embodiment of the present invention. 11.14...Memory element, 12...Address signal win, 3...Printed circuit board. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2
Claims (2)
子配列と鏡像の関係にある端子配列を有する第2の集積
回路とを有し、上記第1、第2の集積回路を同一プリン
ト基板に実装したことを特徴とする集積回路装置。(1) having a first integrated circuit element and a second integrated circuit having a terminal arrangement that is a mirror image of the terminal arrangement of the first integrated circuit; An integrated circuit device characterized by being mounted on the same printed circuit board.
2の集積回路を他方の面に実装したことを特徴とする特
許請求の範囲第1項記載の集積回路装置。(2) The integrated circuit device according to claim 1, wherein the first integrated circuit is mounted on one side of a printed circuit board and the second integrated circuit is mounted on the other side.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21541684A JPS6193694A (en) | 1984-10-15 | 1984-10-15 | Ic device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21541684A JPS6193694A (en) | 1984-10-15 | 1984-10-15 | Ic device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6193694A true JPS6193694A (en) | 1986-05-12 |
Family
ID=16671968
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21541684A Pending JPS6193694A (en) | 1984-10-15 | 1984-10-15 | Ic device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6193694A (en) |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6327053U (en) * | 1986-08-07 | 1988-02-22 | ||
JPS63296292A (en) * | 1987-05-27 | 1988-12-02 | Mitsubishi Electric Corp | Semiconductor device |
WO1999024896A1 (en) * | 1997-11-06 | 1999-05-20 | Hitachi, Ltd. | Information processor |
JP2014027216A (en) * | 2012-07-30 | 2014-02-06 | Renesas Electronics Corp | Semiconductor device and manufacturing method of the same |
JP2014528650A (en) * | 2011-10-03 | 2014-10-27 | インヴェンサス・コーポレイション | Stub minimization for multi-die wire bond assemblies with orthogonal windows |
JP2014528652A (en) * | 2011-10-03 | 2014-10-27 | インヴェンサス・コーポレイション | Stub minimization by offsetting the terminal grid from the center of the package |
JP2014535165A (en) * | 2011-10-03 | 2014-12-25 | インヴェンサス・コーポレイション | Minimizing stubs in assemblies without wire bonds to the package substrate |
WO2016068264A1 (en) * | 2014-10-31 | 2016-05-06 | 川崎重工業株式会社 | Control circuit board and robot control device |
US9460758B2 (en) | 2013-06-11 | 2016-10-04 | Invensas Corporation | Single package dual channel memory with co-support |
US9679838B2 (en) | 2011-10-03 | 2017-06-13 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
US9679613B1 (en) | 2016-05-06 | 2017-06-13 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
US9679876B2 (en) | 2011-10-03 | 2017-06-13 | Invensas Corporation | Microelectronic package having at least two microelectronic elements that are horizontally spaced apart from each other |
US10026467B2 (en) | 2015-11-09 | 2018-07-17 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
US10032752B2 (en) | 2011-10-03 | 2018-07-24 | Invensas Corporation | Microelectronic package having stub minimization using symmetrically-positioned duplicate sets of terminals for wirebond assemblies without windows |
-
1984
- 1984-10-15 JP JP21541684A patent/JPS6193694A/en active Pending
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6327053U (en) * | 1986-08-07 | 1988-02-22 | ||
JPS63296292A (en) * | 1987-05-27 | 1988-12-02 | Mitsubishi Electric Corp | Semiconductor device |
WO1999024896A1 (en) * | 1997-11-06 | 1999-05-20 | Hitachi, Ltd. | Information processor |
US9679838B2 (en) | 2011-10-03 | 2017-06-13 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
US10090280B2 (en) | 2011-10-03 | 2018-10-02 | Invensas Corporation | Microelectronic package including microelectronic elements having stub minimization for wirebond assemblies without windows |
JP2014528652A (en) * | 2011-10-03 | 2014-10-27 | インヴェンサス・コーポレイション | Stub minimization by offsetting the terminal grid from the center of the package |
JP2014534624A (en) * | 2011-10-03 | 2014-12-18 | インヴェンサス・コーポレイション | Stub minimization of multi-die wirebond assemblies with parallel windows |
JP2014535165A (en) * | 2011-10-03 | 2014-12-25 | インヴェンサス・コーポレイション | Minimizing stubs in assemblies without wire bonds to the package substrate |
JP2015502652A (en) * | 2011-10-03 | 2015-01-22 | インヴェンサス・コーポレイション | Minimizing stubs in assemblies without wire bonds to the package substrate |
US10692842B2 (en) | 2011-10-03 | 2020-06-23 | Invensas Corporation | Microelectronic package including microelectronic elements having stub minimization for wirebond assemblies without windows |
US10643977B2 (en) | 2011-10-03 | 2020-05-05 | Invensas Corporation | Microelectronic package having stub minimization using symmetrically-positioned duplicate sets of terminals for wirebond assemblies without windows |
JP2014528650A (en) * | 2011-10-03 | 2014-10-27 | インヴェンサス・コーポレイション | Stub minimization for multi-die wire bond assemblies with orthogonal windows |
US10032752B2 (en) | 2011-10-03 | 2018-07-24 | Invensas Corporation | Microelectronic package having stub minimization using symmetrically-positioned duplicate sets of terminals for wirebond assemblies without windows |
US9679876B2 (en) | 2011-10-03 | 2017-06-13 | Invensas Corporation | Microelectronic package having at least two microelectronic elements that are horizontally spaced apart from each other |
JP2014027216A (en) * | 2012-07-30 | 2014-02-06 | Renesas Electronics Corp | Semiconductor device and manufacturing method of the same |
US9460758B2 (en) | 2013-06-11 | 2016-10-04 | Invensas Corporation | Single package dual channel memory with co-support |
CN107107341A (en) * | 2014-10-31 | 2017-08-29 | 川崎重工业株式会社 | Control circuitry substrate and robot controller |
US10251275B2 (en) | 2014-10-31 | 2019-04-02 | Kawasaki Jukogyo Kabushiki Kaisha | Control circuit board and robot control device |
CN107107341B (en) * | 2014-10-31 | 2020-03-03 | 川崎重工业株式会社 | Control circuit substrate and robot control device |
JP2016092111A (en) * | 2014-10-31 | 2016-05-23 | 川崎重工業株式会社 | Control circuit board and robot control device |
WO2016068264A1 (en) * | 2014-10-31 | 2016-05-06 | 川崎重工業株式会社 | Control circuit board and robot control device |
US10026467B2 (en) | 2015-11-09 | 2018-07-17 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
US9679613B1 (en) | 2016-05-06 | 2017-06-13 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
US9928883B2 (en) | 2016-05-06 | 2018-03-27 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
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